Re: [PATCH 3/3 v2] powerpc/mpic: FSL MPIC error interrupt support.

From: Scott Wood <scottwood@freescale.com>
To: Kumar Gala <galak@kernel.crashing.org>
Cc: Bogdan Hamciuc <bogdan.hamciuc@freescale.com>,
	Varun Sethi <Varun.Sethi@freescale.com>,
	linuxppc-dev@lists.ozlabs.org
Subject: Re: [PATCH 3/3 v2] powerpc/mpic: FSL MPIC error interrupt support.
Date: Mon, 9 Jul 2012 15:22:32 -0500	[thread overview]
Message-ID: <4FFB3D88.6030106@freescale.com> (raw)
In-Reply-To: <62D13F27-5E39-450E-953D-102DCA32AA9D@kernel.crashing.org>

On 07/09/2012 02:03 PM, Kumar Gala wrote:
> 
> On Jul 9, 2012, at 3:47 AM, Varun Sethi wrote:
> 
>> +int mpic_err_int_init(struct mpic *mpic, irq_hw_number_t irqnum)
>> +{
> 
> Why can't we do this during mpic_init() time?

Are you willing to hardcode that IRQ 16 is the error interrupt, without
waiting to see an intspec?

>> +	ret = request_irq(virq, fsl_error_int_handler, IRQF_NO_THREAD,
>> +		    "mpic-error-int", mpic);
> 
> Hmm, should we be using irq_set_chained_handler() instead of request_irq

As I said last time, "that's how Varun initially did it and I asked him
to change it, because it gets a lot trickier to get things right, and I
didn't see what it was buying us."  That original patch had locking
problems as a result.

Using the chained handler mechanism puts the responsibility on us to do
a lot of the generic stuff that's already perfectly well implemented in
generic code.  We're implementing a cascade, not a new flow.

-Scott