From mboxrd@z Thu Jan  1 00:00:00 1970
From: Marek Vasut <marex@denx.de>
Date: Tue, 26 Sep 2017 12:30:27 +0200
Subject: [U-Boot] [PATCH v2 02/19] doc: dtbinding: Description on FPGA
 RBF properties at Arria 10 FPGA manager
In-Reply-To: <1506416078.27760.30.camel@intel.com>
References: <1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>
 <1506328815-23733-3-git-send-email-tien.fong.chee@intel.com>
 <1090da36-ef39-8ff1-b8b8-42415bad8a9e@denx.de>
 <1506416078.27760.30.camel@intel.com>
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On 09/26/2017 10:54 AM, Chee, Tien Fong wrote:
> On Isn, 2017-09-25 at 11:00 +0200, Marek Vasut wrote:
>> On 09/25/2017 10:39 AM, tien.fong.chee at intel.com wrote:
>>>
>>> From: Tien Fong Chee <tien.fong.chee@intel.com>
>>>
>>> This patch adds description on properties about location of FPGA
>>> RBFs are
>>> stored, type and functionality of RBF used to configure FPGA.
>>>
>>> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
>> Why does this patch have different tags than 1/19 ? Please keep
>> things
>> consistent ...
>>
> Not get you. What's you means for tags?

ARM: socfpga: , not the random doc: dtbinding: .
Heck, the first and second patch change the same file, yet have
different tags, why ?

>>> ---
>>>  doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt | 11
>>> +++++++++++
>>>  1 file changed, 11 insertions(+)
>>>
>>> diff --git a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-
>>> mgr.txt b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-
>>> mgr.txt
>>> index 2fd8e7a..7abb746 100644
>>> --- a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
>>> +++ b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
>>> @@ -7,6 +7,14 @@ Required properties:
>>>                 - The second index is for writing FPGA
>>> configuration data.
>>>  - resets     : Phandle and reset specifier for the device's reset.
>>>  - clocks     : Clocks used by the device.
>>> +- bitstream_periph : FPGA peripheral raw binary file which is used
>>> to
>>> +                     initialize FPGA IOs, PLL, IO48 and DDR.
>>> +- bitstream_core : FPGA core raw binary file contains FPGA design
>>> which is used
>>> +                   to program FPGA CRAM and ERAM.
>>> +- bitstream_devpart : Partition of flash device where bitstream
>>> files are
>>> +		       stored.
>>> +                      <dev[:part]> - dev is flash device number,
>>> part is flash
>>> +                                     device partition.
>>>  
>>>  Example:
>>>  
>>> @@ -16,4 +24,7 @@ Example:
>>>  		       0xffcfe400 0x20>;
>>>  		clocks = <&l4_mp_clk>;
>>>  		resets = <&rst FPGAMGR_RESET>;
>>> +		bitstream_periph =
>>> "ghrd_10as066n2.periph.rbf.mkimage";
>>> +		bitstream_core =
>>> "ghrd_10as066n2.core.rbf.mkimage";
>>> +		bitstream_devpart = "0:1";
>>>  	};
>>>


-- 
Best regards,
Marek Vasut