From mboxrd@z Thu Jan 1 00:00:00 1970 From: Alexandre Torgue Subject: Re: [PATCH 0/2] pinctrl: stm32: add suspend/resume management Date: Fri, 24 May 2019 14:26:19 +0200 Message-ID: <4a35e070-b18a-e0f5-76b6-72054eb98b43@st.com> References: <1557474150-19618-1-git-send-email-alexandre.torgue@st.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org To: Linus Walleij , Benjamin Gaignard Cc: Maxime Coquelin , "linux-kernel@vger.kernel.org" , "open list:GPIO SUBSYSTEM" , Linux ARM , linux-stm32@st-md-mailman.stormreply.com List-Id: linux-gpio@vger.kernel.org On 5/24/19 1:24 PM, Linus Walleij wrote: > On Fri, May 10, 2019 at 9:42 AM Alexandre Torgue > wrote: > >> During power sequence, GPIO hardware registers could be lost if the power >> supply is switched off. Each device using pinctrl API is in charge of >> managing pins during suspend/resume sequences. But for pins used as gpio or >> irq stm32 pinctrl driver has to save the hardware configuration. >> Each register will be saved at runtime and restored during resume sequence. > > Both patches applied. > > On the same pinctrl devel branch is also Benjamin's patches to support > the "link_consumers" property on the pin controller descriptor to > enable links from pin control consumers back to their pin controller > suppliers, especially important for STMFX. > > Would you please check if it work fine if you turn on this feature > for the SoC STM32 pin controller? > Sure. Either today or next Monday. I let you know. regards Alex > I am working a bit on refining the patches, so I want to enable testing > with some SoC pin controllers as well and possibly make the > behavior default. > > Yours, > Linus Walleij > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.1 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4E121C282E3 for ; Fri, 24 May 2019 12:26:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2545420868 for ; Fri, 24 May 2019 12:26:33 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=st.com header.i=@st.com header.b="UBkDOjp+" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2391513AbfEXM0c (ORCPT ); Fri, 24 May 2019 08:26:32 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:6870 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S2391299AbfEXM0c (ORCPT ); Fri, 24 May 2019 08:26:32 -0400 Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx08-00178001.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x4OCJ6Hq021165; Fri, 24 May 2019 14:26:21 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=st.com; h=subject : to : cc : references : from : message-id : date : mime-version : in-reply-to : content-type : content-transfer-encoding; s=STMicroelectronics; bh=MRkkLHdMQA+fa243SgLqmgSMuMqZksxq6zRTMMLwqTI=; b=UBkDOjp+86RcHTz7CrpA0k7LNC39DmwaTk3HVvoWoQGecrJtUjcvL29dWEKfb/b/sJgW qXPr18nlCniLI3rhEv4fCjUGz/9rNmlf6HeEwh3gEwxrNcSSJVcSSueBDcH1JVgmmFCT VWhdz34tvJpQLziQRDBJXlzWz3Q7g0D5ZMbAhL9v3MVnqAdC/IBzGyHRO/hoJmYsmO9b pgsVSILuEZvytnIPiBXjxUhdLNqkUxIxxkyLJLNcvbaPB7+U9nHiZKgwLf43Ialw9uJP QeOUiNJBLqyWdvOfSzReKN7Hsgd/oo9z9p4262dpW1KPVXLUSsAiRoaOHxGAJtJuCOlK BA== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-00178001.pphosted.com with ESMTP id 2sj774nmu5-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Fri, 24 May 2019 14:26:21 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 23DA034; Fri, 24 May 2019 12:26:21 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag3node2.st.com [10.75.127.8]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id EEDDD2BCC; Fri, 24 May 2019 12:26:20 +0000 (GMT) Received: from [10.48.0.204] (10.75.127.50) by SFHDAG3NODE2.st.com (10.75.127.8) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Fri, 24 May 2019 14:26:20 +0200 Subject: Re: [PATCH 0/2] pinctrl: stm32: add suspend/resume management To: Linus Walleij , Benjamin Gaignard CC: Maxime Coquelin , "linux-kernel@vger.kernel.org" , "open list:GPIO SUBSYSTEM" , Linux ARM , References: <1557474150-19618-1-git-send-email-alexandre.torgue@st.com> From: Alexandre Torgue Message-ID: <4a35e070-b18a-e0f5-76b6-72054eb98b43@st.com> Date: Fri, 24 May 2019 14:26:19 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8"; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.75.127.50] X-ClientProxiedBy: SFHDAG5NODE2.st.com (10.75.127.14) To SFHDAG3NODE2.st.com (10.75.127.8) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2019-05-24_05:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 5/24/19 1:24 PM, Linus Walleij wrote: > On Fri, May 10, 2019 at 9:42 AM Alexandre Torgue > wrote: > >> During power sequence, GPIO hardware registers could be lost if the power >> supply is switched off. Each device using pinctrl API is in charge of >> managing pins during suspend/resume sequences. But for pins used as gpio or >> irq stm32 pinctrl driver has to save the hardware configuration. >> Each register will be saved at runtime and restored during resume sequence. > > Both patches applied. > > On the same pinctrl devel branch is also Benjamin's patches to support > the "link_consumers" property on the pin controller descriptor to > enable links from pin control consumers back to their pin controller > suppliers, especially important for STMFX. > > Would you please check if it work fine if you turn on this feature > for the SoC STM32 pin controller? > Sure. Either today or next Monday. I let you know. regards Alex > I am working a bit on refining the patches, so I want to enable testing > with some SoC pin controllers as well and possibly make the > behavior default. > > Yours, > Linus Walleij > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, T_DKIMWL_WL_HIGH,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0E83DC072B5 for ; Fri, 24 May 2019 12:26:33 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D3F4220862 for ; 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Fri, 24 May 2019 12:26:20 +0000 (GMT) Received: from [10.48.0.204] (10.75.127.50) by SFHDAG3NODE2.st.com (10.75.127.8) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Fri, 24 May 2019 14:26:20 +0200 Subject: Re: [PATCH 0/2] pinctrl: stm32: add suspend/resume management To: Linus Walleij , Benjamin Gaignard References: <1557474150-19618-1-git-send-email-alexandre.torgue@st.com> From: Alexandre Torgue Message-ID: <4a35e070-b18a-e0f5-76b6-72054eb98b43@st.com> Date: Fri, 24 May 2019 14:26:19 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-Originating-IP: [10.75.127.50] X-ClientProxiedBy: SFHDAG5NODE2.st.com (10.75.127.14) To SFHDAG3NODE2.st.com (10.75.127.8) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-05-24_05:, , signatures=0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190524_052627_482103_82D44F07 X-CRM114-Status: GOOD ( 16.15 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Linux ARM , "open list:GPIO SUBSYSTEM" , "linux-kernel@vger.kernel.org" , Maxime Coquelin , linux-stm32@st-md-mailman.stormreply.com Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 5/24/19 1:24 PM, Linus Walleij wrote: > On Fri, May 10, 2019 at 9:42 AM Alexandre Torgue > wrote: > >> During power sequence, GPIO hardware registers could be lost if the power >> supply is switched off. Each device using pinctrl API is in charge of >> managing pins during suspend/resume sequences. But for pins used as gpio or >> irq stm32 pinctrl driver has to save the hardware configuration. >> Each register will be saved at runtime and restored during resume sequence. > > Both patches applied. > > On the same pinctrl devel branch is also Benjamin's patches to support > the "link_consumers" property on the pin controller descriptor to > enable links from pin control consumers back to their pin controller > suppliers, especially important for STMFX. > > Would you please check if it work fine if you turn on this feature > for the SoC STM32 pin controller? > Sure. Either today or next Monday. I let you know. regards Alex > I am working a bit on refining the patches, so I want to enable testing > with some SoC pin controllers as well and possibly make the > behavior default. > > Yours, > Linus Walleij > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel