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[88.156.142.67]) by smtp.gmail.com with ESMTPSA id t3-20020a056512208300b004acbfa4a18bsm296625lfr.173.2022.11.30.07.51.32 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 30 Nov 2022 07:51:33 -0800 (PST) Message-ID: <4a7a9bf7-f831-e1c1-0a31-8afcf92ae84c@linaro.org> Date: Wed, 30 Nov 2022 16:51:32 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.5.0 Subject: Re: [PATCH v2 2/5] dt-bindings: net: add schema for NXP S32CC dwmac glue driver Content-Language: en-US To: Chester Lin , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Jan Petrous , Andrew Lunn Cc: Alexandre Torgue , Giuseppe Cavallaro , Jose Abreu , netdev@vger.kernel.org, s32@nxp.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, =?UTF-8?Q?Andreas_F=c3=a4rber?= , Matthias Brugger References: <20221128054920.2113-1-clin@suse.com> <20221128054920.2113-3-clin@suse.com> From: Krzysztof Kozlowski In-Reply-To: <20221128054920.2113-3-clin@suse.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 28/11/2022 06:49, Chester Lin wrote: > Add the DT schema for the DWMAC Ethernet controller on NXP S32 Common > Chassis. > > Signed-off-by: Jan Petrous > Signed-off-by: Chester Lin Thank you for your patch. There is something to discuss/improve. > --- > > Changes in v2: > - Fix schema issues. > - Add minItems to clocks & clock-names. > - Replace all sgmii/SGMII terms with pcs/PCS. > > .../bindings/net/nxp,s32cc-dwmac.yaml | 135 ++++++++++++++++++ > 1 file changed, 135 insertions(+) > create mode 100644 Documentation/devicetree/bindings/net/nxp,s32cc-dwmac.yaml > > diff --git a/Documentation/devicetree/bindings/net/nxp,s32cc-dwmac.yaml b/Documentation/devicetree/bindings/net/nxp,s32cc-dwmac.yaml > new file mode 100644 > index 000000000000..c6839fd3df40 > --- /dev/null > +++ b/Documentation/devicetree/bindings/net/nxp,s32cc-dwmac.yaml > @@ -0,0 +1,135 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +# Copyright 2021-2022 NXP > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/net/nxp,s32cc-dwmac.yaml#" > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" Drop quotes from both. > + > +title: NXP S32CC DWMAC Ethernet controller > + > +maintainers: > + - Jan Petrous > + - Chester Lin > + > +allOf: > + - $ref: "snps,dwmac.yaml#" Drop quotes. > + > +properties: > + compatible: > + enum: > + - nxp,s32cc-dwmac > + > + reg: > + items: > + - description: Main GMAC registers > + - description: S32 MAC control registers > + > + dma-coherent: true > + > + clocks: > + minItems: 5 Why only 5 clocks are required? Receive clocks don't have to be there? Is such system - only with clocks for transmit - usable? > + items: > + - description: Main GMAC clock > + - description: Peripheral registers clock > + - description: Transmit PCS clock > + - description: Transmit RGMII clock > + - description: Transmit RMII clock > + - description: Transmit MII clock > + - description: Receive PCS clock > + - description: Receive RGMII clock > + - description: Receive RMII clock > + - description: Receive MII clock > + - description: > + PTP reference clock. This clock is used for programming the > + Timestamp Addend Register. If not passed then the system > + clock will be used. > + > + clock-names: > + minItems: 5 > + items: > + - const: stmmaceth > + - const: pclk > + - const: tx_pcs > + - const: tx_rgmii > + - const: tx_rmii > + - const: tx_mii > + - const: rx_pcs > + - const: rx_rgmii > + - const: rx_rmii > + - const: rx_mii > + - const: ptp_ref > + > + tx-fifo-depth: > + const: 20480 > + > + rx-fifo-depth: > + const: 20480 > + > +required: > + - compatible > + - reg > + - tx-fifo-depth > + - rx-fifo-depth > + - clocks > + - clock-names > + > +unevaluatedProperties: false > + > +examples: > + - | > + #include > + #include > + > + #define S32GEN1_SCMI_CLK_GMAC0_AXI > + #define S32GEN1_SCMI_CLK_GMAC0_TX_PCS > + #define S32GEN1_SCMI_CLK_GMAC0_TX_RGMII > + #define S32GEN1_SCMI_CLK_GMAC0_TX_RMII > + #define S32GEN1_SCMI_CLK_GMAC0_TX_MII > + #define S32GEN1_SCMI_CLK_GMAC0_RX_PCS > + #define S32GEN1_SCMI_CLK_GMAC0_RX_RGMII > + #define S32GEN1_SCMI_CLK_GMAC0_RX_RMII > + #define S32GEN1_SCMI_CLK_GMAC0_RX_MII > + #define S32GEN1_SCMI_CLK_GMAC0_TS Why defines? Your clock controller is not ready? If so, just use raw numbers. > + > + soc { > + #address-cells = <1>; > + #size-cells = <1>; > + > + gmac0: ethernet@4033c000 { > + compatible = "nxp,s32cc-dwmac"; > + reg = <0x4033c000 0x2000>, /* gmac IP */ > + <0x4007C004 0x4>; /* S32 CTRL_STS reg */ Lowercase hex. > + interrupt-parent = <&gic>; > + interrupts = ; > + interrupt-names = "macirq"; > + phy-mode = "rgmii-id"; > + tx-fifo-depth = <20480>; > + rx-fifo-depth = <20480>; > + dma-coherent; > + clocks = <&clks S32GEN1_SCMI_CLK_GMAC0_AXI>, > + <&clks S32GEN1_SCMI_CLK_GMAC0_AXI>, > + <&clks S32GEN1_SCMI_CLK_GMAC0_TX_PCS>, > + <&clks S32GEN1_SCMI_CLK_GMAC0_TX_RGMII>, > + <&clks S32GEN1_SCMI_CLK_GMAC0_TX_RMII>, > + <&clks S32GEN1_SCMI_CLK_GMAC0_TX_MII>, > + <&clks S32GEN1_SCMI_CLK_GMAC0_RX_PCS>, > + <&clks S32GEN1_SCMI_CLK_GMAC0_RX_RGMII>, > + <&clks S32GEN1_SCMI_CLK_GMAC0_RX_RMII>, > + <&clks S32GEN1_SCMI_CLK_GMAC0_RX_MII>, > + <&clks S32GEN1_SCMI_CLK_GMAC0_TS>; Best regards, Krzysztof From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9D0AEC4332F for ; Wed, 30 Nov 2022 15:52:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:From:References:Cc:To: Subject:MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=NJ3o6uU36o6LznlvcYdLAO2TU1R3x8kFUdIVtsPJ8I0=; b=XeIsXEFeGh0L2R OqwcOwPlH+t3sh3xTH6DgkDRMj1jXKiIk/zM13oOy1JD7Rr8s6ekXPE6itEohl8X3AHcsSK3HMkxY WnjX7n0eDdElTWl9kLH26Fnn57YQvNFwYL+cLxL0JBrYdplWroqFTxaViIkFVxNgzSHpRKdpc8LAh 7egrhtzAlZ0sUFjR6bbs7Gqx1DJL5tf9fiYIYmawIVNIfxoaTEL3Y2vaxG6FvAl8IShFKGFqir1Go bg8rez41+920BpAiZSehCt85Z0wKA7U7eikpbgmY3Ta2YNSNmzFHnX0Iu9Bp6hRNWIdg2qyRgHuYF qy4RnSP7Pf+/DuFMbTVA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1p0PN7-0006sk-Vd; Wed, 30 Nov 2022 15:51:42 +0000 Received: from mail-lj1-x232.google.com ([2a00:1450:4864:20::232]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1p0PN2-0006ly-H4 for linux-arm-kernel@lists.infradead.org; Wed, 30 Nov 2022 15:51:39 +0000 Received: by mail-lj1-x232.google.com with SMTP id r8so21365351ljn.8 for ; Wed, 30 Nov 2022 07:51:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=PG0uNEVGK4q7da5/MLy+snrbykYNb1/tHqcYAuUGVuE=; b=YNd1J19Wgi306BQblAaPgKiipYJCYfpfdz/CeUQkZXVXZRPmnsfMyUS9HiqfBZqkX9 W2xdcA4Xj1qpFuxp+n2t4RVMuRUn0EUCcTy3drHjothY/1Zk3YeD6ONjthQnfkoBF95f mBMzqQSRhGWl2rnmw4V47jbq3KbVB/1EF73YnKCD+Os3ZtXVnOmKkLmujB9mCtqcatPZ adja1EwtKGVjCwLIHZWDCAGICaD58aKB5SRN1Y1e5c1jseRZfXRieRnLe11+MIiSBNgU npmdm0g2HeUCZCLRaphw12jBLOzLpOfikY3wLxNgzadTyp3AS4G0jQiMWTTWe2My+pZD Owxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=PG0uNEVGK4q7da5/MLy+snrbykYNb1/tHqcYAuUGVuE=; b=A2OGpT1dCxAaa9Cs+yS7CzeyKsSSEeGyjR9EVgd/yLXAcCQ97sZ9fBtrfgyoyZog4N MyPjqHSRgYdgtZIC5XQmWkWF+dHyJoWcNjy/s3LjGieG+Q9usJmQ2j5aBQq54TddcZxj CQXG6PkexXRviy/BPMOJb7Ch1AAEwW9/rvpVxIQeyeUVdN+C9VEmZMBdeTEm9AXaIoFK L+UcdFs90PZk/oqxqTT2AprbtvmqmCa/nunHm8+Xz5spvLiTAk+TOYKVS4N2EAK3CcXU qBF6OdpzEtQmfBibJtjM3ur2d88XqZ3W5DPnIFp0OXFcbGJiz3BZTPYHeAzf6krRbg1E yE+g== X-Gm-Message-State: ANoB5pl4fl406Q5FjKJUzUjMCUBG5acIhIuMWlX7B+9PjY5xlObKatHe fZRP/Vv1DcF4c+t9o2P95nV7aw== X-Google-Smtp-Source: AA0mqf7WjHG5qZxOo7GtR4qXw/4cWciSGicSqr/rFLFWR/5xIAagdnHXnwB0zrmbHNC8Q/jGHdM8iw== X-Received: by 2002:a2e:bc88:0:b0:26f:ae32:a207 with SMTP id h8-20020a2ebc88000000b0026fae32a207mr21540208ljf.321.1669823493993; Wed, 30 Nov 2022 07:51:33 -0800 (PST) Received: from [192.168.0.20] (088156142067.dynamic-2-waw-k-3-2-0.vectranet.pl. [88.156.142.67]) by smtp.gmail.com with ESMTPSA id t3-20020a056512208300b004acbfa4a18bsm296625lfr.173.2022.11.30.07.51.32 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 30 Nov 2022 07:51:33 -0800 (PST) Message-ID: <4a7a9bf7-f831-e1c1-0a31-8afcf92ae84c@linaro.org> Date: Wed, 30 Nov 2022 16:51:32 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.5.0 Subject: Re: [PATCH v2 2/5] dt-bindings: net: add schema for NXP S32CC dwmac glue driver Content-Language: en-US To: Chester Lin , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Jan Petrous , Andrew Lunn Cc: Alexandre Torgue , Giuseppe Cavallaro , Jose Abreu , netdev@vger.kernel.org, s32@nxp.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, =?UTF-8?Q?Andreas_F=c3=a4rber?= , Matthias Brugger References: <20221128054920.2113-1-clin@suse.com> <20221128054920.2113-3-clin@suse.com> From: Krzysztof Kozlowski In-Reply-To: <20221128054920.2113-3-clin@suse.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221130_075136_617979_1AD3B39D X-CRM114-Status: GOOD ( 23.31 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 28/11/2022 06:49, Chester Lin wrote: > Add the DT schema for the DWMAC Ethernet controller on NXP S32 Common > Chassis. > > Signed-off-by: Jan Petrous > Signed-off-by: Chester Lin Thank you for your patch. There is something to discuss/improve. > --- > > Changes in v2: > - Fix schema issues. > - Add minItems to clocks & clock-names. > - Replace all sgmii/SGMII terms with pcs/PCS. > > .../bindings/net/nxp,s32cc-dwmac.yaml | 135 ++++++++++++++++++ > 1 file changed, 135 insertions(+) > create mode 100644 Documentation/devicetree/bindings/net/nxp,s32cc-dwmac.yaml > > diff --git a/Documentation/devicetree/bindings/net/nxp,s32cc-dwmac.yaml b/Documentation/devicetree/bindings/net/nxp,s32cc-dwmac.yaml > new file mode 100644 > index 000000000000..c6839fd3df40 > --- /dev/null > +++ b/Documentation/devicetree/bindings/net/nxp,s32cc-dwmac.yaml > @@ -0,0 +1,135 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +# Copyright 2021-2022 NXP > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/net/nxp,s32cc-dwmac.yaml#" > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" Drop quotes from both. > + > +title: NXP S32CC DWMAC Ethernet controller > + > +maintainers: > + - Jan Petrous > + - Chester Lin > + > +allOf: > + - $ref: "snps,dwmac.yaml#" Drop quotes. > + > +properties: > + compatible: > + enum: > + - nxp,s32cc-dwmac > + > + reg: > + items: > + - description: Main GMAC registers > + - description: S32 MAC control registers > + > + dma-coherent: true > + > + clocks: > + minItems: 5 Why only 5 clocks are required? Receive clocks don't have to be there? Is such system - only with clocks for transmit - usable? > + items: > + - description: Main GMAC clock > + - description: Peripheral registers clock > + - description: Transmit PCS clock > + - description: Transmit RGMII clock > + - description: Transmit RMII clock > + - description: Transmit MII clock > + - description: Receive PCS clock > + - description: Receive RGMII clock > + - description: Receive RMII clock > + - description: Receive MII clock > + - description: > + PTP reference clock. This clock is used for programming the > + Timestamp Addend Register. If not passed then the system > + clock will be used. > + > + clock-names: > + minItems: 5 > + items: > + - const: stmmaceth > + - const: pclk > + - const: tx_pcs > + - const: tx_rgmii > + - const: tx_rmii > + - const: tx_mii > + - const: rx_pcs > + - const: rx_rgmii > + - const: rx_rmii > + - const: rx_mii > + - const: ptp_ref > + > + tx-fifo-depth: > + const: 20480 > + > + rx-fifo-depth: > + const: 20480 > + > +required: > + - compatible > + - reg > + - tx-fifo-depth > + - rx-fifo-depth > + - clocks > + - clock-names > + > +unevaluatedProperties: false > + > +examples: > + - | > + #include > + #include > + > + #define S32GEN1_SCMI_CLK_GMAC0_AXI > + #define S32GEN1_SCMI_CLK_GMAC0_TX_PCS > + #define S32GEN1_SCMI_CLK_GMAC0_TX_RGMII > + #define S32GEN1_SCMI_CLK_GMAC0_TX_RMII > + #define S32GEN1_SCMI_CLK_GMAC0_TX_MII > + #define S32GEN1_SCMI_CLK_GMAC0_RX_PCS > + #define S32GEN1_SCMI_CLK_GMAC0_RX_RGMII > + #define S32GEN1_SCMI_CLK_GMAC0_RX_RMII > + #define S32GEN1_SCMI_CLK_GMAC0_RX_MII > + #define S32GEN1_SCMI_CLK_GMAC0_TS Why defines? Your clock controller is not ready? If so, just use raw numbers. > + > + soc { > + #address-cells = <1>; > + #size-cells = <1>; > + > + gmac0: ethernet@4033c000 { > + compatible = "nxp,s32cc-dwmac"; > + reg = <0x4033c000 0x2000>, /* gmac IP */ > + <0x4007C004 0x4>; /* S32 CTRL_STS reg */ Lowercase hex. > + interrupt-parent = <&gic>; > + interrupts = ; > + interrupt-names = "macirq"; > + phy-mode = "rgmii-id"; > + tx-fifo-depth = <20480>; > + rx-fifo-depth = <20480>; > + dma-coherent; > + clocks = <&clks S32GEN1_SCMI_CLK_GMAC0_AXI>, > + <&clks S32GEN1_SCMI_CLK_GMAC0_AXI>, > + <&clks S32GEN1_SCMI_CLK_GMAC0_TX_PCS>, > + <&clks S32GEN1_SCMI_CLK_GMAC0_TX_RGMII>, > + <&clks S32GEN1_SCMI_CLK_GMAC0_TX_RMII>, > + <&clks S32GEN1_SCMI_CLK_GMAC0_TX_MII>, > + <&clks S32GEN1_SCMI_CLK_GMAC0_RX_PCS>, > + <&clks S32GEN1_SCMI_CLK_GMAC0_RX_RGMII>, > + <&clks S32GEN1_SCMI_CLK_GMAC0_RX_RMII>, > + <&clks S32GEN1_SCMI_CLK_GMAC0_RX_MII>, > + <&clks S32GEN1_SCMI_CLK_GMAC0_TS>; Best regards, Krzysztof _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel