* [Qemu-devel] [PULL 00/51] tcg queued patches
@ 2017-10-25 9:34 Richard Henderson
2017-10-25 9:34 ` [Qemu-devel] [PULL 01/51] tcg: Merge opcode arguments into TCGOp Richard Henderson
` (53 more replies)
0 siblings, 54 replies; 59+ messages in thread
From: Richard Henderson @ 2017-10-25 9:34 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
Primarily Emilio's work toward removing tb_lock, with fixes.
But there are some other tcg-related patches that are queued.
r~
The following changes since commit 3d7196d43bfe12efe98568cb60057e273652b99b:
Merge remote-tracking branch 'remotes/kraxel/tags/usb-20171023-pull-request' into staging (2017-10-24 16:05:57 +0100)
are available in the git repository at:
git://github.com/rth7680/qemu.git tags/pull-tcg-20171025
for you to fetch changes up to cc689485ee3e9dca05765326ee8fd619a6ec48f0:
translate-all: exit from tb_phys_invalidate if qht_remove fails (2017-10-24 13:53:42 -0700)
----------------------------------------------------------------
TCG patch queue
----------------------------------------------------------------
Emilio G. Cota (25):
tcg: define CF_PARALLEL and use it for TB hashing along with CF_COUNT_MASK
tcg: convert tb->cflags reads to tb_cflags(tb)
target/arm: check CF_PARALLEL instead of parallel_cpus
target/hppa: check CF_PARALLEL instead of parallel_cpus
target/i386: check CF_PARALLEL instead of parallel_cpus
target/m68k: check CF_PARALLEL instead of parallel_cpus
target/s390x: check CF_PARALLEL instead of parallel_cpus
target/sh4: check CF_PARALLEL instead of parallel_cpus
target/sparc: check CF_PARALLEL instead of parallel_cpus
tcg: check CF_PARALLEL instead of parallel_cpus
cpu-exec: lookup/generate TB outside exclusive region during step_atomic
translate-all: use a binary search tree to track TBs in TBContext
exec-all: rename tb_free to tb_remove
translate-all: report correct avg host TB size
tcg: take tb_ctx out of TCGContext
tcg: define tcg_init_ctx and make tcg_ctx a pointer
gen-icount: fold exitreq_label into TCGContext
tcg: introduce **tcg_ctxs to keep track of all TCGContext's
tcg: distribute profiling counters across TCGContext's
tcg: allocate optimizer temps with tcg_malloc
osdep: introduce qemu_mprotect_rwx/none
translate-all: use qemu_protect_rwx/none helpers
tcg: introduce regions to split code_gen_buffer
tcg: enable multiple TCG contexts in softmmu
translate-all: exit from tb_phys_invalidate if qht_remove fails
Richard Henderson (26):
tcg: Merge opcode arguments into TCGOp
tcg: Propagate args to op->args in optimizer
tcg: Propagate args to op->args in tcg.c
tcg: Propagate TCGOp down to allocators
tcg: Introduce arg_temp
tcg: Add temp_global bit to TCGTemp
tcg: Return NULL temp for TCG_CALL_DUMMY_ARG
tcg: Introduce temp_arg, export temp_idx
tcg: Use per-temp state data in liveness
tcg: Avoid loops against variable bounds
tcg: Change temp_allocate_frame arg to TCGTemp
tcg: Remove unused TCG_CALL_DUMMY_TCGV
tcg: Use per-temp state data in optimize
tcg: Push tcg_ctx into generator functions
tcg: Push tcg_ctx into tcg_gen_callN
tcg: Introduce tcgv_{i32,i64,ptr}_{arg,temp}
tcg: Introduce temp_tcgv_{i32,i64,ptr}
tcg: Remove GET_TCGV_* and MAKE_TCGV_*
tcg: Remove TCGV_EQUAL*
qom: Introduce CPUClass.tcg_initialize
tcg: Use offsets not indices for TCGv_*
tcg: Add CPUState cflags_next_tb
tcg: Include CF_COUNT_MASK in CF_HASH_MASK
tcg: Add CF_LAST_IO + CF_USE_ICOUNT to CF_HASH_MASK
tcg: Remove CF_IGNORE_ICOUNT
tcg: Initialize cpu_env generically
include/exec/exec-all.h | 42 +-
include/exec/gen-icount.h | 27 +-
include/exec/helper-gen.h | 22 +-
include/exec/helper-head.h | 16 +-
include/exec/tb-context.h | 6 +-
include/exec/tb-hash-xx.h | 9 +-
include/exec/tb-hash.h | 4 +-
include/exec/tb-lookup.h | 6 +-
include/qemu/osdep.h | 2 +
include/qom/cpu.h | 9 +-
target/arm/helper-a64.h | 4 +
target/arm/translate.h | 1 -
target/hppa/helper.h | 2 +
target/m68k/helper.h | 1 +
target/s390x/helper.h | 4 +
target/sparc/cpu.h | 2 +-
tcg/tcg-op.h | 140 +++---
tcg/tcg.h | 294 ++++++-----
accel/tcg/cpu-exec.c | 100 ++--
accel/tcg/tcg-runtime.c | 4 +-
accel/tcg/translate-all.c | 533 +++++++++-----------
accel/tcg/translator.c | 4 +-
bsd-user/main.c | 3 +-
cpus.c | 14 +
exec.c | 14 +-
linux-user/main.c | 9 +-
linux-user/syscall.c | 1 +
qom/cpu.c | 1 +
target/alpha/cpu.c | 3 +-
target/alpha/translate.c | 14 +-
target/arm/cpu.c | 6 +-
target/arm/helper-a64.c | 38 +-
target/arm/op_helper.c | 7 -
target/arm/translate-a64.c | 38 +-
target/arm/translate.c | 19 +-
target/cris/cpu.c | 16 +-
target/cris/translate.c | 15 +-
target/cris/translate_v10.c | 2 -
target/hppa/cpu.c | 3 +-
target/hppa/op_helper.c | 32 +-
target/hppa/translate.c | 24 +-
target/i386/cpu.c | 5 +-
target/i386/translate.c | 67 ++-
target/lm32/cpu.c | 7 +-
target/lm32/translate.c | 18 +-
target/m68k/cpu.c | 7 +-
target/m68k/op_helper.c | 33 +-
target/m68k/translate.c | 25 +-
target/microblaze/cpu.c | 7 +-
target/microblaze/translate.c | 10 +-
target/mips/cpu.c | 5 +-
target/mips/translate.c | 37 +-
target/moxie/cpu.c | 7 +-
target/moxie/translate.c | 11 +-
target/nios2/cpu.c | 7 +-
target/nios2/translate.c | 10 +-
target/openrisc/cpu.c | 7 +-
target/openrisc/translate.c | 9 +-
target/ppc/translate.c | 20 +-
target/ppc/translate_init.c | 37 +-
target/s390x/cpu.c | 7 +-
target/s390x/mem_helper.c | 80 ++-
target/s390x/translate.c | 40 +-
target/sh4/cpu.c | 5 +-
target/sh4/translate.c | 19 +-
target/sparc/cpu.c | 5 +-
target/sparc/translate.c | 36 +-
target/tilegx/cpu.c | 7 +-
target/tilegx/translate.c | 5 +-
target/tricore/cpu.c | 5 +-
target/tricore/translate.c | 11 +-
target/unicore32/cpu.c | 7 +-
target/unicore32/translate.c | 10 +-
target/xtensa/cpu.c | 7 +-
target/xtensa/translate.c | 31 +-
tcg/optimize.c | 654 +++++++++++++-----------
tcg/tcg-op.c | 190 +++----
tcg/tcg.c | 1116 +++++++++++++++++++++++++++--------------
tests/qht-bench.c | 2 +-
util/osdep.c | 41 ++
80 files changed, 2285 insertions(+), 1813 deletions(-)
^ permalink raw reply [flat|nested] 59+ messages in thread
* [Qemu-devel] [PULL 01/51] tcg: Merge opcode arguments into TCGOp
2017-10-25 9:34 [Qemu-devel] [PULL 00/51] tcg queued patches Richard Henderson
@ 2017-10-25 9:34 ` Richard Henderson
2017-10-25 9:34 ` [Qemu-devel] [PULL 02/51] tcg: Propagate args to op->args in optimizer Richard Henderson
` (52 subsequent siblings)
53 siblings, 0 replies; 59+ messages in thread
From: Richard Henderson @ 2017-10-25 9:34 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Richard Henderson
From: Richard Henderson <rth@twiddle.net>
Rather than have a separate buffer of 10*max_ops entries,
give each opcode 10 entries. The result is actually a bit
smaller and should have slightly more cache locality.
Reviewed-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/tcg.h | 37 ++++++++++------------
tcg/optimize.c | 6 ++--
tcg/tcg-op.c | 99 +++++++++++++++++++++-------------------------------------
tcg/tcg.c | 98 ++++++++++++++++++++++++++-------------------------------
4 files changed, 98 insertions(+), 142 deletions(-)
diff --git a/tcg/tcg.h b/tcg/tcg.h
index b2d42e3136..2cefd9f125 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -51,8 +51,6 @@
#define OPC_BUF_SIZE 640
#define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
-#define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)
-
#define CPU_TEMP_BUF_NLONGS 128
/* Default target word size to pointer size. */
@@ -606,33 +604,33 @@ typedef struct TCGTempSet {
#define SYNC_ARG 1
typedef uint16_t TCGLifeData;
-/* The layout here is designed to avoid crossing of a 32-bit boundary.
- If we do so, gcc adds padding, expanding the size to 12. */
+/* The layout here is designed to avoid a bitfield crossing of
+ a 32-bit boundary, which would cause GCC to add extra padding. */
typedef struct TCGOp {
TCGOpcode opc : 8; /* 8 */
- /* Index of the prev/next op, or 0 for the end of the list. */
- unsigned prev : 10; /* 18 */
- unsigned next : 10; /* 28 */
-
/* The number of out and in parameter for a call. */
- unsigned calli : 4; /* 32 */
- unsigned callo : 2; /* 34 */
+ unsigned calli : 4; /* 12 */
+ unsigned callo : 2; /* 14 */
+ unsigned : 2; /* 16 */
- /* Index of the arguments for this op, or 0 for zero-operand ops. */
- unsigned args : 14; /* 48 */
+ /* Index of the prev/next op, or 0 for the end of the list. */
+ unsigned prev : 16; /* 32 */
+ unsigned next : 16; /* 48 */
/* Lifetime data of the operands. */
unsigned life : 16; /* 64 */
+
+ /* Arguments for the opcode. */
+ TCGArg args[MAX_OPC_PARAM];
} TCGOp;
+/* Make sure that we don't expand the structure without noticing. */
+QEMU_BUILD_BUG_ON(sizeof(TCGOp) != 8 + sizeof(TCGArg) * MAX_OPC_PARAM);
+
/* Make sure operands fit in the bitfields above. */
QEMU_BUILD_BUG_ON(NB_OPS > (1 << 8));
-QEMU_BUILD_BUG_ON(OPC_BUF_SIZE > (1 << 10));
-QEMU_BUILD_BUG_ON(OPPARAM_BUF_SIZE > (1 << 14));
-
-/* Make sure that we don't overflow 64 bits without noticing. */
-QEMU_BUILD_BUG_ON(sizeof(TCGOp) > 8);
+QEMU_BUILD_BUG_ON(OPC_BUF_SIZE > (1 << 16));
struct TCGContext {
uint8_t *pool_cur, *pool_end;
@@ -682,7 +680,6 @@ struct TCGContext {
#endif
int gen_next_op_idx;
- int gen_next_parm_idx;
/* Code generation. Note that we specifically do not use tcg_insn_unit
here, because there's too much arithmetic throughout that relies
@@ -720,7 +717,6 @@ struct TCGContext {
TCGTemp *reg_to_temp[TCG_TARGET_NB_REGS];
TCGOp gen_op_buf[OPC_BUF_SIZE];
- TCGArg gen_opparam_buf[OPPARAM_BUF_SIZE];
uint16_t gen_insn_end_off[TCG_MAX_INSNS];
target_ulong gen_insn_data[TCG_MAX_INSNS][TARGET_INSN_START_WORDS];
@@ -731,8 +727,7 @@ extern bool parallel_cpus;
static inline void tcg_set_insn_param(int op_idx, int arg, TCGArg v)
{
- int op_argi = tcg_ctx.gen_op_buf[op_idx].args;
- tcg_ctx.gen_opparam_buf[op_argi + arg] = v;
+ tcg_ctx.gen_op_buf[op_idx].args[arg] = v;
}
/* The number of opcodes emitted so far. */
diff --git a/tcg/optimize.c b/tcg/optimize.c
index adfc56ce62..002aad6bf4 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -576,7 +576,7 @@ void tcg_optimize(TCGContext *s)
TCGArg tmp;
TCGOp * const op = &s->gen_op_buf[oi];
- TCGArg * const args = &s->gen_opparam_buf[op->args];
+ TCGArg * const args = op->args;
TCGOpcode opc = op->opc;
const TCGOpDef *def = &tcg_op_defs[opc];
@@ -1184,7 +1184,7 @@ void tcg_optimize(TCGContext *s)
uint64_t b = ((uint64_t)bh << 32) | bl;
TCGArg rl, rh;
TCGOp *op2 = tcg_op_insert_before(s, op, INDEX_op_movi_i32, 2);
- TCGArg *args2 = &s->gen_opparam_buf[op2->args];
+ TCGArg *args2 = op2->args;
if (opc == INDEX_op_add2_i32) {
a += b;
@@ -1210,7 +1210,7 @@ void tcg_optimize(TCGContext *s)
uint64_t r = (uint64_t)a * b;
TCGArg rl, rh;
TCGOp *op2 = tcg_op_insert_before(s, op, INDEX_op_movi_i32, 2);
- TCGArg *args2 = &s->gen_opparam_buf[op2->args];
+ TCGArg *args2 = op2->args;
rl = args[0];
rh = args[1];
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index d3c0e4799e..bd84a782e3 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -46,107 +46,78 @@ extern TCGv_i32 TCGV_HIGH_link_error(TCGv_i64);
Up to and including filling in the forward link immediately. We'll do
proper termination of the end of the list after we finish translation. */
-static void tcg_emit_op(TCGContext *ctx, TCGOpcode opc, int args)
+static inline TCGOp *tcg_emit_op(TCGContext *ctx, TCGOpcode opc)
{
int oi = ctx->gen_next_op_idx;
int ni = oi + 1;
int pi = oi - 1;
+ TCGOp *op = &ctx->gen_op_buf[oi];
tcg_debug_assert(oi < OPC_BUF_SIZE);
ctx->gen_op_buf[0].prev = oi;
ctx->gen_next_op_idx = ni;
- ctx->gen_op_buf[oi] = (TCGOp){
- .opc = opc,
- .args = args,
- .prev = pi,
- .next = ni
- };
+ memset(op, 0, offsetof(TCGOp, args));
+ op->opc = opc;
+ op->prev = pi;
+ op->next = ni;
+
+ return op;
}
void tcg_gen_op1(TCGContext *ctx, TCGOpcode opc, TCGArg a1)
{
- int pi = ctx->gen_next_parm_idx;
-
- tcg_debug_assert(pi + 1 <= OPPARAM_BUF_SIZE);
- ctx->gen_next_parm_idx = pi + 1;
- ctx->gen_opparam_buf[pi] = a1;
-
- tcg_emit_op(ctx, opc, pi);
+ TCGOp *op = tcg_emit_op(ctx, opc);
+ op->args[0] = a1;
}
void tcg_gen_op2(TCGContext *ctx, TCGOpcode opc, TCGArg a1, TCGArg a2)
{
- int pi = ctx->gen_next_parm_idx;
-
- tcg_debug_assert(pi + 2 <= OPPARAM_BUF_SIZE);
- ctx->gen_next_parm_idx = pi + 2;
- ctx->gen_opparam_buf[pi + 0] = a1;
- ctx->gen_opparam_buf[pi + 1] = a2;
-
- tcg_emit_op(ctx, opc, pi);
+ TCGOp *op = tcg_emit_op(ctx, opc);
+ op->args[0] = a1;
+ op->args[1] = a2;
}
void tcg_gen_op3(TCGContext *ctx, TCGOpcode opc, TCGArg a1,
TCGArg a2, TCGArg a3)
{
- int pi = ctx->gen_next_parm_idx;
-
- tcg_debug_assert(pi + 3 <= OPPARAM_BUF_SIZE);
- ctx->gen_next_parm_idx = pi + 3;
- ctx->gen_opparam_buf[pi + 0] = a1;
- ctx->gen_opparam_buf[pi + 1] = a2;
- ctx->gen_opparam_buf[pi + 2] = a3;
-
- tcg_emit_op(ctx, opc, pi);
+ TCGOp *op = tcg_emit_op(ctx, opc);
+ op->args[0] = a1;
+ op->args[1] = a2;
+ op->args[2] = a3;
}
void tcg_gen_op4(TCGContext *ctx, TCGOpcode opc, TCGArg a1,
TCGArg a2, TCGArg a3, TCGArg a4)
{
- int pi = ctx->gen_next_parm_idx;
-
- tcg_debug_assert(pi + 4 <= OPPARAM_BUF_SIZE);
- ctx->gen_next_parm_idx = pi + 4;
- ctx->gen_opparam_buf[pi + 0] = a1;
- ctx->gen_opparam_buf[pi + 1] = a2;
- ctx->gen_opparam_buf[pi + 2] = a3;
- ctx->gen_opparam_buf[pi + 3] = a4;
-
- tcg_emit_op(ctx, opc, pi);
+ TCGOp *op = tcg_emit_op(ctx, opc);
+ op->args[0] = a1;
+ op->args[1] = a2;
+ op->args[2] = a3;
+ op->args[3] = a4;
}
void tcg_gen_op5(TCGContext *ctx, TCGOpcode opc, TCGArg a1,
TCGArg a2, TCGArg a3, TCGArg a4, TCGArg a5)
{
- int pi = ctx->gen_next_parm_idx;
-
- tcg_debug_assert(pi + 5 <= OPPARAM_BUF_SIZE);
- ctx->gen_next_parm_idx = pi + 5;
- ctx->gen_opparam_buf[pi + 0] = a1;
- ctx->gen_opparam_buf[pi + 1] = a2;
- ctx->gen_opparam_buf[pi + 2] = a3;
- ctx->gen_opparam_buf[pi + 3] = a4;
- ctx->gen_opparam_buf[pi + 4] = a5;
-
- tcg_emit_op(ctx, opc, pi);
+ TCGOp *op = tcg_emit_op(ctx, opc);
+ op->args[0] = a1;
+ op->args[1] = a2;
+ op->args[2] = a3;
+ op->args[3] = a4;
+ op->args[4] = a5;
}
void tcg_gen_op6(TCGContext *ctx, TCGOpcode opc, TCGArg a1, TCGArg a2,
TCGArg a3, TCGArg a4, TCGArg a5, TCGArg a6)
{
- int pi = ctx->gen_next_parm_idx;
-
- tcg_debug_assert(pi + 6 <= OPPARAM_BUF_SIZE);
- ctx->gen_next_parm_idx = pi + 6;
- ctx->gen_opparam_buf[pi + 0] = a1;
- ctx->gen_opparam_buf[pi + 1] = a2;
- ctx->gen_opparam_buf[pi + 2] = a3;
- ctx->gen_opparam_buf[pi + 3] = a4;
- ctx->gen_opparam_buf[pi + 4] = a5;
- ctx->gen_opparam_buf[pi + 5] = a6;
-
- tcg_emit_op(ctx, opc, pi);
+ TCGOp *op = tcg_emit_op(ctx, opc);
+ op->args[0] = a1;
+ op->args[1] = a2;
+ op->args[2] = a3;
+ op->args[3] = a4;
+ op->args[4] = a5;
+ op->args[5] = a6;
}
void tcg_gen_mb(TCGBar mb_type)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 4492e1eb3f..98673f2190 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -471,7 +471,6 @@ void tcg_func_start(TCGContext *s)
s->gen_op_buf[0].next = 1;
s->gen_op_buf[0].prev = 0;
s->gen_next_op_idx = 1;
- s->gen_next_parm_idx = 0;
}
static inline int temp_idx(TCGContext *s, TCGTemp *ts)
@@ -980,9 +979,10 @@ bool tcg_op_supported(TCGOpcode op)
void tcg_gen_callN(TCGContext *s, void *func, TCGArg ret,
int nargs, TCGArg *args)
{
- int i, real_args, nb_rets, pi, pi_first;
+ int i, real_args, nb_rets, pi;
unsigned sizemask, flags;
TCGHelperInfo *info;
+ TCGOp *op;
info = g_hash_table_lookup(helper_table, (gpointer)func);
flags = info->flags;
@@ -995,11 +995,11 @@ void tcg_gen_callN(TCGContext *s, void *func, TCGArg ret,
int orig_sizemask = sizemask;
int orig_nargs = nargs;
TCGv_i64 retl, reth;
+ TCGArg split_args[MAX_OPC_PARAM];
TCGV_UNUSED_I64(retl);
TCGV_UNUSED_I64(reth);
if (sizemask != 0) {
- TCGArg *split_args = __builtin_alloca(sizeof(TCGArg) * nargs * 2);
for (i = real_args = 0; i < nargs; ++i) {
int is_64bit = sizemask & (1 << (i+1)*2);
if (is_64bit) {
@@ -1034,7 +1034,19 @@ void tcg_gen_callN(TCGContext *s, void *func, TCGArg ret,
}
#endif /* TCG_TARGET_EXTEND_ARGS */
- pi_first = pi = s->gen_next_parm_idx;
+ i = s->gen_next_op_idx;
+ tcg_debug_assert(i < OPC_BUF_SIZE);
+ s->gen_op_buf[0].prev = i;
+ s->gen_next_op_idx = i + 1;
+ op = &s->gen_op_buf[i];
+
+ /* Set links for sequential allocation during translation. */
+ memset(op, 0, offsetof(TCGOp, args));
+ op->opc = INDEX_op_call;
+ op->prev = i - 1;
+ op->next = i + 1;
+
+ pi = 0;
if (ret != TCG_CALL_DUMMY_ARG) {
#if defined(__sparc__) && !defined(__arch64__) \
&& !defined(CONFIG_TCG_INTERPRETER)
@@ -1044,31 +1056,33 @@ void tcg_gen_callN(TCGContext *s, void *func, TCGArg ret,
two return temporaries, and reassemble below. */
retl = tcg_temp_new_i64();
reth = tcg_temp_new_i64();
- s->gen_opparam_buf[pi++] = GET_TCGV_I64(reth);
- s->gen_opparam_buf[pi++] = GET_TCGV_I64(retl);
+ op->args[pi++] = GET_TCGV_I64(reth);
+ op->args[pi++] = GET_TCGV_I64(retl);
nb_rets = 2;
} else {
- s->gen_opparam_buf[pi++] = ret;
+ op->args[pi++] = ret;
nb_rets = 1;
}
#else
if (TCG_TARGET_REG_BITS < 64 && (sizemask & 1)) {
#ifdef HOST_WORDS_BIGENDIAN
- s->gen_opparam_buf[pi++] = ret + 1;
- s->gen_opparam_buf[pi++] = ret;
+ op->args[pi++] = ret + 1;
+ op->args[pi++] = ret;
#else
- s->gen_opparam_buf[pi++] = ret;
- s->gen_opparam_buf[pi++] = ret + 1;
+ op->args[pi++] = ret;
+ op->args[pi++] = ret + 1;
#endif
nb_rets = 2;
} else {
- s->gen_opparam_buf[pi++] = ret;
+ op->args[pi++] = ret;
nb_rets = 1;
}
#endif
} else {
nb_rets = 0;
}
+ op->callo = nb_rets;
+
real_args = 0;
for (i = 0; i < nargs; i++) {
int is_64bit = sizemask & (1 << (i+1)*2);
@@ -1076,7 +1090,7 @@ void tcg_gen_callN(TCGContext *s, void *func, TCGArg ret,
#ifdef TCG_TARGET_CALL_ALIGN_ARGS
/* some targets want aligned 64 bit args */
if (real_args & 1) {
- s->gen_opparam_buf[pi++] = TCG_CALL_DUMMY_ARG;
+ op->args[pi++] = TCG_CALL_DUMMY_ARG;
real_args++;
}
#endif
@@ -1091,42 +1105,26 @@ void tcg_gen_callN(TCGContext *s, void *func, TCGArg ret,
have to get more complicated to differentiate between
stack arguments and register arguments. */
#if defined(HOST_WORDS_BIGENDIAN) != defined(TCG_TARGET_STACK_GROWSUP)
- s->gen_opparam_buf[pi++] = args[i] + 1;
- s->gen_opparam_buf[pi++] = args[i];
+ op->args[pi++] = args[i] + 1;
+ op->args[pi++] = args[i];
#else
- s->gen_opparam_buf[pi++] = args[i];
- s->gen_opparam_buf[pi++] = args[i] + 1;
+ op->args[pi++] = args[i];
+ op->args[pi++] = args[i] + 1;
#endif
real_args += 2;
continue;
}
- s->gen_opparam_buf[pi++] = args[i];
+ op->args[pi++] = args[i];
real_args++;
}
- s->gen_opparam_buf[pi++] = (uintptr_t)func;
- s->gen_opparam_buf[pi++] = flags;
+ op->args[pi++] = (uintptr_t)func;
+ op->args[pi++] = flags;
+ op->calli = real_args;
- i = s->gen_next_op_idx;
- tcg_debug_assert(i < OPC_BUF_SIZE);
- tcg_debug_assert(pi <= OPPARAM_BUF_SIZE);
-
- /* Set links for sequential allocation during translation. */
- s->gen_op_buf[i] = (TCGOp){
- .opc = INDEX_op_call,
- .callo = nb_rets,
- .calli = real_args,
- .args = pi_first,
- .prev = i - 1,
- .next = i + 1
- };
-
- /* Make sure the calli field didn't overflow. */
- tcg_debug_assert(s->gen_op_buf[i].calli == real_args);
-
- s->gen_op_buf[0].prev = i;
- s->gen_next_op_idx = i + 1;
- s->gen_next_parm_idx = pi;
+ /* Make sure the fields didn't overflow. */
+ tcg_debug_assert(op->calli == real_args);
+ tcg_debug_assert(pi <= ARRAY_SIZE(op->args));
#if defined(__sparc__) && !defined(__arch64__) \
&& !defined(CONFIG_TCG_INTERPRETER)
@@ -1286,7 +1284,7 @@ void tcg_dump_ops(TCGContext *s)
op = &s->gen_op_buf[oi];
c = op->opc;
def = &tcg_op_defs[c];
- args = &s->gen_opparam_buf[op->args];
+ args = op->args;
if (c == INDEX_op_insn_start) {
col += qemu_log("%s ----", oi != s->gen_op_buf[0].next ? "\n" : "");
@@ -1570,20 +1568,16 @@ TCGOp *tcg_op_insert_before(TCGContext *s, TCGOp *old_op,
TCGOpcode opc, int nargs)
{
int oi = s->gen_next_op_idx;
- int pi = s->gen_next_parm_idx;
int prev = old_op->prev;
int next = old_op - s->gen_op_buf;
TCGOp *new_op;
tcg_debug_assert(oi < OPC_BUF_SIZE);
- tcg_debug_assert(pi + nargs <= OPPARAM_BUF_SIZE);
s->gen_next_op_idx = oi + 1;
- s->gen_next_parm_idx = pi + nargs;
new_op = &s->gen_op_buf[oi];
*new_op = (TCGOp){
.opc = opc,
- .args = pi,
.prev = prev,
.next = next
};
@@ -1597,20 +1591,16 @@ TCGOp *tcg_op_insert_after(TCGContext *s, TCGOp *old_op,
TCGOpcode opc, int nargs)
{
int oi = s->gen_next_op_idx;
- int pi = s->gen_next_parm_idx;
int prev = old_op - s->gen_op_buf;
int next = old_op->next;
TCGOp *new_op;
tcg_debug_assert(oi < OPC_BUF_SIZE);
- tcg_debug_assert(pi + nargs <= OPPARAM_BUF_SIZE);
s->gen_next_op_idx = oi + 1;
- s->gen_next_parm_idx = pi + nargs;
new_op = &s->gen_op_buf[oi];
*new_op = (TCGOp){
.opc = opc,
- .args = pi,
.prev = prev,
.next = next
};
@@ -1666,7 +1656,7 @@ static void liveness_pass_1(TCGContext *s, uint8_t *temp_state)
TCGArg arg;
TCGOp * const op = &s->gen_op_buf[oi];
- TCGArg * const args = &s->gen_opparam_buf[op->args];
+ TCGArg * const args = op->args;
TCGOpcode opc = op->opc;
const TCGOpDef *def = &tcg_op_defs[opc];
@@ -1904,7 +1894,7 @@ static bool liveness_pass_2(TCGContext *s, uint8_t *temp_state)
for (oi = s->gen_op_buf[0].next; oi != 0; oi = oi_next) {
TCGOp *op = &s->gen_op_buf[oi];
- TCGArg *args = &s->gen_opparam_buf[op->args];
+ TCGArg *args = op->args;
TCGOpcode opc = op->opc;
const TCGOpDef *def = &tcg_op_defs[opc];
TCGLifeData arg_life = op->life;
@@ -1947,7 +1937,7 @@ static bool liveness_pass_2(TCGContext *s, uint8_t *temp_state)
? INDEX_op_ld_i32
: INDEX_op_ld_i64);
TCGOp *lop = tcg_op_insert_before(s, op, lopc, 3);
- TCGArg *largs = &s->gen_opparam_buf[lop->args];
+ TCGArg *largs = lop->args;
largs[0] = dir;
largs[1] = temp_idx(s, its->mem_base);
@@ -2019,7 +2009,7 @@ static bool liveness_pass_2(TCGContext *s, uint8_t *temp_state)
? INDEX_op_st_i32
: INDEX_op_st_i64);
TCGOp *sop = tcg_op_insert_after(s, op, sopc, 3);
- TCGArg *sargs = &s->gen_opparam_buf[sop->args];
+ TCGArg *sargs = sop->args;
sargs[0] = dir;
sargs[1] = temp_idx(s, its->mem_base);
@@ -2851,7 +2841,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb)
num_insns = -1;
for (oi = s->gen_op_buf[0].next; oi != 0; oi = oi_next) {
TCGOp * const op = &s->gen_op_buf[oi];
- TCGArg * const args = &s->gen_opparam_buf[op->args];
+ TCGArg * const args = op->args;
TCGOpcode opc = op->opc;
const TCGOpDef *def = &tcg_op_defs[opc];
TCGLifeData arg_life = op->life;
--
2.13.6
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [Qemu-devel] [PULL 02/51] tcg: Propagate args to op->args in optimizer
2017-10-25 9:34 [Qemu-devel] [PULL 00/51] tcg queued patches Richard Henderson
2017-10-25 9:34 ` [Qemu-devel] [PULL 01/51] tcg: Merge opcode arguments into TCGOp Richard Henderson
@ 2017-10-25 9:34 ` Richard Henderson
2017-10-25 9:34 ` [Qemu-devel] [PULL 03/51] tcg: Propagate args to op->args in tcg.c Richard Henderson
` (51 subsequent siblings)
53 siblings, 0 replies; 59+ messages in thread
From: Richard Henderson @ 2017-10-25 9:34 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Richard Henderson
From: Richard Henderson <rth@twiddle.net>
Reviewed-by: Emilio G. Cota <cota@braap.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/optimize.c | 430 ++++++++++++++++++++++++++++++---------------------------
1 file changed, 227 insertions(+), 203 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 002aad6bf4..1a1c6fb90c 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -166,8 +166,7 @@ static bool temps_are_copies(TCGArg arg1, TCGArg arg2)
return false;
}
-static void tcg_opt_gen_movi(TCGContext *s, TCGOp *op, TCGArg *args,
- TCGArg dst, TCGArg val)
+static void tcg_opt_gen_movi(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg val)
{
TCGOpcode new_op = op_to_movi(op->opc);
tcg_target_ulong mask;
@@ -184,12 +183,11 @@ static void tcg_opt_gen_movi(TCGContext *s, TCGOp *op, TCGArg *args,
}
temps[dst].mask = mask;
- args[0] = dst;
- args[1] = val;
+ op->args[0] = dst;
+ op->args[1] = val;
}
-static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, TCGArg *args,
- TCGArg dst, TCGArg src)
+static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg src)
{
if (temps_are_copies(dst, src)) {
tcg_op_remove(s, op);
@@ -218,8 +216,8 @@ static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, TCGArg *args,
temps[dst].val = temps[src].val;
}
- args[0] = dst;
- args[1] = src;
+ op->args[0] = dst;
+ op->args[1] = src;
}
static TCGArg do_constant_folding_2(TCGOpcode op, TCGArg x, TCGArg y)
@@ -559,7 +557,7 @@ static bool swap_commutative2(TCGArg *p1, TCGArg *p2)
void tcg_optimize(TCGContext *s)
{
int oi, oi_next, nb_temps, nb_globals;
- TCGArg *prev_mb_args = NULL;
+ TCGOp *prev_mb = NULL;
/* Array VALS has an element for each temp.
If this temp holds a constant then its value is kept in VALS' element.
@@ -576,7 +574,6 @@ void tcg_optimize(TCGContext *s)
TCGArg tmp;
TCGOp * const op = &s->gen_op_buf[oi];
- TCGArg * const args = op->args;
TCGOpcode opc = op->opc;
const TCGOpDef *def = &tcg_op_defs[opc];
@@ -588,7 +585,7 @@ void tcg_optimize(TCGContext *s)
nb_oargs = op->callo;
nb_iargs = op->calli;
for (i = 0; i < nb_oargs + nb_iargs; i++) {
- tmp = args[i];
+ tmp = op->args[i];
if (tmp != TCG_CALL_DUMMY_ARG) {
init_temp_info(tmp);
}
@@ -597,14 +594,14 @@ void tcg_optimize(TCGContext *s)
nb_oargs = def->nb_oargs;
nb_iargs = def->nb_iargs;
for (i = 0; i < nb_oargs + nb_iargs; i++) {
- init_temp_info(args[i]);
+ init_temp_info(op->args[i]);
}
}
/* Do copy propagation */
for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) {
- if (temp_is_copy(args[i])) {
- args[i] = find_better_copy(s, args[i]);
+ if (temp_is_copy(op->args[i])) {
+ op->args[i] = find_better_copy(s, op->args[i]);
}
}
@@ -620,45 +617,45 @@ void tcg_optimize(TCGContext *s)
CASE_OP_32_64(nor):
CASE_OP_32_64(muluh):
CASE_OP_32_64(mulsh):
- swap_commutative(args[0], &args[1], &args[2]);
+ swap_commutative(op->args[0], &op->args[1], &op->args[2]);
break;
CASE_OP_32_64(brcond):
- if (swap_commutative(-1, &args[0], &args[1])) {
- args[2] = tcg_swap_cond(args[2]);
+ if (swap_commutative(-1, &op->args[0], &op->args[1])) {
+ op->args[2] = tcg_swap_cond(op->args[2]);
}
break;
CASE_OP_32_64(setcond):
- if (swap_commutative(args[0], &args[1], &args[2])) {
- args[3] = tcg_swap_cond(args[3]);
+ if (swap_commutative(op->args[0], &op->args[1], &op->args[2])) {
+ op->args[3] = tcg_swap_cond(op->args[3]);
}
break;
CASE_OP_32_64(movcond):
- if (swap_commutative(-1, &args[1], &args[2])) {
- args[5] = tcg_swap_cond(args[5]);
+ if (swap_commutative(-1, &op->args[1], &op->args[2])) {
+ op->args[5] = tcg_swap_cond(op->args[5]);
}
/* For movcond, we canonicalize the "false" input reg to match
the destination reg so that the tcg backend can implement
a "move if true" operation. */
- if (swap_commutative(args[0], &args[4], &args[3])) {
- args[5] = tcg_invert_cond(args[5]);
+ if (swap_commutative(op->args[0], &op->args[4], &op->args[3])) {
+ op->args[5] = tcg_invert_cond(op->args[5]);
}
break;
CASE_OP_32_64(add2):
- swap_commutative(args[0], &args[2], &args[4]);
- swap_commutative(args[1], &args[3], &args[5]);
+ swap_commutative(op->args[0], &op->args[2], &op->args[4]);
+ swap_commutative(op->args[1], &op->args[3], &op->args[5]);
break;
CASE_OP_32_64(mulu2):
CASE_OP_32_64(muls2):
- swap_commutative(args[0], &args[2], &args[3]);
+ swap_commutative(op->args[0], &op->args[2], &op->args[3]);
break;
case INDEX_op_brcond2_i32:
- if (swap_commutative2(&args[0], &args[2])) {
- args[4] = tcg_swap_cond(args[4]);
+ if (swap_commutative2(&op->args[0], &op->args[2])) {
+ op->args[4] = tcg_swap_cond(op->args[4]);
}
break;
case INDEX_op_setcond2_i32:
- if (swap_commutative2(&args[1], &args[3])) {
- args[5] = tcg_swap_cond(args[5]);
+ if (swap_commutative2(&op->args[1], &op->args[3])) {
+ op->args[5] = tcg_swap_cond(op->args[5]);
}
break;
default:
@@ -673,8 +670,8 @@ void tcg_optimize(TCGContext *s)
CASE_OP_32_64(sar):
CASE_OP_32_64(rotl):
CASE_OP_32_64(rotr):
- if (temp_is_const(args[1]) && temps[args[1]].val == 0) {
- tcg_opt_gen_movi(s, op, args, args[0], 0);
+ if (temp_is_const(op->args[1]) && temps[op->args[1]].val == 0) {
+ tcg_opt_gen_movi(s, op, op->args[0], 0);
continue;
}
break;
@@ -683,7 +680,7 @@ void tcg_optimize(TCGContext *s)
TCGOpcode neg_op;
bool have_neg;
- if (temp_is_const(args[2])) {
+ if (temp_is_const(op->args[2])) {
/* Proceed with possible constant folding. */
break;
}
@@ -697,40 +694,45 @@ void tcg_optimize(TCGContext *s)
if (!have_neg) {
break;
}
- if (temp_is_const(args[1]) && temps[args[1]].val == 0) {
+ if (temp_is_const(op->args[1])
+ && temps[op->args[1]].val == 0) {
op->opc = neg_op;
- reset_temp(args[0]);
- args[1] = args[2];
+ reset_temp(op->args[0]);
+ op->args[1] = op->args[2];
continue;
}
}
break;
CASE_OP_32_64(xor):
CASE_OP_32_64(nand):
- if (!temp_is_const(args[1])
- && temp_is_const(args[2]) && temps[args[2]].val == -1) {
+ if (!temp_is_const(op->args[1])
+ && temp_is_const(op->args[2])
+ && temps[op->args[2]].val == -1) {
i = 1;
goto try_not;
}
break;
CASE_OP_32_64(nor):
- if (!temp_is_const(args[1])
- && temp_is_const(args[2]) && temps[args[2]].val == 0) {
+ if (!temp_is_const(op->args[1])
+ && temp_is_const(op->args[2])
+ && temps[op->args[2]].val == 0) {
i = 1;
goto try_not;
}
break;
CASE_OP_32_64(andc):
- if (!temp_is_const(args[2])
- && temp_is_const(args[1]) && temps[args[1]].val == -1) {
+ if (!temp_is_const(op->args[2])
+ && temp_is_const(op->args[1])
+ && temps[op->args[1]].val == -1) {
i = 2;
goto try_not;
}
break;
CASE_OP_32_64(orc):
CASE_OP_32_64(eqv):
- if (!temp_is_const(args[2])
- && temp_is_const(args[1]) && temps[args[1]].val == 0) {
+ if (!temp_is_const(op->args[2])
+ && temp_is_const(op->args[1])
+ && temps[op->args[1]].val == 0) {
i = 2;
goto try_not;
}
@@ -751,8 +753,8 @@ void tcg_optimize(TCGContext *s)
break;
}
op->opc = not_op;
- reset_temp(args[0]);
- args[1] = args[i];
+ reset_temp(op->args[0]);
+ op->args[1] = op->args[i];
continue;
}
default:
@@ -771,18 +773,20 @@ void tcg_optimize(TCGContext *s)
CASE_OP_32_64(or):
CASE_OP_32_64(xor):
CASE_OP_32_64(andc):
- if (!temp_is_const(args[1])
- && temp_is_const(args[2]) && temps[args[2]].val == 0) {
- tcg_opt_gen_mov(s, op, args, args[0], args[1]);
+ if (!temp_is_const(op->args[1])
+ && temp_is_const(op->args[2])
+ && temps[op->args[2]].val == 0) {
+ tcg_opt_gen_mov(s, op, op->args[0], op->args[1]);
continue;
}
break;
CASE_OP_32_64(and):
CASE_OP_32_64(orc):
CASE_OP_32_64(eqv):
- if (!temp_is_const(args[1])
- && temp_is_const(args[2]) && temps[args[2]].val == -1) {
- tcg_opt_gen_mov(s, op, args, args[0], args[1]);
+ if (!temp_is_const(op->args[1])
+ && temp_is_const(op->args[2])
+ && temps[op->args[2]].val == -1) {
+ tcg_opt_gen_mov(s, op, op->args[0], op->args[1]);
continue;
}
break;
@@ -796,21 +800,21 @@ void tcg_optimize(TCGContext *s)
affected = -1;
switch (opc) {
CASE_OP_32_64(ext8s):
- if ((temps[args[1]].mask & 0x80) != 0) {
+ if ((temps[op->args[1]].mask & 0x80) != 0) {
break;
}
CASE_OP_32_64(ext8u):
mask = 0xff;
goto and_const;
CASE_OP_32_64(ext16s):
- if ((temps[args[1]].mask & 0x8000) != 0) {
+ if ((temps[op->args[1]].mask & 0x8000) != 0) {
break;
}
CASE_OP_32_64(ext16u):
mask = 0xffff;
goto and_const;
case INDEX_op_ext32s_i64:
- if ((temps[args[1]].mask & 0x80000000) != 0) {
+ if ((temps[op->args[1]].mask & 0x80000000) != 0) {
break;
}
case INDEX_op_ext32u_i64:
@@ -818,110 +822,111 @@ void tcg_optimize(TCGContext *s)
goto and_const;
CASE_OP_32_64(and):
- mask = temps[args[2]].mask;
- if (temp_is_const(args[2])) {
+ mask = temps[op->args[2]].mask;
+ if (temp_is_const(op->args[2])) {
and_const:
- affected = temps[args[1]].mask & ~mask;
+ affected = temps[op->args[1]].mask & ~mask;
}
- mask = temps[args[1]].mask & mask;
+ mask = temps[op->args[1]].mask & mask;
break;
case INDEX_op_ext_i32_i64:
- if ((temps[args[1]].mask & 0x80000000) != 0) {
+ if ((temps[op->args[1]].mask & 0x80000000) != 0) {
break;
}
case INDEX_op_extu_i32_i64:
/* We do not compute affected as it is a size changing op. */
- mask = (uint32_t)temps[args[1]].mask;
+ mask = (uint32_t)temps[op->args[1]].mask;
break;
CASE_OP_32_64(andc):
/* Known-zeros does not imply known-ones. Therefore unless
- args[2] is constant, we can't infer anything from it. */
- if (temp_is_const(args[2])) {
- mask = ~temps[args[2]].mask;
+ op->args[2] is constant, we can't infer anything from it. */
+ if (temp_is_const(op->args[2])) {
+ mask = ~temps[op->args[2]].mask;
goto and_const;
}
- /* But we certainly know nothing outside args[1] may be set. */
- mask = temps[args[1]].mask;
+ /* But we certainly know nothing outside op->args[1] may be set. */
+ mask = temps[op->args[1]].mask;
break;
case INDEX_op_sar_i32:
- if (temp_is_const(args[2])) {
- tmp = temps[args[2]].val & 31;
- mask = (int32_t)temps[args[1]].mask >> tmp;
+ if (temp_is_const(op->args[2])) {
+ tmp = temps[op->args[2]].val & 31;
+ mask = (int32_t)temps[op->args[1]].mask >> tmp;
}
break;
case INDEX_op_sar_i64:
- if (temp_is_const(args[2])) {
- tmp = temps[args[2]].val & 63;
- mask = (int64_t)temps[args[1]].mask >> tmp;
+ if (temp_is_const(op->args[2])) {
+ tmp = temps[op->args[2]].val & 63;
+ mask = (int64_t)temps[op->args[1]].mask >> tmp;
}
break;
case INDEX_op_shr_i32:
- if (temp_is_const(args[2])) {
- tmp = temps[args[2]].val & 31;
- mask = (uint32_t)temps[args[1]].mask >> tmp;
+ if (temp_is_const(op->args[2])) {
+ tmp = temps[op->args[2]].val & 31;
+ mask = (uint32_t)temps[op->args[1]].mask >> tmp;
}
break;
case INDEX_op_shr_i64:
- if (temp_is_const(args[2])) {
- tmp = temps[args[2]].val & 63;
- mask = (uint64_t)temps[args[1]].mask >> tmp;
+ if (temp_is_const(op->args[2])) {
+ tmp = temps[op->args[2]].val & 63;
+ mask = (uint64_t)temps[op->args[1]].mask >> tmp;
}
break;
case INDEX_op_extrl_i64_i32:
- mask = (uint32_t)temps[args[1]].mask;
+ mask = (uint32_t)temps[op->args[1]].mask;
break;
case INDEX_op_extrh_i64_i32:
- mask = (uint64_t)temps[args[1]].mask >> 32;
+ mask = (uint64_t)temps[op->args[1]].mask >> 32;
break;
CASE_OP_32_64(shl):
- if (temp_is_const(args[2])) {
- tmp = temps[args[2]].val & (TCG_TARGET_REG_BITS - 1);
- mask = temps[args[1]].mask << tmp;
+ if (temp_is_const(op->args[2])) {
+ tmp = temps[op->args[2]].val & (TCG_TARGET_REG_BITS - 1);
+ mask = temps[op->args[1]].mask << tmp;
}
break;
CASE_OP_32_64(neg):
/* Set to 1 all bits to the left of the rightmost. */
- mask = -(temps[args[1]].mask & -temps[args[1]].mask);
+ mask = -(temps[op->args[1]].mask & -temps[op->args[1]].mask);
break;
CASE_OP_32_64(deposit):
- mask = deposit64(temps[args[1]].mask, args[3], args[4],
- temps[args[2]].mask);
+ mask = deposit64(temps[op->args[1]].mask, op->args[3],
+ op->args[4], temps[op->args[2]].mask);
break;
CASE_OP_32_64(extract):
- mask = extract64(temps[args[1]].mask, args[2], args[3]);
- if (args[2] == 0) {
- affected = temps[args[1]].mask & ~mask;
+ mask = extract64(temps[op->args[1]].mask, op->args[2], op->args[3]);
+ if (op->args[2] == 0) {
+ affected = temps[op->args[1]].mask & ~mask;
}
break;
CASE_OP_32_64(sextract):
- mask = sextract64(temps[args[1]].mask, args[2], args[3]);
- if (args[2] == 0 && (tcg_target_long)mask >= 0) {
- affected = temps[args[1]].mask & ~mask;
+ mask = sextract64(temps[op->args[1]].mask,
+ op->args[2], op->args[3]);
+ if (op->args[2] == 0 && (tcg_target_long)mask >= 0) {
+ affected = temps[op->args[1]].mask & ~mask;
}
break;
CASE_OP_32_64(or):
CASE_OP_32_64(xor):
- mask = temps[args[1]].mask | temps[args[2]].mask;
+ mask = temps[op->args[1]].mask | temps[op->args[2]].mask;
break;
case INDEX_op_clz_i32:
case INDEX_op_ctz_i32:
- mask = temps[args[2]].mask | 31;
+ mask = temps[op->args[2]].mask | 31;
break;
case INDEX_op_clz_i64:
case INDEX_op_ctz_i64:
- mask = temps[args[2]].mask | 63;
+ mask = temps[op->args[2]].mask | 63;
break;
case INDEX_op_ctpop_i32:
@@ -937,7 +942,7 @@ void tcg_optimize(TCGContext *s)
break;
CASE_OP_32_64(movcond):
- mask = temps[args[3]].mask | temps[args[4]].mask;
+ mask = temps[op->args[3]].mask | temps[op->args[4]].mask;
break;
CASE_OP_32_64(ld8u):
@@ -952,7 +957,7 @@ void tcg_optimize(TCGContext *s)
CASE_OP_32_64(qemu_ld):
{
- TCGMemOpIdx oi = args[nb_oargs + nb_iargs];
+ TCGMemOpIdx oi = op->args[nb_oargs + nb_iargs];
TCGMemOp mop = get_memop(oi);
if (!(mop & MO_SIGN)) {
mask = (2ULL << ((8 << (mop & MO_SIZE)) - 1)) - 1;
@@ -976,12 +981,12 @@ void tcg_optimize(TCGContext *s)
if (partmask == 0) {
tcg_debug_assert(nb_oargs == 1);
- tcg_opt_gen_movi(s, op, args, args[0], 0);
+ tcg_opt_gen_movi(s, op, op->args[0], 0);
continue;
}
if (affected == 0) {
tcg_debug_assert(nb_oargs == 1);
- tcg_opt_gen_mov(s, op, args, args[0], args[1]);
+ tcg_opt_gen_mov(s, op, op->args[0], op->args[1]);
continue;
}
@@ -991,8 +996,8 @@ void tcg_optimize(TCGContext *s)
CASE_OP_32_64(mul):
CASE_OP_32_64(muluh):
CASE_OP_32_64(mulsh):
- if ((temp_is_const(args[2]) && temps[args[2]].val == 0)) {
- tcg_opt_gen_movi(s, op, args, args[0], 0);
+ if ((temp_is_const(op->args[2]) && temps[op->args[2]].val == 0)) {
+ tcg_opt_gen_movi(s, op, op->args[0], 0);
continue;
}
break;
@@ -1004,8 +1009,8 @@ void tcg_optimize(TCGContext *s)
switch (opc) {
CASE_OP_32_64(or):
CASE_OP_32_64(and):
- if (temps_are_copies(args[1], args[2])) {
- tcg_opt_gen_mov(s, op, args, args[0], args[1]);
+ if (temps_are_copies(op->args[1], op->args[2])) {
+ tcg_opt_gen_mov(s, op, op->args[0], op->args[1]);
continue;
}
break;
@@ -1018,8 +1023,8 @@ void tcg_optimize(TCGContext *s)
CASE_OP_32_64(andc):
CASE_OP_32_64(sub):
CASE_OP_32_64(xor):
- if (temps_are_copies(args[1], args[2])) {
- tcg_opt_gen_movi(s, op, args, args[0], 0);
+ if (temps_are_copies(op->args[1], op->args[2])) {
+ tcg_opt_gen_movi(s, op, op->args[0], 0);
continue;
}
break;
@@ -1032,10 +1037,10 @@ void tcg_optimize(TCGContext *s)
allocator where needed and possible. Also detect copies. */
switch (opc) {
CASE_OP_32_64(mov):
- tcg_opt_gen_mov(s, op, args, args[0], args[1]);
+ tcg_opt_gen_mov(s, op, op->args[0], op->args[1]);
break;
CASE_OP_32_64(movi):
- tcg_opt_gen_movi(s, op, args, args[0], args[1]);
+ tcg_opt_gen_movi(s, op, op->args[0], op->args[1]);
break;
CASE_OP_32_64(not):
@@ -1051,9 +1056,9 @@ void tcg_optimize(TCGContext *s)
case INDEX_op_extu_i32_i64:
case INDEX_op_extrl_i64_i32:
case INDEX_op_extrh_i64_i32:
- if (temp_is_const(args[1])) {
- tmp = do_constant_folding(opc, temps[args[1]].val, 0);
- tcg_opt_gen_movi(s, op, args, args[0], tmp);
+ if (temp_is_const(op->args[1])) {
+ tmp = do_constant_folding(opc, temps[op->args[1]].val, 0);
+ tcg_opt_gen_movi(s, op, op->args[0], tmp);
break;
}
goto do_default;
@@ -1080,68 +1085,72 @@ void tcg_optimize(TCGContext *s)
CASE_OP_32_64(divu):
CASE_OP_32_64(rem):
CASE_OP_32_64(remu):
- if (temp_is_const(args[1]) && temp_is_const(args[2])) {
- tmp = do_constant_folding(opc, temps[args[1]].val,
- temps[args[2]].val);
- tcg_opt_gen_movi(s, op, args, args[0], tmp);
+ if (temp_is_const(op->args[1]) && temp_is_const(op->args[2])) {
+ tmp = do_constant_folding(opc, temps[op->args[1]].val,
+ temps[op->args[2]].val);
+ tcg_opt_gen_movi(s, op, op->args[0], tmp);
break;
}
goto do_default;
CASE_OP_32_64(clz):
CASE_OP_32_64(ctz):
- if (temp_is_const(args[1])) {
- TCGArg v = temps[args[1]].val;
+ if (temp_is_const(op->args[1])) {
+ TCGArg v = temps[op->args[1]].val;
if (v != 0) {
tmp = do_constant_folding(opc, v, 0);
- tcg_opt_gen_movi(s, op, args, args[0], tmp);
+ tcg_opt_gen_movi(s, op, op->args[0], tmp);
} else {
- tcg_opt_gen_mov(s, op, args, args[0], args[2]);
+ tcg_opt_gen_mov(s, op, op->args[0], op->args[2]);
}
break;
}
goto do_default;
CASE_OP_32_64(deposit):
- if (temp_is_const(args[1]) && temp_is_const(args[2])) {
- tmp = deposit64(temps[args[1]].val, args[3], args[4],
- temps[args[2]].val);
- tcg_opt_gen_movi(s, op, args, args[0], tmp);
+ if (temp_is_const(op->args[1]) && temp_is_const(op->args[2])) {
+ tmp = deposit64(temps[op->args[1]].val, op->args[3],
+ op->args[4], temps[op->args[2]].val);
+ tcg_opt_gen_movi(s, op, op->args[0], tmp);
break;
}
goto do_default;
CASE_OP_32_64(extract):
- if (temp_is_const(args[1])) {
- tmp = extract64(temps[args[1]].val, args[2], args[3]);
- tcg_opt_gen_movi(s, op, args, args[0], tmp);
+ if (temp_is_const(op->args[1])) {
+ tmp = extract64(temps[op->args[1]].val,
+ op->args[2], op->args[3]);
+ tcg_opt_gen_movi(s, op, op->args[0], tmp);
break;
}
goto do_default;
CASE_OP_32_64(sextract):
- if (temp_is_const(args[1])) {
- tmp = sextract64(temps[args[1]].val, args[2], args[3]);
- tcg_opt_gen_movi(s, op, args, args[0], tmp);
+ if (temp_is_const(op->args[1])) {
+ tmp = sextract64(temps[op->args[1]].val,
+ op->args[2], op->args[3]);
+ tcg_opt_gen_movi(s, op, op->args[0], tmp);
break;
}
goto do_default;
CASE_OP_32_64(setcond):
- tmp = do_constant_folding_cond(opc, args[1], args[2], args[3]);
+ tmp = do_constant_folding_cond(opc, op->args[1],
+ op->args[2], op->args[3]);
if (tmp != 2) {
- tcg_opt_gen_movi(s, op, args, args[0], tmp);
+ tcg_opt_gen_movi(s, op, op->args[0], tmp);
break;
}
goto do_default;
CASE_OP_32_64(brcond):
- tmp = do_constant_folding_cond(opc, args[0], args[1], args[2]);
+ tmp = do_constant_folding_cond(opc, op->args[0],
+ op->args[1], op->args[2]);
if (tmp != 2) {
if (tmp) {
reset_all_temps(nb_temps);
op->opc = INDEX_op_br;
- args[0] = args[3];
+ op->args[0] = op->args[3];
} else {
tcg_op_remove(s, op);
}
@@ -1150,21 +1159,22 @@ void tcg_optimize(TCGContext *s)
goto do_default;
CASE_OP_32_64(movcond):
- tmp = do_constant_folding_cond(opc, args[1], args[2], args[5]);
+ tmp = do_constant_folding_cond(opc, op->args[1],
+ op->args[2], op->args[5]);
if (tmp != 2) {
- tcg_opt_gen_mov(s, op, args, args[0], args[4-tmp]);
+ tcg_opt_gen_mov(s, op, op->args[0], op->args[4-tmp]);
break;
}
- if (temp_is_const(args[3]) && temp_is_const(args[4])) {
- tcg_target_ulong tv = temps[args[3]].val;
- tcg_target_ulong fv = temps[args[4]].val;
- TCGCond cond = args[5];
+ if (temp_is_const(op->args[3]) && temp_is_const(op->args[4])) {
+ tcg_target_ulong tv = temps[op->args[3]].val;
+ tcg_target_ulong fv = temps[op->args[4]].val;
+ TCGCond cond = op->args[5];
if (fv == 1 && tv == 0) {
cond = tcg_invert_cond(cond);
} else if (!(tv == 1 && fv == 0)) {
goto do_default;
}
- args[3] = cond;
+ op->args[3] = cond;
op->opc = opc = (opc == INDEX_op_movcond_i32
? INDEX_op_setcond_i32
: INDEX_op_setcond_i64);
@@ -1174,17 +1184,16 @@ void tcg_optimize(TCGContext *s)
case INDEX_op_add2_i32:
case INDEX_op_sub2_i32:
- if (temp_is_const(args[2]) && temp_is_const(args[3])
- && temp_is_const(args[4]) && temp_is_const(args[5])) {
- uint32_t al = temps[args[2]].val;
- uint32_t ah = temps[args[3]].val;
- uint32_t bl = temps[args[4]].val;
- uint32_t bh = temps[args[5]].val;
+ if (temp_is_const(op->args[2]) && temp_is_const(op->args[3])
+ && temp_is_const(op->args[4]) && temp_is_const(op->args[5])) {
+ uint32_t al = temps[op->args[2]].val;
+ uint32_t ah = temps[op->args[3]].val;
+ uint32_t bl = temps[op->args[4]].val;
+ uint32_t bh = temps[op->args[5]].val;
uint64_t a = ((uint64_t)ah << 32) | al;
uint64_t b = ((uint64_t)bh << 32) | bl;
TCGArg rl, rh;
TCGOp *op2 = tcg_op_insert_before(s, op, INDEX_op_movi_i32, 2);
- TCGArg *args2 = op2->args;
if (opc == INDEX_op_add2_i32) {
a += b;
@@ -1192,10 +1201,10 @@ void tcg_optimize(TCGContext *s)
a -= b;
}
- rl = args[0];
- rh = args[1];
- tcg_opt_gen_movi(s, op, args, rl, (int32_t)a);
- tcg_opt_gen_movi(s, op2, args2, rh, (int32_t)(a >> 32));
+ rl = op->args[0];
+ rh = op->args[1];
+ tcg_opt_gen_movi(s, op, rl, (int32_t)a);
+ tcg_opt_gen_movi(s, op2, rh, (int32_t)(a >> 32));
/* We've done all we need to do with the movi. Skip it. */
oi_next = op2->next;
@@ -1204,18 +1213,17 @@ void tcg_optimize(TCGContext *s)
goto do_default;
case INDEX_op_mulu2_i32:
- if (temp_is_const(args[2]) && temp_is_const(args[3])) {
- uint32_t a = temps[args[2]].val;
- uint32_t b = temps[args[3]].val;
+ if (temp_is_const(op->args[2]) && temp_is_const(op->args[3])) {
+ uint32_t a = temps[op->args[2]].val;
+ uint32_t b = temps[op->args[3]].val;
uint64_t r = (uint64_t)a * b;
TCGArg rl, rh;
TCGOp *op2 = tcg_op_insert_before(s, op, INDEX_op_movi_i32, 2);
- TCGArg *args2 = op2->args;
- rl = args[0];
- rh = args[1];
- tcg_opt_gen_movi(s, op, args, rl, (int32_t)r);
- tcg_opt_gen_movi(s, op2, args2, rh, (int32_t)(r >> 32));
+ rl = op->args[0];
+ rh = op->args[1];
+ tcg_opt_gen_movi(s, op, rl, (int32_t)r);
+ tcg_opt_gen_movi(s, op2, rh, (int32_t)(r >> 32));
/* We've done all we need to do with the movi. Skip it. */
oi_next = op2->next;
@@ -1224,41 +1232,47 @@ void tcg_optimize(TCGContext *s)
goto do_default;
case INDEX_op_brcond2_i32:
- tmp = do_constant_folding_cond2(&args[0], &args[2], args[4]);
+ tmp = do_constant_folding_cond2(&op->args[0], &op->args[2],
+ op->args[4]);
if (tmp != 2) {
if (tmp) {
do_brcond_true:
reset_all_temps(nb_temps);
op->opc = INDEX_op_br;
- args[0] = args[5];
+ op->args[0] = op->args[5];
} else {
do_brcond_false:
tcg_op_remove(s, op);
}
- } else if ((args[4] == TCG_COND_LT || args[4] == TCG_COND_GE)
- && temp_is_const(args[2]) && temps[args[2]].val == 0
- && temp_is_const(args[3]) && temps[args[3]].val == 0) {
+ } else if ((op->args[4] == TCG_COND_LT
+ || op->args[4] == TCG_COND_GE)
+ && temp_is_const(op->args[2])
+ && temps[op->args[2]].val == 0
+ && temp_is_const(op->args[3])
+ && temps[op->args[3]].val == 0) {
/* Simplify LT/GE comparisons vs zero to a single compare
vs the high word of the input. */
do_brcond_high:
reset_all_temps(nb_temps);
op->opc = INDEX_op_brcond_i32;
- args[0] = args[1];
- args[1] = args[3];
- args[2] = args[4];
- args[3] = args[5];
- } else if (args[4] == TCG_COND_EQ) {
+ op->args[0] = op->args[1];
+ op->args[1] = op->args[3];
+ op->args[2] = op->args[4];
+ op->args[3] = op->args[5];
+ } else if (op->args[4] == TCG_COND_EQ) {
/* Simplify EQ comparisons where one of the pairs
can be simplified. */
tmp = do_constant_folding_cond(INDEX_op_brcond_i32,
- args[0], args[2], TCG_COND_EQ);
+ op->args[0], op->args[2],
+ TCG_COND_EQ);
if (tmp == 0) {
goto do_brcond_false;
} else if (tmp == 1) {
goto do_brcond_high;
}
tmp = do_constant_folding_cond(INDEX_op_brcond_i32,
- args[1], args[3], TCG_COND_EQ);
+ op->args[1], op->args[3],
+ TCG_COND_EQ);
if (tmp == 0) {
goto do_brcond_false;
} else if (tmp != 1) {
@@ -1267,21 +1281,23 @@ void tcg_optimize(TCGContext *s)
do_brcond_low:
reset_all_temps(nb_temps);
op->opc = INDEX_op_brcond_i32;
- args[1] = args[2];
- args[2] = args[4];
- args[3] = args[5];
- } else if (args[4] == TCG_COND_NE) {
+ op->args[1] = op->args[2];
+ op->args[2] = op->args[4];
+ op->args[3] = op->args[5];
+ } else if (op->args[4] == TCG_COND_NE) {
/* Simplify NE comparisons where one of the pairs
can be simplified. */
tmp = do_constant_folding_cond(INDEX_op_brcond_i32,
- args[0], args[2], TCG_COND_NE);
+ op->args[0], op->args[2],
+ TCG_COND_NE);
if (tmp == 0) {
goto do_brcond_high;
} else if (tmp == 1) {
goto do_brcond_true;
}
tmp = do_constant_folding_cond(INDEX_op_brcond_i32,
- args[1], args[3], TCG_COND_NE);
+ op->args[1], op->args[3],
+ TCG_COND_NE);
if (tmp == 0) {
goto do_brcond_low;
} else if (tmp == 1) {
@@ -1294,57 +1310,65 @@ void tcg_optimize(TCGContext *s)
break;
case INDEX_op_setcond2_i32:
- tmp = do_constant_folding_cond2(&args[1], &args[3], args[5]);
+ tmp = do_constant_folding_cond2(&op->args[1], &op->args[3],
+ op->args[5]);
if (tmp != 2) {
do_setcond_const:
- tcg_opt_gen_movi(s, op, args, args[0], tmp);
- } else if ((args[5] == TCG_COND_LT || args[5] == TCG_COND_GE)
- && temp_is_const(args[3]) && temps[args[3]].val == 0
- && temp_is_const(args[4]) && temps[args[4]].val == 0) {
+ tcg_opt_gen_movi(s, op, op->args[0], tmp);
+ } else if ((op->args[5] == TCG_COND_LT
+ || op->args[5] == TCG_COND_GE)
+ && temp_is_const(op->args[3])
+ && temps[op->args[3]].val == 0
+ && temp_is_const(op->args[4])
+ && temps[op->args[4]].val == 0) {
/* Simplify LT/GE comparisons vs zero to a single compare
vs the high word of the input. */
do_setcond_high:
- reset_temp(args[0]);
- temps[args[0]].mask = 1;
+ reset_temp(op->args[0]);
+ temps[op->args[0]].mask = 1;
op->opc = INDEX_op_setcond_i32;
- args[1] = args[2];
- args[2] = args[4];
- args[3] = args[5];
- } else if (args[5] == TCG_COND_EQ) {
+ op->args[1] = op->args[2];
+ op->args[2] = op->args[4];
+ op->args[3] = op->args[5];
+ } else if (op->args[5] == TCG_COND_EQ) {
/* Simplify EQ comparisons where one of the pairs
can be simplified. */
tmp = do_constant_folding_cond(INDEX_op_setcond_i32,
- args[1], args[3], TCG_COND_EQ);
+ op->args[1], op->args[3],
+ TCG_COND_EQ);
if (tmp == 0) {
goto do_setcond_const;
} else if (tmp == 1) {
goto do_setcond_high;
}
tmp = do_constant_folding_cond(INDEX_op_setcond_i32,
- args[2], args[4], TCG_COND_EQ);
+ op->args[2], op->args[4],
+ TCG_COND_EQ);
if (tmp == 0) {
goto do_setcond_high;
} else if (tmp != 1) {
goto do_default;
}
do_setcond_low:
- reset_temp(args[0]);
- temps[args[0]].mask = 1;
+ reset_temp(op->args[0]);
+ temps[op->args[0]].mask = 1;
op->opc = INDEX_op_setcond_i32;
- args[2] = args[3];
- args[3] = args[5];
- } else if (args[5] == TCG_COND_NE) {
+ op->args[2] = op->args[3];
+ op->args[3] = op->args[5];
+ } else if (op->args[5] == TCG_COND_NE) {
/* Simplify NE comparisons where one of the pairs
can be simplified. */
tmp = do_constant_folding_cond(INDEX_op_setcond_i32,
- args[1], args[3], TCG_COND_NE);
+ op->args[1], op->args[3],
+ TCG_COND_NE);
if (tmp == 0) {
goto do_setcond_high;
} else if (tmp == 1) {
goto do_setcond_const;
}
tmp = do_constant_folding_cond(INDEX_op_setcond_i32,
- args[2], args[4], TCG_COND_NE);
+ op->args[2], op->args[4],
+ TCG_COND_NE);
if (tmp == 0) {
goto do_setcond_low;
} else if (tmp == 1) {
@@ -1357,7 +1381,7 @@ void tcg_optimize(TCGContext *s)
break;
case INDEX_op_call:
- if (!(args[nb_oargs + nb_iargs + 1]
+ if (!(op->args[nb_oargs + nb_iargs + 1]
& (TCG_CALL_NO_READ_GLOBALS | TCG_CALL_NO_WRITE_GLOBALS))) {
for (i = 0; i < nb_globals; i++) {
if (test_bit(i, temps_used.l)) {
@@ -1379,11 +1403,11 @@ void tcg_optimize(TCGContext *s)
} else {
do_reset_output:
for (i = 0; i < nb_oargs; i++) {
- reset_temp(args[i]);
+ reset_temp(op->args[i]);
/* Save the corresponding known-zero bits mask for the
first output argument (only one supported so far). */
if (i == 0) {
- temps[args[i]].mask = mask;
+ temps[op->args[i]].mask = mask;
}
}
}
@@ -1391,7 +1415,7 @@ void tcg_optimize(TCGContext *s)
}
/* Eliminate duplicate and redundant fence instructions. */
- if (prev_mb_args) {
+ if (prev_mb) {
switch (opc) {
case INDEX_op_mb:
/* Merge two barriers of the same type into one,
@@ -1405,7 +1429,7 @@ void tcg_optimize(TCGContext *s)
* barrier. This is stricter than specified but for
* the purposes of TCG is better than not optimizing.
*/
- prev_mb_args[0] |= args[0];
+ prev_mb->args[0] |= op->args[0];
tcg_op_remove(s, op);
break;
@@ -1421,11 +1445,11 @@ void tcg_optimize(TCGContext *s)
case INDEX_op_qemu_st_i64:
case INDEX_op_call:
/* Opcodes that touch guest memory stop the optimization. */
- prev_mb_args = NULL;
+ prev_mb = NULL;
break;
}
} else if (opc == INDEX_op_mb) {
- prev_mb_args = args;
+ prev_mb = op;
}
}
}
--
2.13.6
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [Qemu-devel] [PULL 03/51] tcg: Propagate args to op->args in tcg.c
2017-10-25 9:34 [Qemu-devel] [PULL 00/51] tcg queued patches Richard Henderson
2017-10-25 9:34 ` [Qemu-devel] [PULL 01/51] tcg: Merge opcode arguments into TCGOp Richard Henderson
2017-10-25 9:34 ` [Qemu-devel] [PULL 02/51] tcg: Propagate args to op->args in optimizer Richard Henderson
@ 2017-10-25 9:34 ` Richard Henderson
2017-10-25 9:34 ` [Qemu-devel] [PULL 04/51] tcg: Propagate TCGOp down to allocators Richard Henderson
` (50 subsequent siblings)
53 siblings, 0 replies; 59+ messages in thread
From: Richard Henderson @ 2017-10-25 9:34 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Richard Henderson
From: Richard Henderson <rth@twiddle.net>
Reviewed-by: Emilio G. Cota <cota@braap.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/tcg.c | 121 ++++++++++++++++++++++++++++++--------------------------------
1 file changed, 58 insertions(+), 63 deletions(-)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 98673f2190..4f56077f64 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1277,14 +1277,12 @@ void tcg_dump_ops(TCGContext *s)
for (oi = s->gen_op_buf[0].next; oi != 0; oi = op->next) {
int i, k, nb_oargs, nb_iargs, nb_cargs;
const TCGOpDef *def;
- const TCGArg *args;
TCGOpcode c;
int col = 0;
op = &s->gen_op_buf[oi];
c = op->opc;
def = &tcg_op_defs[c];
- args = op->args;
if (c == INDEX_op_insn_start) {
col += qemu_log("%s ----", oi != s->gen_op_buf[0].next ? "\n" : "");
@@ -1292,9 +1290,9 @@ void tcg_dump_ops(TCGContext *s)
for (i = 0; i < TARGET_INSN_START_WORDS; ++i) {
target_ulong a;
#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
- a = ((target_ulong)args[i * 2 + 1] << 32) | args[i * 2];
+ a = deposit64(op->args[i * 2], 32, 32, op->args[i * 2 + 1]);
#else
- a = args[i];
+ a = op->args[i];
#endif
col += qemu_log(" " TARGET_FMT_lx, a);
}
@@ -1306,14 +1304,14 @@ void tcg_dump_ops(TCGContext *s)
/* function name, flags, out args */
col += qemu_log(" %s %s,$0x%" TCG_PRIlx ",$%d", def->name,
- tcg_find_helper(s, args[nb_oargs + nb_iargs]),
- args[nb_oargs + nb_iargs + 1], nb_oargs);
+ tcg_find_helper(s, op->args[nb_oargs + nb_iargs]),
+ op->args[nb_oargs + nb_iargs + 1], nb_oargs);
for (i = 0; i < nb_oargs; i++) {
col += qemu_log(",%s", tcg_get_arg_str_idx(s, buf, sizeof(buf),
- args[i]));
+ op->args[i]));
}
for (i = 0; i < nb_iargs; i++) {
- TCGArg arg = args[nb_oargs + i];
+ TCGArg arg = op->args[nb_oargs + i];
const char *t = "<dummy>";
if (arg != TCG_CALL_DUMMY_ARG) {
t = tcg_get_arg_str_idx(s, buf, sizeof(buf), arg);
@@ -1333,14 +1331,14 @@ void tcg_dump_ops(TCGContext *s)
col += qemu_log(",");
}
col += qemu_log("%s", tcg_get_arg_str_idx(s, buf, sizeof(buf),
- args[k++]));
+ op->args[k++]));
}
for (i = 0; i < nb_iargs; i++) {
if (k != 0) {
col += qemu_log(",");
}
col += qemu_log("%s", tcg_get_arg_str_idx(s, buf, sizeof(buf),
- args[k++]));
+ op->args[k++]));
}
switch (c) {
case INDEX_op_brcond_i32:
@@ -1351,10 +1349,11 @@ void tcg_dump_ops(TCGContext *s)
case INDEX_op_brcond_i64:
case INDEX_op_setcond_i64:
case INDEX_op_movcond_i64:
- if (args[k] < ARRAY_SIZE(cond_name) && cond_name[args[k]]) {
- col += qemu_log(",%s", cond_name[args[k++]]);
+ if (op->args[k] < ARRAY_SIZE(cond_name)
+ && cond_name[op->args[k]]) {
+ col += qemu_log(",%s", cond_name[op->args[k++]]);
} else {
- col += qemu_log(",$0x%" TCG_PRIlx, args[k++]);
+ col += qemu_log(",$0x%" TCG_PRIlx, op->args[k++]);
}
i = 1;
break;
@@ -1363,7 +1362,7 @@ void tcg_dump_ops(TCGContext *s)
case INDEX_op_qemu_ld_i64:
case INDEX_op_qemu_st_i64:
{
- TCGMemOpIdx oi = args[k++];
+ TCGMemOpIdx oi = op->args[k++];
TCGMemOp op = get_memop(oi);
unsigned ix = get_mmuidx(oi);
@@ -1388,14 +1387,15 @@ void tcg_dump_ops(TCGContext *s)
case INDEX_op_brcond_i32:
case INDEX_op_brcond_i64:
case INDEX_op_brcond2_i32:
- col += qemu_log("%s$L%d", k ? "," : "", arg_label(args[k])->id);
+ col += qemu_log("%s$L%d", k ? "," : "",
+ arg_label(op->args[k])->id);
i++, k++;
break;
default:
break;
}
for (; i < nb_cargs; i++, k++) {
- col += qemu_log("%s$0x%" TCG_PRIlx, k ? "," : "", args[k]);
+ col += qemu_log("%s$0x%" TCG_PRIlx, k ? "," : "", op->args[k]);
}
}
if (op->life) {
@@ -1656,7 +1656,6 @@ static void liveness_pass_1(TCGContext *s, uint8_t *temp_state)
TCGArg arg;
TCGOp * const op = &s->gen_op_buf[oi];
- TCGArg * const args = op->args;
TCGOpcode opc = op->opc;
const TCGOpDef *def = &tcg_op_defs[opc];
@@ -1669,12 +1668,12 @@ static void liveness_pass_1(TCGContext *s, uint8_t *temp_state)
nb_oargs = op->callo;
nb_iargs = op->calli;
- call_flags = args[nb_oargs + nb_iargs + 1];
+ call_flags = op->args[nb_oargs + nb_iargs + 1];
/* pure functions can be removed if their result is unused */
if (call_flags & TCG_CALL_NO_SIDE_EFFECTS) {
for (i = 0; i < nb_oargs; i++) {
- arg = args[i];
+ arg = op->args[i];
if (temp_state[arg] != TS_DEAD) {
goto do_not_remove_call;
}
@@ -1685,7 +1684,7 @@ static void liveness_pass_1(TCGContext *s, uint8_t *temp_state)
/* output args are dead */
for (i = 0; i < nb_oargs; i++) {
- arg = args[i];
+ arg = op->args[i];
if (temp_state[arg] & TS_DEAD) {
arg_life |= DEAD_ARG << i;
}
@@ -1708,7 +1707,7 @@ static void liveness_pass_1(TCGContext *s, uint8_t *temp_state)
/* record arguments that die in this helper */
for (i = nb_oargs; i < nb_iargs + nb_oargs; i++) {
- arg = args[i];
+ arg = op->args[i];
if (arg != TCG_CALL_DUMMY_ARG) {
if (temp_state[arg] & TS_DEAD) {
arg_life |= DEAD_ARG << i;
@@ -1717,7 +1716,7 @@ static void liveness_pass_1(TCGContext *s, uint8_t *temp_state)
}
/* input arguments are live for preceding opcodes */
for (i = nb_oargs; i < nb_iargs + nb_oargs; i++) {
- arg = args[i];
+ arg = op->args[i];
if (arg != TCG_CALL_DUMMY_ARG) {
temp_state[arg] &= ~TS_DEAD;
}
@@ -1729,7 +1728,7 @@ static void liveness_pass_1(TCGContext *s, uint8_t *temp_state)
break;
case INDEX_op_discard:
/* mark the temporary as dead */
- temp_state[args[0]] = TS_DEAD;
+ temp_state[op->args[0]] = TS_DEAD;
break;
case INDEX_op_add2_i32:
@@ -1750,15 +1749,15 @@ static void liveness_pass_1(TCGContext *s, uint8_t *temp_state)
the low part. The result can be optimized to a simple
add or sub. This happens often for x86_64 guest when the
cpu mode is set to 32 bit. */
- if (temp_state[args[1]] == TS_DEAD) {
- if (temp_state[args[0]] == TS_DEAD) {
+ if (temp_state[op->args[1]] == TS_DEAD) {
+ if (temp_state[op->args[0]] == TS_DEAD) {
goto do_remove;
}
/* Replace the opcode and adjust the args in place,
leaving 3 unused args at the end. */
op->opc = opc = opc_new;
- args[1] = args[2];
- args[2] = args[4];
+ op->args[1] = op->args[2];
+ op->args[2] = op->args[4];
/* Fall through and mark the single-word operation live. */
nb_iargs = 2;
nb_oargs = 1;
@@ -1788,21 +1787,21 @@ static void liveness_pass_1(TCGContext *s, uint8_t *temp_state)
do_mul2:
nb_iargs = 2;
nb_oargs = 2;
- if (temp_state[args[1]] == TS_DEAD) {
- if (temp_state[args[0]] == TS_DEAD) {
+ if (temp_state[op->args[1]] == TS_DEAD) {
+ if (temp_state[op->args[0]] == TS_DEAD) {
/* Both parts of the operation are dead. */
goto do_remove;
}
/* The high part of the operation is dead; generate the low. */
op->opc = opc = opc_new;
- args[1] = args[2];
- args[2] = args[3];
- } else if (temp_state[args[0]] == TS_DEAD && have_opc_new2) {
+ op->args[1] = op->args[2];
+ op->args[2] = op->args[3];
+ } else if (temp_state[op->args[0]] == TS_DEAD && have_opc_new2) {
/* The low part of the operation is dead; generate the high. */
op->opc = opc = opc_new2;
- args[0] = args[1];
- args[1] = args[2];
- args[2] = args[3];
+ op->args[0] = op->args[1];
+ op->args[1] = op->args[2];
+ op->args[2] = op->args[3];
} else {
goto do_not_remove;
}
@@ -1820,7 +1819,7 @@ static void liveness_pass_1(TCGContext *s, uint8_t *temp_state)
implies side effects */
if (!(def->flags & TCG_OPF_SIDE_EFFECTS) && nb_oargs != 0) {
for (i = 0; i < nb_oargs; i++) {
- if (temp_state[args[i]] != TS_DEAD) {
+ if (temp_state[op->args[i]] != TS_DEAD) {
goto do_not_remove;
}
}
@@ -1830,7 +1829,7 @@ static void liveness_pass_1(TCGContext *s, uint8_t *temp_state)
do_not_remove:
/* output args are dead */
for (i = 0; i < nb_oargs; i++) {
- arg = args[i];
+ arg = op->args[i];
if (temp_state[arg] & TS_DEAD) {
arg_life |= DEAD_ARG << i;
}
@@ -1852,14 +1851,14 @@ static void liveness_pass_1(TCGContext *s, uint8_t *temp_state)
/* record arguments that die in this opcode */
for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) {
- arg = args[i];
+ arg = op->args[i];
if (temp_state[arg] & TS_DEAD) {
arg_life |= DEAD_ARG << i;
}
}
/* input arguments are live for preceding opcodes */
for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) {
- temp_state[args[i]] &= ~TS_DEAD;
+ temp_state[op->args[i]] &= ~TS_DEAD;
}
}
break;
@@ -1894,7 +1893,6 @@ static bool liveness_pass_2(TCGContext *s, uint8_t *temp_state)
for (oi = s->gen_op_buf[0].next; oi != 0; oi = oi_next) {
TCGOp *op = &s->gen_op_buf[oi];
- TCGArg *args = op->args;
TCGOpcode opc = op->opc;
const TCGOpDef *def = &tcg_op_defs[opc];
TCGLifeData arg_life = op->life;
@@ -1906,7 +1904,7 @@ static bool liveness_pass_2(TCGContext *s, uint8_t *temp_state)
if (opc == INDEX_op_call) {
nb_oargs = op->callo;
nb_iargs = op->calli;
- call_flags = args[nb_oargs + nb_iargs + 1];
+ call_flags = op->args[nb_oargs + nb_iargs + 1];
} else {
nb_iargs = def->nb_iargs;
nb_oargs = def->nb_oargs;
@@ -1927,7 +1925,7 @@ static bool liveness_pass_2(TCGContext *s, uint8_t *temp_state)
/* Make sure that input arguments are available. */
for (i = nb_oargs; i < nb_iargs + nb_oargs; i++) {
- arg = args[i];
+ arg = op->args[i];
/* Note this unsigned test catches TCG_CALL_ARG_DUMMY too. */
if (arg < nb_globals) {
dir = dir_temps[arg];
@@ -1937,11 +1935,10 @@ static bool liveness_pass_2(TCGContext *s, uint8_t *temp_state)
? INDEX_op_ld_i32
: INDEX_op_ld_i64);
TCGOp *lop = tcg_op_insert_before(s, op, lopc, 3);
- TCGArg *largs = lop->args;
- largs[0] = dir;
- largs[1] = temp_idx(s, its->mem_base);
- largs[2] = its->mem_offset;
+ lop->args[0] = dir;
+ lop->args[1] = temp_idx(s, its->mem_base);
+ lop->args[2] = its->mem_offset;
/* Loaded, but synced with memory. */
temp_state[arg] = TS_MEM;
@@ -1953,11 +1950,11 @@ static bool liveness_pass_2(TCGContext *s, uint8_t *temp_state)
No action is required except keeping temp_state up to date
so that we reload when needed. */
for (i = nb_oargs; i < nb_iargs + nb_oargs; i++) {
- arg = args[i];
+ arg = op->args[i];
if (arg < nb_globals) {
dir = dir_temps[arg];
if (dir != 0) {
- args[i] = dir;
+ op->args[i] = dir;
changes = true;
if (IS_DEAD_ARG(i)) {
temp_state[arg] = TS_DEAD;
@@ -1988,7 +1985,7 @@ static bool liveness_pass_2(TCGContext *s, uint8_t *temp_state)
/* Outputs become available. */
for (i = 0; i < nb_oargs; i++) {
- arg = args[i];
+ arg = op->args[i];
if (arg >= nb_globals) {
continue;
}
@@ -1996,7 +1993,7 @@ static bool liveness_pass_2(TCGContext *s, uint8_t *temp_state)
if (dir == 0) {
continue;
}
- args[i] = dir;
+ op->args[i] = dir;
changes = true;
/* The output is now live and modified. */
@@ -2009,11 +2006,10 @@ static bool liveness_pass_2(TCGContext *s, uint8_t *temp_state)
? INDEX_op_st_i32
: INDEX_op_st_i64);
TCGOp *sop = tcg_op_insert_after(s, op, sopc, 3);
- TCGArg *sargs = sop->args;
- sargs[0] = dir;
- sargs[1] = temp_idx(s, its->mem_base);
- sargs[2] = its->mem_offset;
+ sop->args[0] = dir;
+ sop->args[1] = temp_idx(s, its->mem_base);
+ sop->args[2] = its->mem_offset;
temp_state[arg] = TS_MEM;
}
@@ -2841,7 +2837,6 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb)
num_insns = -1;
for (oi = s->gen_op_buf[0].next; oi != 0; oi = oi_next) {
TCGOp * const op = &s->gen_op_buf[oi];
- TCGArg * const args = op->args;
TCGOpcode opc = op->opc;
const TCGOpDef *def = &tcg_op_defs[opc];
TCGLifeData arg_life = op->life;
@@ -2854,11 +2849,11 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb)
switch (opc) {
case INDEX_op_mov_i32:
case INDEX_op_mov_i64:
- tcg_reg_alloc_mov(s, def, args, arg_life);
+ tcg_reg_alloc_mov(s, def, op->args, arg_life);
break;
case INDEX_op_movi_i32:
case INDEX_op_movi_i64:
- tcg_reg_alloc_movi(s, args, arg_life);
+ tcg_reg_alloc_movi(s, op->args, arg_life);
break;
case INDEX_op_insn_start:
if (num_insns >= 0) {
@@ -2868,22 +2863,22 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb)
for (i = 0; i < TARGET_INSN_START_WORDS; ++i) {
target_ulong a;
#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
- a = ((target_ulong)args[i * 2 + 1] << 32) | args[i * 2];
+ a = deposit64(op->args[i * 2], 32, 32, op->args[i * 2 + 1]);
#else
- a = args[i];
+ a = op->args[i];
#endif
s->gen_insn_data[num_insns][i] = a;
}
break;
case INDEX_op_discard:
- temp_dead(s, &s->temps[args[0]]);
+ temp_dead(s, &s->temps[op->args[0]]);
break;
case INDEX_op_set_label:
tcg_reg_alloc_bb_end(s, s->reserved_regs);
- tcg_out_label(s, arg_label(args[0]), s->code_ptr);
+ tcg_out_label(s, arg_label(op->args[0]), s->code_ptr);
break;
case INDEX_op_call:
- tcg_reg_alloc_call(s, op->callo, op->calli, args, arg_life);
+ tcg_reg_alloc_call(s, op->callo, op->calli, op->args, arg_life);
break;
default:
/* Sanity check that we've not introduced any unhandled opcodes. */
@@ -2891,7 +2886,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb)
/* Note: in order to speed up the code, it would be much
faster to have specialized register allocator functions for
some common argument patterns */
- tcg_reg_alloc_op(s, def, opc, args, arg_life);
+ tcg_reg_alloc_op(s, def, opc, op->args, arg_life);
break;
}
#ifdef CONFIG_DEBUG_TCG
--
2.13.6
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [Qemu-devel] [PULL 04/51] tcg: Propagate TCGOp down to allocators
2017-10-25 9:34 [Qemu-devel] [PULL 00/51] tcg queued patches Richard Henderson
` (2 preceding siblings ...)
2017-10-25 9:34 ` [Qemu-devel] [PULL 03/51] tcg: Propagate args to op->args in tcg.c Richard Henderson
@ 2017-10-25 9:34 ` Richard Henderson
2017-10-25 9:34 ` [Qemu-devel] [PULL 05/51] tcg: Introduce arg_temp Richard Henderson
` (49 subsequent siblings)
53 siblings, 0 replies; 59+ messages in thread
From: Richard Henderson @ 2017-10-25 9:34 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Richard Henderson
From: Richard Henderson <rth@twiddle.net>
Reviewed-by: Emilio G. Cota <cota@braap.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/tcg.c | 75 +++++++++++++++++++++++++++++++--------------------------------
1 file changed, 37 insertions(+), 38 deletions(-)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 4f56077f64..27c8b14295 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -2334,25 +2334,24 @@ static void tcg_reg_alloc_do_movi(TCGContext *s, TCGTemp *ots,
}
}
-static void tcg_reg_alloc_movi(TCGContext *s, const TCGArg *args,
- TCGLifeData arg_life)
+static void tcg_reg_alloc_movi(TCGContext *s, const TCGOp *op)
{
- TCGTemp *ots = &s->temps[args[0]];
- tcg_target_ulong val = args[1];
+ TCGTemp *ots = &s->temps[op->args[0]];
+ tcg_target_ulong val = op->args[1];
- tcg_reg_alloc_do_movi(s, ots, val, arg_life);
+ tcg_reg_alloc_do_movi(s, ots, val, op->life);
}
-static void tcg_reg_alloc_mov(TCGContext *s, const TCGOpDef *def,
- const TCGArg *args, TCGLifeData arg_life)
+static void tcg_reg_alloc_mov(TCGContext *s, const TCGOp *op)
{
+ const TCGLifeData arg_life = op->life;
TCGRegSet allocated_regs;
TCGTemp *ts, *ots;
TCGType otype, itype;
allocated_regs = s->reserved_regs;
- ots = &s->temps[args[0]];
- ts = &s->temps[args[1]];
+ ots = &s->temps[op->args[0]];
+ ts = &s->temps[op->args[1]];
/* Note that otype != itype for no-op truncation. */
otype = ots->type;
@@ -2382,7 +2381,7 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TCGOpDef *def,
liveness analysis disabled). */
tcg_debug_assert(NEED_SYNC_ARG(0));
if (!ots->mem_allocated) {
- temp_allocate_frame(s, args[0]);
+ temp_allocate_frame(s, op->args[0]);
}
tcg_out_st(s, otype, ts->reg, ots->mem_base->reg, ots->mem_offset);
if (IS_DEAD_ARG(1)) {
@@ -2416,10 +2415,10 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TCGOpDef *def,
}
}
-static void tcg_reg_alloc_op(TCGContext *s,
- const TCGOpDef *def, TCGOpcode opc,
- const TCGArg *args, TCGLifeData arg_life)
+static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
{
+ const TCGLifeData arg_life = op->life;
+ const TCGOpDef * const def = &tcg_op_defs[op->opc];
TCGRegSet i_allocated_regs;
TCGRegSet o_allocated_regs;
int i, k, nb_iargs, nb_oargs;
@@ -2435,16 +2434,16 @@ static void tcg_reg_alloc_op(TCGContext *s,
/* copy constants */
memcpy(new_args + nb_oargs + nb_iargs,
- args + nb_oargs + nb_iargs,
+ op->args + nb_oargs + nb_iargs,
sizeof(TCGArg) * def->nb_cargs);
i_allocated_regs = s->reserved_regs;
o_allocated_regs = s->reserved_regs;
/* satisfy input constraints */
- for(k = 0; k < nb_iargs; k++) {
+ for (k = 0; k < nb_iargs; k++) {
i = def->sorted_args[nb_oargs + k];
- arg = args[i];
+ arg = op->args[i];
arg_ct = &def->args_ct[i];
ts = &s->temps[arg];
@@ -2462,7 +2461,7 @@ static void tcg_reg_alloc_op(TCGContext *s,
if (ts->fixed_reg) {
/* if fixed register, we must allocate a new register
if the alias is not the same register */
- if (arg != args[arg_ct->alias_index])
+ if (arg != op->args[arg_ct->alias_index])
goto allocate_in_reg;
} else {
/* if the input is aliased to an output and if it is
@@ -2503,7 +2502,7 @@ static void tcg_reg_alloc_op(TCGContext *s,
/* mark dead temporaries and free the associated registers */
for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) {
if (IS_DEAD_ARG(i)) {
- temp_dead(s, &s->temps[args[i]]);
+ temp_dead(s, &s->temps[op->args[i]]);
}
}
@@ -2527,7 +2526,7 @@ static void tcg_reg_alloc_op(TCGContext *s,
/* satisfy the output constraints */
for(k = 0; k < nb_oargs; k++) {
i = def->sorted_args[k];
- arg = args[i];
+ arg = op->args[i];
arg_ct = &def->args_ct[i];
ts = &s->temps[arg];
if ((arg_ct->ct & TCG_CT_ALIAS)
@@ -2566,11 +2565,11 @@ static void tcg_reg_alloc_op(TCGContext *s,
}
/* emit instruction */
- tcg_out_op(s, opc, new_args, const_args);
+ tcg_out_op(s, op->opc, new_args, const_args);
/* move the outputs in the correct register if needed */
for(i = 0; i < nb_oargs; i++) {
- ts = &s->temps[args[i]];
+ ts = &s->temps[op->args[i]];
reg = new_args[i];
if (ts->fixed_reg && ts->reg != reg) {
tcg_out_mov(s, ts->type, ts->reg, reg);
@@ -2589,9 +2588,11 @@ static void tcg_reg_alloc_op(TCGContext *s,
#define STACK_DIR(x) (x)
#endif
-static void tcg_reg_alloc_call(TCGContext *s, int nb_oargs, int nb_iargs,
- const TCGArg * const args, TCGLifeData arg_life)
+static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op)
{
+ const int nb_oargs = op->callo;
+ const int nb_iargs = op->calli;
+ const TCGLifeData arg_life = op->life;
int flags, nb_regs, i;
TCGReg reg;
TCGArg arg;
@@ -2602,8 +2603,8 @@ static void tcg_reg_alloc_call(TCGContext *s, int nb_oargs, int nb_iargs,
int allocate_args;
TCGRegSet allocated_regs;
- func_addr = (tcg_insn_unit *)(intptr_t)args[nb_oargs + nb_iargs];
- flags = args[nb_oargs + nb_iargs + 1];
+ func_addr = (tcg_insn_unit *)(intptr_t)op->args[nb_oargs + nb_iargs];
+ flags = op->args[nb_oargs + nb_iargs + 1];
nb_regs = ARRAY_SIZE(tcg_target_call_iarg_regs);
if (nb_regs > nb_iargs) {
@@ -2622,8 +2623,8 @@ static void tcg_reg_alloc_call(TCGContext *s, int nb_oargs, int nb_iargs,
}
stack_offset = TCG_TARGET_CALL_STACK_OFFSET;
- for(i = nb_regs; i < nb_iargs; i++) {
- arg = args[nb_oargs + i];
+ for (i = nb_regs; i < nb_iargs; i++) {
+ arg = op->args[nb_oargs + i];
#ifdef TCG_TARGET_STACK_GROWSUP
stack_offset -= sizeof(tcg_target_long);
#endif
@@ -2640,8 +2641,8 @@ static void tcg_reg_alloc_call(TCGContext *s, int nb_oargs, int nb_iargs,
/* assign input registers */
allocated_regs = s->reserved_regs;
- for(i = 0; i < nb_regs; i++) {
- arg = args[nb_oargs + i];
+ for (i = 0; i < nb_regs; i++) {
+ arg = op->args[nb_oargs + i];
if (arg != TCG_CALL_DUMMY_ARG) {
ts = &s->temps[arg];
reg = tcg_target_call_iarg_regs[i];
@@ -2663,9 +2664,9 @@ static void tcg_reg_alloc_call(TCGContext *s, int nb_oargs, int nb_iargs,
}
/* mark dead temporaries and free the associated registers */
- for(i = nb_oargs; i < nb_iargs + nb_oargs; i++) {
+ for (i = nb_oargs; i < nb_iargs + nb_oargs; i++) {
if (IS_DEAD_ARG(i)) {
- temp_dead(s, &s->temps[args[i]]);
+ temp_dead(s, &s->temps[op->args[i]]);
}
}
@@ -2690,7 +2691,7 @@ static void tcg_reg_alloc_call(TCGContext *s, int nb_oargs, int nb_iargs,
/* assign output registers and emit moves if needed */
for(i = 0; i < nb_oargs; i++) {
- arg = args[i];
+ arg = op->args[i];
ts = &s->temps[arg];
reg = tcg_target_call_oarg_regs[i];
tcg_debug_assert(s->reg_to_temp[reg] == NULL);
@@ -2838,8 +2839,6 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb)
for (oi = s->gen_op_buf[0].next; oi != 0; oi = oi_next) {
TCGOp * const op = &s->gen_op_buf[oi];
TCGOpcode opc = op->opc;
- const TCGOpDef *def = &tcg_op_defs[opc];
- TCGLifeData arg_life = op->life;
oi_next = op->next;
#ifdef CONFIG_PROFILER
@@ -2849,11 +2848,11 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb)
switch (opc) {
case INDEX_op_mov_i32:
case INDEX_op_mov_i64:
- tcg_reg_alloc_mov(s, def, op->args, arg_life);
+ tcg_reg_alloc_mov(s, op);
break;
case INDEX_op_movi_i32:
case INDEX_op_movi_i64:
- tcg_reg_alloc_movi(s, op->args, arg_life);
+ tcg_reg_alloc_movi(s, op);
break;
case INDEX_op_insn_start:
if (num_insns >= 0) {
@@ -2878,7 +2877,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb)
tcg_out_label(s, arg_label(op->args[0]), s->code_ptr);
break;
case INDEX_op_call:
- tcg_reg_alloc_call(s, op->callo, op->calli, op->args, arg_life);
+ tcg_reg_alloc_call(s, op);
break;
default:
/* Sanity check that we've not introduced any unhandled opcodes. */
@@ -2886,7 +2885,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb)
/* Note: in order to speed up the code, it would be much
faster to have specialized register allocator functions for
some common argument patterns */
- tcg_reg_alloc_op(s, def, opc, op->args, arg_life);
+ tcg_reg_alloc_op(s, op);
break;
}
#ifdef CONFIG_DEBUG_TCG
--
2.13.6
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [Qemu-devel] [PULL 05/51] tcg: Introduce arg_temp
2017-10-25 9:34 [Qemu-devel] [PULL 00/51] tcg queued patches Richard Henderson
` (3 preceding siblings ...)
2017-10-25 9:34 ` [Qemu-devel] [PULL 04/51] tcg: Propagate TCGOp down to allocators Richard Henderson
@ 2017-10-25 9:34 ` Richard Henderson
2017-10-25 9:34 ` [Qemu-devel] [PULL 06/51] tcg: Add temp_global bit to TCGTemp Richard Henderson
` (48 subsequent siblings)
53 siblings, 0 replies; 59+ messages in thread
From: Richard Henderson @ 2017-10-25 9:34 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Richard Henderson
From: Richard Henderson <rth@twiddle.net>
Reviewed-by: Emilio G. Cota <cota@braap.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/tcg.h | 5 +++++
tcg/optimize.c | 4 ++--
tcg/tcg.c | 51 +++++++++++++++++++++++++--------------------------
3 files changed, 32 insertions(+), 28 deletions(-)
diff --git a/tcg/tcg.h b/tcg/tcg.h
index 2cefd9f125..f06187fd8e 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -725,6 +725,11 @@ struct TCGContext {
extern TCGContext tcg_ctx;
extern bool parallel_cpus;
+static inline TCGTemp *arg_temp(TCGArg a)
+{
+ return &tcg_ctx.temps[a];
+}
+
static inline void tcg_set_insn_param(int op_idx, int arg, TCGArg v)
{
tcg_ctx.gen_op_buf[op_idx].args[arg] = v;
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 1a1c6fb90c..d8c3a7ed56 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -133,7 +133,7 @@ static TCGArg find_better_copy(TCGContext *s, TCGArg temp)
}
/* If it is a temp, search for a temp local. */
- if (!s->temps[temp].temp_local) {
+ if (!arg_temp(temp)->temp_local) {
for (i = temps[temp].next_copy ; i != temp ; i = temps[i].next_copy) {
if (s->temps[i].temp_local) {
return i;
@@ -207,7 +207,7 @@ static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg src)
}
temps[dst].mask = mask;
- if (s->temps[src].type == s->temps[dst].type) {
+ if (arg_temp(src)->type == arg_temp(dst)->type) {
temps[dst].next_copy = temps[src].next_copy;
temps[dst].prev_copy = src;
temps[temps[dst].next_copy].prev_copy = dst;
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 27c8b14295..935f3da0a1 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1200,11 +1200,10 @@ static char *tcg_get_arg_str_ptr(TCGContext *s, char *buf, int buf_size,
return buf;
}
-static char *tcg_get_arg_str_idx(TCGContext *s, char *buf,
- int buf_size, int idx)
+static char *tcg_get_arg_str(TCGContext *s, char *buf,
+ int buf_size, TCGArg arg)
{
- tcg_debug_assert(idx >= 0 && idx < s->nb_temps);
- return tcg_get_arg_str_ptr(s, buf, buf_size, &s->temps[idx]);
+ return tcg_get_arg_str_ptr(s, buf, buf_size, arg_temp(arg));
}
/* Find helper name. */
@@ -1307,14 +1306,14 @@ void tcg_dump_ops(TCGContext *s)
tcg_find_helper(s, op->args[nb_oargs + nb_iargs]),
op->args[nb_oargs + nb_iargs + 1], nb_oargs);
for (i = 0; i < nb_oargs; i++) {
- col += qemu_log(",%s", tcg_get_arg_str_idx(s, buf, sizeof(buf),
- op->args[i]));
+ col += qemu_log(",%s", tcg_get_arg_str(s, buf, sizeof(buf),
+ op->args[i]));
}
for (i = 0; i < nb_iargs; i++) {
TCGArg arg = op->args[nb_oargs + i];
const char *t = "<dummy>";
if (arg != TCG_CALL_DUMMY_ARG) {
- t = tcg_get_arg_str_idx(s, buf, sizeof(buf), arg);
+ t = tcg_get_arg_str(s, buf, sizeof(buf), arg);
}
col += qemu_log(",%s", t);
}
@@ -1330,15 +1329,15 @@ void tcg_dump_ops(TCGContext *s)
if (k != 0) {
col += qemu_log(",");
}
- col += qemu_log("%s", tcg_get_arg_str_idx(s, buf, sizeof(buf),
- op->args[k++]));
+ col += qemu_log("%s", tcg_get_arg_str(s, buf, sizeof(buf),
+ op->args[k++]));
}
for (i = 0; i < nb_iargs; i++) {
if (k != 0) {
col += qemu_log(",");
}
- col += qemu_log("%s", tcg_get_arg_str_idx(s, buf, sizeof(buf),
- op->args[k++]));
+ col += qemu_log("%s", tcg_get_arg_str(s, buf, sizeof(buf),
+ op->args[k++]));
}
switch (c) {
case INDEX_op_brcond_i32:
@@ -1930,7 +1929,7 @@ static bool liveness_pass_2(TCGContext *s, uint8_t *temp_state)
if (arg < nb_globals) {
dir = dir_temps[arg];
if (dir != 0 && temp_state[arg] == TS_DEAD) {
- TCGTemp *its = &s->temps[arg];
+ TCGTemp *its = arg_temp(arg);
TCGOpcode lopc = (its->type == TCG_TYPE_I32
? INDEX_op_ld_i32
: INDEX_op_ld_i64);
@@ -2001,7 +2000,7 @@ static bool liveness_pass_2(TCGContext *s, uint8_t *temp_state)
/* Sync outputs upon their last write. */
if (NEED_SYNC_ARG(i)) {
- TCGTemp *its = &s->temps[arg];
+ TCGTemp *its = arg_temp(arg);
TCGOpcode sopc = (its->type == TCG_TYPE_I32
? INDEX_op_st_i32
: INDEX_op_st_i64);
@@ -2032,7 +2031,7 @@ static void dump_regs(TCGContext *s)
for(i = 0; i < s->nb_temps; i++) {
ts = &s->temps[i];
- printf(" %10s: ", tcg_get_arg_str_idx(s, buf, sizeof(buf), i));
+ printf(" %10s: ", tcg_get_arg_str_ptr(s, buf, sizeof(buf), ts));
switch(ts->val_type) {
case TEMP_VAL_REG:
printf("%s", tcg_target_reg_names[ts->reg]);
@@ -2336,7 +2335,7 @@ static void tcg_reg_alloc_do_movi(TCGContext *s, TCGTemp *ots,
static void tcg_reg_alloc_movi(TCGContext *s, const TCGOp *op)
{
- TCGTemp *ots = &s->temps[op->args[0]];
+ TCGTemp *ots = arg_temp(op->args[0]);
tcg_target_ulong val = op->args[1];
tcg_reg_alloc_do_movi(s, ots, val, op->life);
@@ -2350,8 +2349,8 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TCGOp *op)
TCGType otype, itype;
allocated_regs = s->reserved_regs;
- ots = &s->temps[op->args[0]];
- ts = &s->temps[op->args[1]];
+ ots = arg_temp(op->args[0]);
+ ts = arg_temp(op->args[1]);
/* Note that otype != itype for no-op truncation. */
otype = ots->type;
@@ -2445,7 +2444,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
i = def->sorted_args[nb_oargs + k];
arg = op->args[i];
arg_ct = &def->args_ct[i];
- ts = &s->temps[arg];
+ ts = arg_temp(arg);
if (ts->val_type == TEMP_VAL_CONST
&& tcg_target_const_match(ts->val, ts->type, arg_ct)) {
@@ -2502,7 +2501,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
/* mark dead temporaries and free the associated registers */
for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) {
if (IS_DEAD_ARG(i)) {
- temp_dead(s, &s->temps[op->args[i]]);
+ temp_dead(s, arg_temp(op->args[i]));
}
}
@@ -2528,7 +2527,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
i = def->sorted_args[k];
arg = op->args[i];
arg_ct = &def->args_ct[i];
- ts = &s->temps[arg];
+ ts = arg_temp(arg);
if ((arg_ct->ct & TCG_CT_ALIAS)
&& !const_args[arg_ct->alias_index]) {
reg = new_args[arg_ct->alias_index];
@@ -2569,7 +2568,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
/* move the outputs in the correct register if needed */
for(i = 0; i < nb_oargs; i++) {
- ts = &s->temps[op->args[i]];
+ ts = arg_temp(op->args[i]);
reg = new_args[i];
if (ts->fixed_reg && ts->reg != reg) {
tcg_out_mov(s, ts->type, ts->reg, reg);
@@ -2629,7 +2628,7 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op)
stack_offset -= sizeof(tcg_target_long);
#endif
if (arg != TCG_CALL_DUMMY_ARG) {
- ts = &s->temps[arg];
+ ts = arg_temp(arg);
temp_load(s, ts, tcg_target_available_regs[ts->type],
s->reserved_regs);
tcg_out_st(s, ts->type, ts->reg, TCG_REG_CALL_STACK, stack_offset);
@@ -2644,7 +2643,7 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op)
for (i = 0; i < nb_regs; i++) {
arg = op->args[nb_oargs + i];
if (arg != TCG_CALL_DUMMY_ARG) {
- ts = &s->temps[arg];
+ ts = arg_temp(arg);
reg = tcg_target_call_iarg_regs[i];
tcg_reg_free(s, reg, allocated_regs);
@@ -2666,7 +2665,7 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op)
/* mark dead temporaries and free the associated registers */
for (i = nb_oargs; i < nb_iargs + nb_oargs; i++) {
if (IS_DEAD_ARG(i)) {
- temp_dead(s, &s->temps[op->args[i]]);
+ temp_dead(s, arg_temp(op->args[i]));
}
}
@@ -2692,7 +2691,7 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op)
/* assign output registers and emit moves if needed */
for(i = 0; i < nb_oargs; i++) {
arg = op->args[i];
- ts = &s->temps[arg];
+ ts = arg_temp(arg);
reg = tcg_target_call_oarg_regs[i];
tcg_debug_assert(s->reg_to_temp[reg] == NULL);
@@ -2870,7 +2869,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb)
}
break;
case INDEX_op_discard:
- temp_dead(s, &s->temps[op->args[0]]);
+ temp_dead(s, arg_temp(op->args[0]));
break;
case INDEX_op_set_label:
tcg_reg_alloc_bb_end(s, s->reserved_regs);
--
2.13.6
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [Qemu-devel] [PULL 06/51] tcg: Add temp_global bit to TCGTemp
2017-10-25 9:34 [Qemu-devel] [PULL 00/51] tcg queued patches Richard Henderson
` (4 preceding siblings ...)
2017-10-25 9:34 ` [Qemu-devel] [PULL 05/51] tcg: Introduce arg_temp Richard Henderson
@ 2017-10-25 9:34 ` Richard Henderson
2017-10-25 9:34 ` [Qemu-devel] [PULL 07/51] tcg: Return NULL temp for TCG_CALL_DUMMY_ARG Richard Henderson
` (47 subsequent siblings)
53 siblings, 0 replies; 59+ messages in thread
From: Richard Henderson @ 2017-10-25 9:34 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Richard Henderson
From: Richard Henderson <rth@twiddle.net>
This avoids needing to test the index of a temp against nb_globals.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/tcg.h | 12 ++++++++----
tcg/optimize.c | 15 ++++++++-------
tcg/tcg.c | 11 ++++++++---
3 files changed, 24 insertions(+), 14 deletions(-)
diff --git a/tcg/tcg.h b/tcg/tcg.h
index f06187fd8e..fc4d1ed58b 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -579,10 +579,14 @@ typedef struct TCGTemp {
unsigned int indirect_base:1;
unsigned int mem_coherent:1;
unsigned int mem_allocated:1;
- unsigned int temp_local:1; /* If true, the temp is saved across
- basic blocks. Otherwise, it is not
- preserved across basic blocks. */
- unsigned int temp_allocated:1; /* never used for code gen */
+ /* If true, the temp is saved across both basic blocks and
+ translation blocks. */
+ unsigned int temp_global:1;
+ /* If true, the temp is saved across basic blocks but dead
+ at the end of translation blocks. If false, the temp is
+ dead at the end of basic blocks. */
+ unsigned int temp_local:1;
+ unsigned int temp_allocated:1;
tcg_target_long val;
struct TCGTemp *mem_base;
diff --git a/tcg/optimize.c b/tcg/optimize.c
index d8c3a7ed56..55f9e83ce8 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -116,25 +116,26 @@ static TCGOpcode op_to_movi(TCGOpcode op)
}
}
-static TCGArg find_better_copy(TCGContext *s, TCGArg temp)
+static TCGArg find_better_copy(TCGContext *s, TCGArg arg)
{
+ TCGTemp *ts = arg_temp(arg);
TCGArg i;
/* If this is already a global, we can't do better. */
- if (temp < s->nb_globals) {
- return temp;
+ if (ts->temp_global) {
+ return arg;
}
/* Search for a global first. */
- for (i = temps[temp].next_copy ; i != temp ; i = temps[i].next_copy) {
+ for (i = temps[arg].next_copy ; i != arg; i = temps[i].next_copy) {
if (i < s->nb_globals) {
return i;
}
}
/* If it is a temp, search for a temp local. */
- if (!arg_temp(temp)->temp_local) {
- for (i = temps[temp].next_copy ; i != temp ; i = temps[i].next_copy) {
+ if (!ts->temp_local) {
+ for (i = temps[arg].next_copy ; i != arg; i = temps[i].next_copy) {
if (s->temps[i].temp_local) {
return i;
}
@@ -142,7 +143,7 @@ static TCGArg find_better_copy(TCGContext *s, TCGArg temp)
}
/* Failure to find a better representation, return the same temp. */
- return temp;
+ return arg;
}
static bool temps_are_copies(TCGArg arg1, TCGArg arg2)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 935f3da0a1..e2a5f3f4c2 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -489,9 +489,14 @@ static inline TCGTemp *tcg_temp_alloc(TCGContext *s)
static inline TCGTemp *tcg_global_alloc(TCGContext *s)
{
+ TCGTemp *ts;
+
tcg_debug_assert(s->nb_globals == s->nb_temps);
s->nb_globals++;
- return tcg_temp_alloc(s);
+ ts = tcg_temp_alloc(s);
+ ts->temp_global = 1;
+
+ return ts;
}
static int tcg_global_reg_new_internal(TCGContext *s, TCGType type,
@@ -1190,7 +1195,7 @@ static char *tcg_get_arg_str_ptr(TCGContext *s, char *buf, int buf_size,
{
int idx = temp_idx(s, ts);
- if (idx < s->nb_globals) {
+ if (ts->temp_global) {
pstrcpy(buf, buf_size, ts->name);
} else if (ts->temp_local) {
snprintf(buf, buf_size, "loc%d", idx - s->nb_globals);
@@ -2128,7 +2133,7 @@ static void temp_free_or_dead(TCGContext *s, TCGTemp *ts, int free_or_dead)
}
ts->val_type = (free_or_dead < 0
|| ts->temp_local
- || temp_idx(s, ts) < s->nb_globals
+ || ts->temp_global
? TEMP_VAL_MEM : TEMP_VAL_DEAD);
}
--
2.13.6
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [Qemu-devel] [PULL 07/51] tcg: Return NULL temp for TCG_CALL_DUMMY_ARG
2017-10-25 9:34 [Qemu-devel] [PULL 00/51] tcg queued patches Richard Henderson
` (5 preceding siblings ...)
2017-10-25 9:34 ` [Qemu-devel] [PULL 06/51] tcg: Add temp_global bit to TCGTemp Richard Henderson
@ 2017-10-25 9:34 ` Richard Henderson
2017-10-25 9:34 ` [Qemu-devel] [PULL 08/51] tcg: Introduce temp_arg, export temp_idx Richard Henderson
` (46 subsequent siblings)
53 siblings, 0 replies; 59+ messages in thread
From: Richard Henderson @ 2017-10-25 9:34 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Richard Henderson
From: Richard Henderson <rth@twiddle.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/tcg.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tcg/tcg.h b/tcg/tcg.h
index fc4d1ed58b..5fcdec1fc5 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -731,7 +731,7 @@ extern bool parallel_cpus;
static inline TCGTemp *arg_temp(TCGArg a)
{
- return &tcg_ctx.temps[a];
+ return a == TCG_CALL_DUMMY_ARG ? NULL : &tcg_ctx.temps[a];
}
static inline void tcg_set_insn_param(int op_idx, int arg, TCGArg v)
--
2.13.6
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [Qemu-devel] [PULL 08/51] tcg: Introduce temp_arg, export temp_idx
2017-10-25 9:34 [Qemu-devel] [PULL 00/51] tcg queued patches Richard Henderson
` (6 preceding siblings ...)
2017-10-25 9:34 ` [Qemu-devel] [PULL 07/51] tcg: Return NULL temp for TCG_CALL_DUMMY_ARG Richard Henderson
@ 2017-10-25 9:34 ` Richard Henderson
2017-10-25 9:34 ` [Qemu-devel] [PULL 09/51] tcg: Use per-temp state data in liveness Richard Henderson
` (45 subsequent siblings)
53 siblings, 0 replies; 59+ messages in thread
From: Richard Henderson @ 2017-10-25 9:34 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Richard Henderson
From: Richard Henderson <rth@twiddle.net>
At the same time, drop the TCGContext argument and use tcg_ctx instead.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/tcg.h | 12 ++++++++++++
tcg/tcg.c | 19 ++++++-------------
2 files changed, 18 insertions(+), 13 deletions(-)
diff --git a/tcg/tcg.h b/tcg/tcg.h
index 5fcdec1fc5..828c1e70e5 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -729,6 +729,18 @@ struct TCGContext {
extern TCGContext tcg_ctx;
extern bool parallel_cpus;
+static inline size_t temp_idx(TCGTemp *ts)
+{
+ ptrdiff_t n = ts - tcg_ctx.temps;
+ tcg_debug_assert(n >= 0 && n < tcg_ctx.nb_temps);
+ return n;
+}
+
+static inline TCGArg temp_arg(TCGTemp *ts)
+{
+ return temp_idx(ts);
+}
+
static inline TCGTemp *arg_temp(TCGArg a)
{
return a == TCG_CALL_DUMMY_ARG ? NULL : &tcg_ctx.temps[a];
diff --git a/tcg/tcg.c b/tcg/tcg.c
index e2a5f3f4c2..f6e76df3ba 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -473,13 +473,6 @@ void tcg_func_start(TCGContext *s)
s->gen_next_op_idx = 1;
}
-static inline int temp_idx(TCGContext *s, TCGTemp *ts)
-{
- ptrdiff_t n = ts - s->temps;
- tcg_debug_assert(n >= 0 && n < s->nb_temps);
- return n;
-}
-
static inline TCGTemp *tcg_temp_alloc(TCGContext *s)
{
int n = s->nb_temps++;
@@ -516,7 +509,7 @@ static int tcg_global_reg_new_internal(TCGContext *s, TCGType type,
ts->name = name;
tcg_regset_set_reg(s->reserved_regs, reg);
- return temp_idx(s, ts);
+ return temp_idx(ts);
}
void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size)
@@ -605,7 +598,7 @@ int tcg_global_mem_new_internal(TCGType type, TCGv_ptr base,
ts->mem_offset = offset;
ts->name = name;
}
- return temp_idx(s, ts);
+ return temp_idx(ts);
}
static int tcg_temp_new_internal(TCGType type, int temp_local)
@@ -645,7 +638,7 @@ static int tcg_temp_new_internal(TCGType type, int temp_local)
ts->temp_allocated = 1;
ts->temp_local = temp_local;
}
- idx = temp_idx(s, ts);
+ idx = temp_idx(ts);
}
#if defined(CONFIG_DEBUG_TCG)
@@ -1193,7 +1186,7 @@ static void tcg_reg_alloc_start(TCGContext *s)
static char *tcg_get_arg_str_ptr(TCGContext *s, char *buf, int buf_size,
TCGTemp *ts)
{
- int idx = temp_idx(s, ts);
+ int idx = temp_idx(ts);
if (ts->temp_global) {
pstrcpy(buf, buf_size, ts->name);
@@ -1941,7 +1934,7 @@ static bool liveness_pass_2(TCGContext *s, uint8_t *temp_state)
TCGOp *lop = tcg_op_insert_before(s, op, lopc, 3);
lop->args[0] = dir;
- lop->args[1] = temp_idx(s, its->mem_base);
+ lop->args[1] = temp_arg(its->mem_base);
lop->args[2] = its->mem_offset;
/* Loaded, but synced with memory. */
@@ -2012,7 +2005,7 @@ static bool liveness_pass_2(TCGContext *s, uint8_t *temp_state)
TCGOp *sop = tcg_op_insert_after(s, op, sopc, 3);
sop->args[0] = dir;
- sop->args[1] = temp_idx(s, its->mem_base);
+ sop->args[1] = temp_arg(its->mem_base);
sop->args[2] = its->mem_offset;
temp_state[arg] = TS_MEM;
--
2.13.6
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [Qemu-devel] [PULL 09/51] tcg: Use per-temp state data in liveness
2017-10-25 9:34 [Qemu-devel] [PULL 00/51] tcg queued patches Richard Henderson
` (7 preceding siblings ...)
2017-10-25 9:34 ` [Qemu-devel] [PULL 08/51] tcg: Introduce temp_arg, export temp_idx Richard Henderson
@ 2017-10-25 9:34 ` Richard Henderson
2017-10-25 9:34 ` [Qemu-devel] [PULL 10/51] tcg: Avoid loops against variable bounds Richard Henderson
` (44 subsequent siblings)
53 siblings, 0 replies; 59+ messages in thread
From: Richard Henderson @ 2017-10-25 9:34 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Richard Henderson
From: Richard Henderson <rth@twiddle.net>
This avoids having to allocate external memory for each temporary.
Reviewed-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/tcg.h | 6 ++
tcg/tcg.c | 225 ++++++++++++++++++++++++++++++++------------------------------
2 files changed, 122 insertions(+), 109 deletions(-)
diff --git a/tcg/tcg.h b/tcg/tcg.h
index 828c1e70e5..0a0bc92dd9 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -592,6 +592,12 @@ typedef struct TCGTemp {
struct TCGTemp *mem_base;
intptr_t mem_offset;
const char *name;
+
+ /* Pass-specific information that can be stored for a temporary.
+ One word worth of integer data, and one pointer to data
+ allocated separately. */
+ uintptr_t state;
+ void *state_ptr;
} TCGTemp;
typedef struct TCGContext TCGContext;
diff --git a/tcg/tcg.c b/tcg/tcg.c
index f6e76df3ba..d08e34a9d8 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1615,42 +1615,54 @@ TCGOp *tcg_op_insert_after(TCGContext *s, TCGOp *old_op,
/* liveness analysis: end of function: all temps are dead, and globals
should be in memory. */
-static inline void tcg_la_func_end(TCGContext *s, uint8_t *temp_state)
+static void tcg_la_func_end(TCGContext *s)
{
- memset(temp_state, TS_DEAD | TS_MEM, s->nb_globals);
- memset(temp_state + s->nb_globals, TS_DEAD, s->nb_temps - s->nb_globals);
+ int ng = s->nb_globals;
+ int nt = s->nb_temps;
+ int i;
+
+ for (i = 0; i < ng; ++i) {
+ s->temps[i].state = TS_DEAD | TS_MEM;
+ }
+ for (i = ng; i < nt; ++i) {
+ s->temps[i].state = TS_DEAD;
+ }
}
/* liveness analysis: end of basic block: all temps are dead, globals
and local temps should be in memory. */
-static inline void tcg_la_bb_end(TCGContext *s, uint8_t *temp_state)
+static void tcg_la_bb_end(TCGContext *s)
{
- int i, n;
+ int ng = s->nb_globals;
+ int nt = s->nb_temps;
+ int i;
- tcg_la_func_end(s, temp_state);
- for (i = s->nb_globals, n = s->nb_temps; i < n; i++) {
- if (s->temps[i].temp_local) {
- temp_state[i] |= TS_MEM;
- }
+ for (i = 0; i < ng; ++i) {
+ s->temps[i].state = TS_DEAD | TS_MEM;
+ }
+ for (i = ng; i < nt; ++i) {
+ s->temps[i].state = (s->temps[i].temp_local
+ ? TS_DEAD | TS_MEM
+ : TS_DEAD);
}
}
/* Liveness analysis : update the opc_arg_life array to tell if a
given input arguments is dead. Instructions updating dead
temporaries are removed. */
-static void liveness_pass_1(TCGContext *s, uint8_t *temp_state)
+static void liveness_pass_1(TCGContext *s)
{
int nb_globals = s->nb_globals;
int oi, oi_prev;
- tcg_la_func_end(s, temp_state);
+ tcg_la_func_end(s);
for (oi = s->gen_op_buf[0].prev; oi != 0; oi = oi_prev) {
int i, nb_iargs, nb_oargs;
TCGOpcode opc_new, opc_new2;
bool have_opc_new2;
TCGLifeData arg_life = 0;
- TCGArg arg;
+ TCGTemp *arg_ts;
TCGOp * const op = &s->gen_op_buf[oi];
TCGOpcode opc = op->opc;
@@ -1670,8 +1682,8 @@ static void liveness_pass_1(TCGContext *s, uint8_t *temp_state)
/* pure functions can be removed if their result is unused */
if (call_flags & TCG_CALL_NO_SIDE_EFFECTS) {
for (i = 0; i < nb_oargs; i++) {
- arg = op->args[i];
- if (temp_state[arg] != TS_DEAD) {
+ arg_ts = arg_temp(op->args[i]);
+ if (arg_ts->state != TS_DEAD) {
goto do_not_remove_call;
}
}
@@ -1681,41 +1693,41 @@ static void liveness_pass_1(TCGContext *s, uint8_t *temp_state)
/* output args are dead */
for (i = 0; i < nb_oargs; i++) {
- arg = op->args[i];
- if (temp_state[arg] & TS_DEAD) {
+ arg_ts = arg_temp(op->args[i]);
+ if (arg_ts->state & TS_DEAD) {
arg_life |= DEAD_ARG << i;
}
- if (temp_state[arg] & TS_MEM) {
+ if (arg_ts->state & TS_MEM) {
arg_life |= SYNC_ARG << i;
}
- temp_state[arg] = TS_DEAD;
+ arg_ts->state = TS_DEAD;
}
if (!(call_flags & (TCG_CALL_NO_WRITE_GLOBALS |
TCG_CALL_NO_READ_GLOBALS))) {
/* globals should go back to memory */
- memset(temp_state, TS_DEAD | TS_MEM, nb_globals);
+ for (i = 0; i < nb_globals; i++) {
+ s->temps[i].state = TS_DEAD | TS_MEM;
+ }
} else if (!(call_flags & TCG_CALL_NO_READ_GLOBALS)) {
/* globals should be synced to memory */
for (i = 0; i < nb_globals; i++) {
- temp_state[i] |= TS_MEM;
+ s->temps[i].state |= TS_MEM;
}
}
/* record arguments that die in this helper */
for (i = nb_oargs; i < nb_iargs + nb_oargs; i++) {
- arg = op->args[i];
- if (arg != TCG_CALL_DUMMY_ARG) {
- if (temp_state[arg] & TS_DEAD) {
- arg_life |= DEAD_ARG << i;
- }
+ arg_ts = arg_temp(op->args[i]);
+ if (arg_ts && arg_ts->state & TS_DEAD) {
+ arg_life |= DEAD_ARG << i;
}
}
/* input arguments are live for preceding opcodes */
for (i = nb_oargs; i < nb_iargs + nb_oargs; i++) {
- arg = op->args[i];
- if (arg != TCG_CALL_DUMMY_ARG) {
- temp_state[arg] &= ~TS_DEAD;
+ arg_ts = arg_temp(op->args[i]);
+ if (arg_ts) {
+ arg_ts->state &= ~TS_DEAD;
}
}
}
@@ -1725,7 +1737,7 @@ static void liveness_pass_1(TCGContext *s, uint8_t *temp_state)
break;
case INDEX_op_discard:
/* mark the temporary as dead */
- temp_state[op->args[0]] = TS_DEAD;
+ arg_temp(op->args[0])->state = TS_DEAD;
break;
case INDEX_op_add2_i32:
@@ -1746,8 +1758,8 @@ static void liveness_pass_1(TCGContext *s, uint8_t *temp_state)
the low part. The result can be optimized to a simple
add or sub. This happens often for x86_64 guest when the
cpu mode is set to 32 bit. */
- if (temp_state[op->args[1]] == TS_DEAD) {
- if (temp_state[op->args[0]] == TS_DEAD) {
+ if (arg_temp(op->args[1])->state == TS_DEAD) {
+ if (arg_temp(op->args[0])->state == TS_DEAD) {
goto do_remove;
}
/* Replace the opcode and adjust the args in place,
@@ -1784,8 +1796,8 @@ static void liveness_pass_1(TCGContext *s, uint8_t *temp_state)
do_mul2:
nb_iargs = 2;
nb_oargs = 2;
- if (temp_state[op->args[1]] == TS_DEAD) {
- if (temp_state[op->args[0]] == TS_DEAD) {
+ if (arg_temp(op->args[1])->state == TS_DEAD) {
+ if (arg_temp(op->args[0])->state == TS_DEAD) {
/* Both parts of the operation are dead. */
goto do_remove;
}
@@ -1793,7 +1805,7 @@ static void liveness_pass_1(TCGContext *s, uint8_t *temp_state)
op->opc = opc = opc_new;
op->args[1] = op->args[2];
op->args[2] = op->args[3];
- } else if (temp_state[op->args[0]] == TS_DEAD && have_opc_new2) {
+ } else if (arg_temp(op->args[0])->state == TS_DEAD && have_opc_new2) {
/* The low part of the operation is dead; generate the high. */
op->opc = opc = opc_new2;
op->args[0] = op->args[1];
@@ -1816,7 +1828,7 @@ static void liveness_pass_1(TCGContext *s, uint8_t *temp_state)
implies side effects */
if (!(def->flags & TCG_OPF_SIDE_EFFECTS) && nb_oargs != 0) {
for (i = 0; i < nb_oargs; i++) {
- if (temp_state[op->args[i]] != TS_DEAD) {
+ if (arg_temp(op->args[i])->state != TS_DEAD) {
goto do_not_remove;
}
}
@@ -1826,36 +1838,36 @@ static void liveness_pass_1(TCGContext *s, uint8_t *temp_state)
do_not_remove:
/* output args are dead */
for (i = 0; i < nb_oargs; i++) {
- arg = op->args[i];
- if (temp_state[arg] & TS_DEAD) {
+ arg_ts = arg_temp(op->args[i]);
+ if (arg_ts->state & TS_DEAD) {
arg_life |= DEAD_ARG << i;
}
- if (temp_state[arg] & TS_MEM) {
+ if (arg_ts->state & TS_MEM) {
arg_life |= SYNC_ARG << i;
}
- temp_state[arg] = TS_DEAD;
+ arg_ts->state = TS_DEAD;
}
/* if end of basic block, update */
if (def->flags & TCG_OPF_BB_END) {
- tcg_la_bb_end(s, temp_state);
+ tcg_la_bb_end(s);
} else if (def->flags & TCG_OPF_SIDE_EFFECTS) {
/* globals should be synced to memory */
for (i = 0; i < nb_globals; i++) {
- temp_state[i] |= TS_MEM;
+ s->temps[i].state |= TS_MEM;
}
}
/* record arguments that die in this opcode */
for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) {
- arg = op->args[i];
- if (temp_state[arg] & TS_DEAD) {
+ arg_ts = arg_temp(op->args[i]);
+ if (arg_ts->state & TS_DEAD) {
arg_life |= DEAD_ARG << i;
}
}
/* input arguments are live for preceding opcodes */
for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) {
- temp_state[op->args[i]] &= ~TS_DEAD;
+ arg_temp(op->args[i])->state &= ~TS_DEAD;
}
}
break;
@@ -1865,16 +1877,12 @@ static void liveness_pass_1(TCGContext *s, uint8_t *temp_state)
}
/* Liveness analysis: Convert indirect regs to direct temporaries. */
-static bool liveness_pass_2(TCGContext *s, uint8_t *temp_state)
+static bool liveness_pass_2(TCGContext *s)
{
int nb_globals = s->nb_globals;
- int16_t *dir_temps;
- int i, oi, oi_next;
+ int nb_temps, i, oi, oi_next;
bool changes = false;
- dir_temps = tcg_malloc(nb_globals * sizeof(int16_t));
- memset(dir_temps, 0, nb_globals * sizeof(int16_t));
-
/* Create a temporary for each indirect global. */
for (i = 0; i < nb_globals; ++i) {
TCGTemp *its = &s->temps[i];
@@ -1882,11 +1890,18 @@ static bool liveness_pass_2(TCGContext *s, uint8_t *temp_state)
TCGTemp *dts = tcg_temp_alloc(s);
dts->type = its->type;
dts->base_type = its->base_type;
- dir_temps[i] = temp_idx(s, dts);
+ its->state_ptr = dts;
+ } else {
+ its->state_ptr = NULL;
}
+ /* All globals begin dead. */
+ its->state = TS_DEAD;
+ }
+ for (nb_temps = s->nb_temps; i < nb_temps; ++i) {
+ TCGTemp *its = &s->temps[i];
+ its->state_ptr = NULL;
+ its->state = TS_DEAD;
}
-
- memset(temp_state, TS_DEAD, nb_globals);
for (oi = s->gen_op_buf[0].next; oi != 0; oi = oi_next) {
TCGOp *op = &s->gen_op_buf[oi];
@@ -1894,7 +1909,7 @@ static bool liveness_pass_2(TCGContext *s, uint8_t *temp_state)
const TCGOpDef *def = &tcg_op_defs[opc];
TCGLifeData arg_life = op->life;
int nb_iargs, nb_oargs, call_flags;
- TCGArg arg, dir;
+ TCGTemp *arg_ts, *dir_ts;
oi_next = op->next;
@@ -1922,23 +1937,21 @@ static bool liveness_pass_2(TCGContext *s, uint8_t *temp_state)
/* Make sure that input arguments are available. */
for (i = nb_oargs; i < nb_iargs + nb_oargs; i++) {
- arg = op->args[i];
- /* Note this unsigned test catches TCG_CALL_ARG_DUMMY too. */
- if (arg < nb_globals) {
- dir = dir_temps[arg];
- if (dir != 0 && temp_state[arg] == TS_DEAD) {
- TCGTemp *its = arg_temp(arg);
- TCGOpcode lopc = (its->type == TCG_TYPE_I32
+ arg_ts = arg_temp(op->args[i]);
+ if (arg_ts) {
+ dir_ts = arg_ts->state_ptr;
+ if (dir_ts && arg_ts->state == TS_DEAD) {
+ TCGOpcode lopc = (arg_ts->type == TCG_TYPE_I32
? INDEX_op_ld_i32
: INDEX_op_ld_i64);
TCGOp *lop = tcg_op_insert_before(s, op, lopc, 3);
- lop->args[0] = dir;
- lop->args[1] = temp_arg(its->mem_base);
- lop->args[2] = its->mem_offset;
+ lop->args[0] = temp_arg(dir_ts);
+ lop->args[1] = temp_arg(arg_ts->mem_base);
+ lop->args[2] = arg_ts->mem_offset;
/* Loaded, but synced with memory. */
- temp_state[arg] = TS_MEM;
+ arg_ts->state = TS_MEM;
}
}
}
@@ -1947,14 +1960,14 @@ static bool liveness_pass_2(TCGContext *s, uint8_t *temp_state)
No action is required except keeping temp_state up to date
so that we reload when needed. */
for (i = nb_oargs; i < nb_iargs + nb_oargs; i++) {
- arg = op->args[i];
- if (arg < nb_globals) {
- dir = dir_temps[arg];
- if (dir != 0) {
- op->args[i] = dir;
+ arg_ts = arg_temp(op->args[i]);
+ if (arg_ts) {
+ dir_ts = arg_ts->state_ptr;
+ if (dir_ts) {
+ op->args[i] = temp_arg(dir_ts);
changes = true;
if (IS_DEAD_ARG(i)) {
- temp_state[arg] = TS_DEAD;
+ arg_ts->state = TS_DEAD;
}
}
}
@@ -1968,51 +1981,49 @@ static bool liveness_pass_2(TCGContext *s, uint8_t *temp_state)
for (i = 0; i < nb_globals; ++i) {
/* Liveness should see that globals are synced back,
that is, either TS_DEAD or TS_MEM. */
- tcg_debug_assert(dir_temps[i] == 0
- || temp_state[i] != 0);
+ arg_ts = &s->temps[i];
+ tcg_debug_assert(arg_ts->state_ptr == 0
+ || arg_ts->state != 0);
}
} else {
for (i = 0; i < nb_globals; ++i) {
/* Liveness should see that globals are saved back,
that is, TS_DEAD, waiting to be reloaded. */
- tcg_debug_assert(dir_temps[i] == 0
- || temp_state[i] == TS_DEAD);
+ arg_ts = &s->temps[i];
+ tcg_debug_assert(arg_ts->state_ptr == 0
+ || arg_ts->state == TS_DEAD);
}
}
/* Outputs become available. */
for (i = 0; i < nb_oargs; i++) {
- arg = op->args[i];
- if (arg >= nb_globals) {
+ arg_ts = arg_temp(op->args[i]);
+ dir_ts = arg_ts->state_ptr;
+ if (!dir_ts) {
continue;
}
- dir = dir_temps[arg];
- if (dir == 0) {
- continue;
- }
- op->args[i] = dir;
+ op->args[i] = temp_arg(dir_ts);
changes = true;
/* The output is now live and modified. */
- temp_state[arg] = 0;
+ arg_ts->state = 0;
/* Sync outputs upon their last write. */
if (NEED_SYNC_ARG(i)) {
- TCGTemp *its = arg_temp(arg);
- TCGOpcode sopc = (its->type == TCG_TYPE_I32
+ TCGOpcode sopc = (arg_ts->type == TCG_TYPE_I32
? INDEX_op_st_i32
: INDEX_op_st_i64);
TCGOp *sop = tcg_op_insert_after(s, op, sopc, 3);
- sop->args[0] = dir;
- sop->args[1] = temp_arg(its->mem_base);
- sop->args[2] = its->mem_offset;
+ sop->args[0] = temp_arg(dir_ts);
+ sop->args[1] = temp_arg(arg_ts->mem_base);
+ sop->args[2] = arg_ts->mem_offset;
- temp_state[arg] = TS_MEM;
+ arg_ts->state = TS_MEM;
}
/* Drop outputs that are dead. */
if (IS_DEAD_ARG(i)) {
- temp_state[arg] = TS_DEAD;
+ arg_ts->state = TS_DEAD;
}
}
}
@@ -2781,27 +2792,23 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb)
s->la_time -= profile_getclock();
#endif
- {
- uint8_t *temp_state = tcg_malloc(s->nb_temps + s->nb_indirects);
-
- liveness_pass_1(s, temp_state);
+ liveness_pass_1(s);
- if (s->nb_indirects > 0) {
+ if (s->nb_indirects > 0) {
#ifdef DEBUG_DISAS
- if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_IND)
- && qemu_log_in_addr_range(tb->pc))) {
- qemu_log_lock();
- qemu_log("OP before indirect lowering:\n");
- tcg_dump_ops(s);
- qemu_log("\n");
- qemu_log_unlock();
- }
+ if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_IND)
+ && qemu_log_in_addr_range(tb->pc))) {
+ qemu_log_lock();
+ qemu_log("OP before indirect lowering:\n");
+ tcg_dump_ops(s);
+ qemu_log("\n");
+ qemu_log_unlock();
+ }
#endif
- /* Replace indirect temps with direct temps. */
- if (liveness_pass_2(s, temp_state)) {
- /* If changes were made, re-run liveness. */
- liveness_pass_1(s, temp_state);
- }
+ /* Replace indirect temps with direct temps. */
+ if (liveness_pass_2(s)) {
+ /* If changes were made, re-run liveness. */
+ liveness_pass_1(s);
}
}
--
2.13.6
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [Qemu-devel] [PULL 10/51] tcg: Avoid loops against variable bounds
2017-10-25 9:34 [Qemu-devel] [PULL 00/51] tcg queued patches Richard Henderson
` (8 preceding siblings ...)
2017-10-25 9:34 ` [Qemu-devel] [PULL 09/51] tcg: Use per-temp state data in liveness Richard Henderson
@ 2017-10-25 9:34 ` Richard Henderson
2017-10-25 9:34 ` [Qemu-devel] [PULL 11/51] tcg: Change temp_allocate_frame arg to TCGTemp Richard Henderson
` (43 subsequent siblings)
53 siblings, 0 replies; 59+ messages in thread
From: Richard Henderson @ 2017-10-25 9:34 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Richard Henderson
From: Richard Henderson <rth@twiddle.net>
Copy s->nb_globals or s->nb_temps to a local variable for the purposes
of iteration. This should allow the compiler to use low-overhead
looping constructs on some hosts.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Emilio G. Cota <cota@braap.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/tcg.c | 27 ++++++++++-----------------
1 file changed, 10 insertions(+), 17 deletions(-)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index d08e34a9d8..840e65c0d4 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1159,23 +1159,16 @@ void tcg_gen_callN(TCGContext *s, void *func, TCGArg ret,
static void tcg_reg_alloc_start(TCGContext *s)
{
- int i;
+ int i, n;
TCGTemp *ts;
- for(i = 0; i < s->nb_globals; i++) {
+
+ for (i = 0, n = s->nb_globals; i < n; i++) {
ts = &s->temps[i];
- if (ts->fixed_reg) {
- ts->val_type = TEMP_VAL_REG;
- } else {
- ts->val_type = TEMP_VAL_MEM;
- }
+ ts->val_type = (ts->fixed_reg ? TEMP_VAL_REG : TEMP_VAL_MEM);
}
- for(i = s->nb_globals; i < s->nb_temps; i++) {
+ for (n = s->nb_temps; i < n; i++) {
ts = &s->temps[i];
- if (ts->temp_local) {
- ts->val_type = TEMP_VAL_MEM;
- } else {
- ts->val_type = TEMP_VAL_DEAD;
- }
+ ts->val_type = (ts->temp_local ? TEMP_VAL_MEM : TEMP_VAL_DEAD);
ts->mem_allocated = 0;
ts->fixed_reg = 0;
}
@@ -2277,9 +2270,9 @@ static void temp_save(TCGContext *s, TCGTemp *ts, TCGRegSet allocated_regs)
temporary registers needs to be allocated to store a constant. */
static void save_globals(TCGContext *s, TCGRegSet allocated_regs)
{
- int i;
+ int i, n;
- for (i = 0; i < s->nb_globals; i++) {
+ for (i = 0, n = s->nb_globals; i < n; i++) {
temp_save(s, &s->temps[i], allocated_regs);
}
}
@@ -2289,9 +2282,9 @@ static void save_globals(TCGContext *s, TCGRegSet allocated_regs)
temporary registers needs to be allocated to store a constant. */
static void sync_globals(TCGContext *s, TCGRegSet allocated_regs)
{
- int i;
+ int i, n;
- for (i = 0; i < s->nb_globals; i++) {
+ for (i = 0, n = s->nb_globals; i < n; i++) {
TCGTemp *ts = &s->temps[i];
tcg_debug_assert(ts->val_type != TEMP_VAL_REG
|| ts->fixed_reg
--
2.13.6
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [Qemu-devel] [PULL 11/51] tcg: Change temp_allocate_frame arg to TCGTemp
2017-10-25 9:34 [Qemu-devel] [PULL 00/51] tcg queued patches Richard Henderson
` (9 preceding siblings ...)
2017-10-25 9:34 ` [Qemu-devel] [PULL 10/51] tcg: Avoid loops against variable bounds Richard Henderson
@ 2017-10-25 9:34 ` Richard Henderson
2017-10-25 9:34 ` [Qemu-devel] [PULL 12/51] tcg: Remove unused TCG_CALL_DUMMY_TCGV Richard Henderson
` (42 subsequent siblings)
53 siblings, 0 replies; 59+ messages in thread
From: Richard Henderson @ 2017-10-25 9:34 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Richard Henderson
From: Richard Henderson <rth@twiddle.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/tcg.c | 8 +++-----
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 840e65c0d4..c10e73babe 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -2096,10 +2096,8 @@ static void check_regs(TCGContext *s)
}
#endif
-static void temp_allocate_frame(TCGContext *s, int temp)
+static void temp_allocate_frame(TCGContext *s, TCGTemp *ts)
{
- TCGTemp *ts;
- ts = &s->temps[temp];
#if !(defined(__sparc__) && TCG_TARGET_REG_BITS == 64)
/* Sparc64 stack is accessed with offset of 2047 */
s->current_frame_offset = (s->current_frame_offset +
@@ -2152,7 +2150,7 @@ static void temp_sync(TCGContext *s, TCGTemp *ts,
}
if (!ts->mem_coherent) {
if (!ts->mem_allocated) {
- temp_allocate_frame(s, temp_idx(s, ts));
+ temp_allocate_frame(s, ts);
}
switch (ts->val_type) {
case TEMP_VAL_CONST:
@@ -2382,7 +2380,7 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TCGOp *op)
liveness analysis disabled). */
tcg_debug_assert(NEED_SYNC_ARG(0));
if (!ots->mem_allocated) {
- temp_allocate_frame(s, op->args[0]);
+ temp_allocate_frame(s, ots);
}
tcg_out_st(s, otype, ts->reg, ots->mem_base->reg, ots->mem_offset);
if (IS_DEAD_ARG(1)) {
--
2.13.6
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [Qemu-devel] [PULL 12/51] tcg: Remove unused TCG_CALL_DUMMY_TCGV
2017-10-25 9:34 [Qemu-devel] [PULL 00/51] tcg queued patches Richard Henderson
` (10 preceding siblings ...)
2017-10-25 9:34 ` [Qemu-devel] [PULL 11/51] tcg: Change temp_allocate_frame arg to TCGTemp Richard Henderson
@ 2017-10-25 9:34 ` Richard Henderson
2017-10-25 9:34 ` [Qemu-devel] [PULL 13/51] tcg: Use per-temp state data in optimize Richard Henderson
` (41 subsequent siblings)
53 siblings, 0 replies; 59+ messages in thread
From: Richard Henderson @ 2017-10-25 9:34 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Richard Henderson
From: Richard Henderson <rth@twiddle.net>
Reviewed-by: Emilio G. Cota <cota@braap.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/tcg.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/tcg/tcg.h b/tcg/tcg.h
index 0a0bc92dd9..c50805217c 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -496,7 +496,6 @@ static inline intptr_t QEMU_ARTIFICIAL GET_TCGV_PTR(TCGv_ptr t)
#define TCG_CALL_NO_WG_SE (TCG_CALL_NO_WG | TCG_CALL_NO_SE)
/* used to align parameters */
-#define TCG_CALL_DUMMY_TCGV MAKE_TCGV_I32(-1)
#define TCG_CALL_DUMMY_ARG ((TCGArg)(-1))
/* Conditions. Note that these are laid out for easy manipulation by
--
2.13.6
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [Qemu-devel] [PULL 13/51] tcg: Use per-temp state data in optimize
2017-10-25 9:34 [Qemu-devel] [PULL 00/51] tcg queued patches Richard Henderson
` (11 preceding siblings ...)
2017-10-25 9:34 ` [Qemu-devel] [PULL 12/51] tcg: Remove unused TCG_CALL_DUMMY_TCGV Richard Henderson
@ 2017-10-25 9:34 ` Richard Henderson
2017-10-25 9:34 ` [Qemu-devel] [PULL 14/51] tcg: Push tcg_ctx into generator functions Richard Henderson
` (40 subsequent siblings)
53 siblings, 0 replies; 59+ messages in thread
From: Richard Henderson @ 2017-10-25 9:34 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Richard Henderson
From: Richard Henderson <rth@twiddle.net>
While we're touching many of the lines anyway, adjust the naming
of the functions to better distinguish when "TCGArg" vs "TCGTemp"
should be used.
Reviewed-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/tcg.h | 5 +
tcg/optimize.c | 423 ++++++++++++++++++++++++++++++++-------------------------
2 files changed, 246 insertions(+), 182 deletions(-)
diff --git a/tcg/tcg.h b/tcg/tcg.h
index c50805217c..563e7d36aa 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -751,6 +751,11 @@ static inline TCGTemp *arg_temp(TCGArg a)
return a == TCG_CALL_DUMMY_ARG ? NULL : &tcg_ctx.temps[a];
}
+static inline size_t arg_index(TCGArg a)
+{
+ return a;
+}
+
static inline void tcg_set_insn_param(int op_idx, int arg, TCGArg v)
{
tcg_ctx.gen_op_buf[op_idx].args[arg] = v;
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 55f9e83ce8..66daced167 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -34,8 +34,8 @@
struct tcg_temp_info {
bool is_const;
- uint16_t prev_copy;
- uint16_t next_copy;
+ TCGTemp *prev_copy;
+ TCGTemp *next_copy;
tcg_target_ulong val;
tcg_target_ulong mask;
};
@@ -43,25 +43,49 @@ struct tcg_temp_info {
static struct tcg_temp_info temps[TCG_MAX_TEMPS];
static TCGTempSet temps_used;
-static inline bool temp_is_const(TCGArg arg)
+static inline struct tcg_temp_info *ts_info(TCGTemp *ts)
{
- return temps[arg].is_const;
+ return ts->state_ptr;
}
-static inline bool temp_is_copy(TCGArg arg)
+static inline struct tcg_temp_info *arg_info(TCGArg arg)
{
- return temps[arg].next_copy != arg;
+ return ts_info(arg_temp(arg));
+}
+
+static inline bool ts_is_const(TCGTemp *ts)
+{
+ return ts_info(ts)->is_const;
+}
+
+static inline bool arg_is_const(TCGArg arg)
+{
+ return ts_is_const(arg_temp(arg));
+}
+
+static inline bool ts_is_copy(TCGTemp *ts)
+{
+ return ts_info(ts)->next_copy != ts;
}
/* Reset TEMP's state, possibly removing the temp for the list of copies. */
-static void reset_temp(TCGArg temp)
+static void reset_ts(TCGTemp *ts)
+{
+ struct tcg_temp_info *ti = ts_info(ts);
+ struct tcg_temp_info *pi = ts_info(ti->prev_copy);
+ struct tcg_temp_info *ni = ts_info(ti->next_copy);
+
+ ni->prev_copy = ti->prev_copy;
+ pi->next_copy = ti->next_copy;
+ ti->next_copy = ts;
+ ti->prev_copy = ts;
+ ti->is_const = false;
+ ti->mask = -1;
+}
+
+static void reset_temp(TCGArg arg)
{
- temps[temps[temp].next_copy].prev_copy = temps[temp].prev_copy;
- temps[temps[temp].prev_copy].next_copy = temps[temp].next_copy;
- temps[temp].next_copy = temp;
- temps[temp].prev_copy = temp;
- temps[temp].is_const = false;
- temps[temp].mask = -1;
+ reset_ts(arg_temp(arg));
}
/* Reset all temporaries, given that there are NB_TEMPS of them. */
@@ -71,17 +95,26 @@ static void reset_all_temps(int nb_temps)
}
/* Initialize and activate a temporary. */
-static void init_temp_info(TCGArg temp)
+static void init_ts_info(TCGTemp *ts)
{
- if (!test_bit(temp, temps_used.l)) {
- temps[temp].next_copy = temp;
- temps[temp].prev_copy = temp;
- temps[temp].is_const = false;
- temps[temp].mask = -1;
- set_bit(temp, temps_used.l);
+ size_t idx = temp_idx(ts);
+ if (!test_bit(idx, temps_used.l)) {
+ struct tcg_temp_info *ti = &temps[idx];
+
+ ts->state_ptr = ti;
+ ti->next_copy = ts;
+ ti->prev_copy = ts;
+ ti->is_const = false;
+ ti->mask = -1;
+ set_bit(idx, temps_used.l);
}
}
+static void init_arg_info(TCGArg arg)
+{
+ init_ts_info(arg_temp(arg));
+}
+
static int op_bits(TCGOpcode op)
{
const TCGOpDef *def = &tcg_op_defs[op];
@@ -116,50 +149,49 @@ static TCGOpcode op_to_movi(TCGOpcode op)
}
}
-static TCGArg find_better_copy(TCGContext *s, TCGArg arg)
+static TCGTemp *find_better_copy(TCGContext *s, TCGTemp *ts)
{
- TCGTemp *ts = arg_temp(arg);
- TCGArg i;
+ TCGTemp *i;
/* If this is already a global, we can't do better. */
if (ts->temp_global) {
- return arg;
+ return ts;
}
/* Search for a global first. */
- for (i = temps[arg].next_copy ; i != arg; i = temps[i].next_copy) {
- if (i < s->nb_globals) {
+ for (i = ts_info(ts)->next_copy; i != ts; i = ts_info(i)->next_copy) {
+ if (i->temp_global) {
return i;
}
}
/* If it is a temp, search for a temp local. */
if (!ts->temp_local) {
- for (i = temps[arg].next_copy ; i != arg; i = temps[i].next_copy) {
- if (s->temps[i].temp_local) {
+ for (i = ts_info(ts)->next_copy; i != ts; i = ts_info(i)->next_copy) {
+ if (ts->temp_local) {
return i;
}
}
}
/* Failure to find a better representation, return the same temp. */
- return arg;
+ return ts;
}
-static bool temps_are_copies(TCGArg arg1, TCGArg arg2)
+static bool ts_are_copies(TCGTemp *ts1, TCGTemp *ts2)
{
- TCGArg i;
+ TCGTemp *i;
- if (arg1 == arg2) {
+ if (ts1 == ts2) {
return true;
}
- if (!temp_is_copy(arg1) || !temp_is_copy(arg2)) {
+ if (!ts_is_copy(ts1) || !ts_is_copy(ts2)) {
return false;
}
- for (i = temps[arg1].next_copy ; i != arg1 ; i = temps[i].next_copy) {
- if (i == arg2) {
+ for (i = ts_info(ts1)->next_copy; i != ts1; i = ts_info(i)->next_copy) {
+ if (i == ts2) {
return true;
}
}
@@ -167,22 +199,28 @@ static bool temps_are_copies(TCGArg arg1, TCGArg arg2)
return false;
}
+static bool args_are_copies(TCGArg arg1, TCGArg arg2)
+{
+ return ts_are_copies(arg_temp(arg1), arg_temp(arg2));
+}
+
static void tcg_opt_gen_movi(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg val)
{
TCGOpcode new_op = op_to_movi(op->opc);
tcg_target_ulong mask;
+ struct tcg_temp_info *di = arg_info(dst);
op->opc = new_op;
reset_temp(dst);
- temps[dst].is_const = true;
- temps[dst].val = val;
+ di->is_const = true;
+ di->val = val;
mask = val;
if (TCG_TARGET_REG_BITS > 32 && new_op == INDEX_op_movi_i32) {
/* High bits of the destination are now garbage. */
mask |= ~0xffffffffull;
}
- temps[dst].mask = mask;
+ di->mask = mask;
op->args[0] = dst;
op->args[1] = val;
@@ -190,35 +228,44 @@ static void tcg_opt_gen_movi(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg val)
static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg src)
{
- if (temps_are_copies(dst, src)) {
+ TCGTemp *dst_ts = arg_temp(dst);
+ TCGTemp *src_ts = arg_temp(src);
+ struct tcg_temp_info *di;
+ struct tcg_temp_info *si;
+ tcg_target_ulong mask;
+ TCGOpcode new_op;
+
+ if (ts_are_copies(dst_ts, src_ts)) {
tcg_op_remove(s, op);
return;
}
- TCGOpcode new_op = op_to_mov(op->opc);
- tcg_target_ulong mask;
+ reset_ts(dst_ts);
+ di = ts_info(dst_ts);
+ si = ts_info(src_ts);
+ new_op = op_to_mov(op->opc);
op->opc = new_op;
+ op->args[0] = dst;
+ op->args[1] = src;
- reset_temp(dst);
- mask = temps[src].mask;
+ mask = si->mask;
if (TCG_TARGET_REG_BITS > 32 && new_op == INDEX_op_mov_i32) {
/* High bits of the destination are now garbage. */
mask |= ~0xffffffffull;
}
- temps[dst].mask = mask;
-
- if (arg_temp(src)->type == arg_temp(dst)->type) {
- temps[dst].next_copy = temps[src].next_copy;
- temps[dst].prev_copy = src;
- temps[temps[dst].next_copy].prev_copy = dst;
- temps[src].next_copy = dst;
- temps[dst].is_const = temps[src].is_const;
- temps[dst].val = temps[src].val;
- }
+ di->mask = mask;
- op->args[0] = dst;
- op->args[1] = src;
+ if (src_ts->type == dst_ts->type) {
+ struct tcg_temp_info *ni = ts_info(si->next_copy);
+
+ di->next_copy = si->next_copy;
+ di->prev_copy = src_ts;
+ ni->prev_copy = dst_ts;
+ si->next_copy = dst_ts;
+ di->is_const = si->is_const;
+ di->val = si->val;
+ }
}
static TCGArg do_constant_folding_2(TCGOpcode op, TCGArg x, TCGArg y)
@@ -465,18 +512,20 @@ static bool do_constant_folding_cond_eq(TCGCond c)
static TCGArg do_constant_folding_cond(TCGOpcode op, TCGArg x,
TCGArg y, TCGCond c)
{
- if (temp_is_const(x) && temp_is_const(y)) {
+ tcg_target_ulong xv = arg_info(x)->val;
+ tcg_target_ulong yv = arg_info(y)->val;
+ if (arg_is_const(x) && arg_is_const(y)) {
switch (op_bits(op)) {
case 32:
- return do_constant_folding_cond_32(temps[x].val, temps[y].val, c);
+ return do_constant_folding_cond_32(xv, yv, c);
case 64:
- return do_constant_folding_cond_64(temps[x].val, temps[y].val, c);
+ return do_constant_folding_cond_64(xv, yv, c);
default:
tcg_abort();
}
- } else if (temps_are_copies(x, y)) {
+ } else if (args_are_copies(x, y)) {
return do_constant_folding_cond_eq(c);
- } else if (temp_is_const(y) && temps[y].val == 0) {
+ } else if (arg_is_const(y) && yv == 0) {
switch (c) {
case TCG_COND_LTU:
return 0;
@@ -496,12 +545,15 @@ static TCGArg do_constant_folding_cond2(TCGArg *p1, TCGArg *p2, TCGCond c)
TCGArg al = p1[0], ah = p1[1];
TCGArg bl = p2[0], bh = p2[1];
- if (temp_is_const(bl) && temp_is_const(bh)) {
- uint64_t b = ((uint64_t)temps[bh].val << 32) | (uint32_t)temps[bl].val;
+ if (arg_is_const(bl) && arg_is_const(bh)) {
+ tcg_target_ulong blv = arg_info(bl)->val;
+ tcg_target_ulong bhv = arg_info(bh)->val;
+ uint64_t b = deposit64(blv, 32, 32, bhv);
- if (temp_is_const(al) && temp_is_const(ah)) {
- uint64_t a;
- a = ((uint64_t)temps[ah].val << 32) | (uint32_t)temps[al].val;
+ if (arg_is_const(al) && arg_is_const(ah)) {
+ tcg_target_ulong alv = arg_info(al)->val;
+ tcg_target_ulong ahv = arg_info(ah)->val;
+ uint64_t a = deposit64(alv, 32, 32, ahv);
return do_constant_folding_cond_64(a, b, c);
}
if (b == 0) {
@@ -515,7 +567,7 @@ static TCGArg do_constant_folding_cond2(TCGArg *p1, TCGArg *p2, TCGCond c)
}
}
}
- if (temps_are_copies(al, bl) && temps_are_copies(ah, bh)) {
+ if (args_are_copies(al, bl) && args_are_copies(ah, bh)) {
return do_constant_folding_cond_eq(c);
}
return 2;
@@ -525,8 +577,8 @@ static bool swap_commutative(TCGArg dest, TCGArg *p1, TCGArg *p2)
{
TCGArg a1 = *p1, a2 = *p2;
int sum = 0;
- sum += temp_is_const(a1);
- sum -= temp_is_const(a2);
+ sum += arg_is_const(a1);
+ sum -= arg_is_const(a2);
/* Prefer the constant in second argument, and then the form
op a, a, b, which is better handled on non-RISC hosts. */
@@ -541,10 +593,10 @@ static bool swap_commutative(TCGArg dest, TCGArg *p1, TCGArg *p2)
static bool swap_commutative2(TCGArg *p1, TCGArg *p2)
{
int sum = 0;
- sum += temp_is_const(p1[0]);
- sum += temp_is_const(p1[1]);
- sum -= temp_is_const(p2[0]);
- sum -= temp_is_const(p2[1]);
+ sum += arg_is_const(p1[0]);
+ sum += arg_is_const(p1[1]);
+ sum -= arg_is_const(p2[0]);
+ sum -= arg_is_const(p2[1]);
if (sum > 0) {
TCGArg t;
t = p1[0], p1[0] = p2[0], p2[0] = t;
@@ -586,23 +638,24 @@ void tcg_optimize(TCGContext *s)
nb_oargs = op->callo;
nb_iargs = op->calli;
for (i = 0; i < nb_oargs + nb_iargs; i++) {
- tmp = op->args[i];
- if (tmp != TCG_CALL_DUMMY_ARG) {
- init_temp_info(tmp);
+ TCGTemp *ts = arg_temp(op->args[i]);
+ if (ts) {
+ init_ts_info(ts);
}
}
} else {
nb_oargs = def->nb_oargs;
nb_iargs = def->nb_iargs;
for (i = 0; i < nb_oargs + nb_iargs; i++) {
- init_temp_info(op->args[i]);
+ init_arg_info(op->args[i]);
}
}
/* Do copy propagation */
for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) {
- if (temp_is_copy(op->args[i])) {
- op->args[i] = find_better_copy(s, op->args[i]);
+ TCGTemp *ts = arg_temp(op->args[i]);
+ if (ts && ts_is_copy(ts)) {
+ op->args[i] = temp_arg(find_better_copy(s, ts));
}
}
@@ -671,7 +724,8 @@ void tcg_optimize(TCGContext *s)
CASE_OP_32_64(sar):
CASE_OP_32_64(rotl):
CASE_OP_32_64(rotr):
- if (temp_is_const(op->args[1]) && temps[op->args[1]].val == 0) {
+ if (arg_is_const(op->args[1])
+ && arg_info(op->args[1])->val == 0) {
tcg_opt_gen_movi(s, op, op->args[0], 0);
continue;
}
@@ -681,7 +735,7 @@ void tcg_optimize(TCGContext *s)
TCGOpcode neg_op;
bool have_neg;
- if (temp_is_const(op->args[2])) {
+ if (arg_is_const(op->args[2])) {
/* Proceed with possible constant folding. */
break;
}
@@ -695,8 +749,8 @@ void tcg_optimize(TCGContext *s)
if (!have_neg) {
break;
}
- if (temp_is_const(op->args[1])
- && temps[op->args[1]].val == 0) {
+ if (arg_is_const(op->args[1])
+ && arg_info(op->args[1])->val == 0) {
op->opc = neg_op;
reset_temp(op->args[0]);
op->args[1] = op->args[2];
@@ -706,34 +760,34 @@ void tcg_optimize(TCGContext *s)
break;
CASE_OP_32_64(xor):
CASE_OP_32_64(nand):
- if (!temp_is_const(op->args[1])
- && temp_is_const(op->args[2])
- && temps[op->args[2]].val == -1) {
+ if (!arg_is_const(op->args[1])
+ && arg_is_const(op->args[2])
+ && arg_info(op->args[2])->val == -1) {
i = 1;
goto try_not;
}
break;
CASE_OP_32_64(nor):
- if (!temp_is_const(op->args[1])
- && temp_is_const(op->args[2])
- && temps[op->args[2]].val == 0) {
+ if (!arg_is_const(op->args[1])
+ && arg_is_const(op->args[2])
+ && arg_info(op->args[2])->val == 0) {
i = 1;
goto try_not;
}
break;
CASE_OP_32_64(andc):
- if (!temp_is_const(op->args[2])
- && temp_is_const(op->args[1])
- && temps[op->args[1]].val == -1) {
+ if (!arg_is_const(op->args[2])
+ && arg_is_const(op->args[1])
+ && arg_info(op->args[1])->val == -1) {
i = 2;
goto try_not;
}
break;
CASE_OP_32_64(orc):
CASE_OP_32_64(eqv):
- if (!temp_is_const(op->args[2])
- && temp_is_const(op->args[1])
- && temps[op->args[1]].val == 0) {
+ if (!arg_is_const(op->args[2])
+ && arg_is_const(op->args[1])
+ && arg_info(op->args[1])->val == 0) {
i = 2;
goto try_not;
}
@@ -774,9 +828,9 @@ void tcg_optimize(TCGContext *s)
CASE_OP_32_64(or):
CASE_OP_32_64(xor):
CASE_OP_32_64(andc):
- if (!temp_is_const(op->args[1])
- && temp_is_const(op->args[2])
- && temps[op->args[2]].val == 0) {
+ if (!arg_is_const(op->args[1])
+ && arg_is_const(op->args[2])
+ && arg_info(op->args[2])->val == 0) {
tcg_opt_gen_mov(s, op, op->args[0], op->args[1]);
continue;
}
@@ -784,9 +838,9 @@ void tcg_optimize(TCGContext *s)
CASE_OP_32_64(and):
CASE_OP_32_64(orc):
CASE_OP_32_64(eqv):
- if (!temp_is_const(op->args[1])
- && temp_is_const(op->args[2])
- && temps[op->args[2]].val == -1) {
+ if (!arg_is_const(op->args[1])
+ && arg_is_const(op->args[2])
+ && arg_info(op->args[2])->val == -1) {
tcg_opt_gen_mov(s, op, op->args[0], op->args[1]);
continue;
}
@@ -801,21 +855,21 @@ void tcg_optimize(TCGContext *s)
affected = -1;
switch (opc) {
CASE_OP_32_64(ext8s):
- if ((temps[op->args[1]].mask & 0x80) != 0) {
+ if ((arg_info(op->args[1])->mask & 0x80) != 0) {
break;
}
CASE_OP_32_64(ext8u):
mask = 0xff;
goto and_const;
CASE_OP_32_64(ext16s):
- if ((temps[op->args[1]].mask & 0x8000) != 0) {
+ if ((arg_info(op->args[1])->mask & 0x8000) != 0) {
break;
}
CASE_OP_32_64(ext16u):
mask = 0xffff;
goto and_const;
case INDEX_op_ext32s_i64:
- if ((temps[op->args[1]].mask & 0x80000000) != 0) {
+ if ((arg_info(op->args[1])->mask & 0x80000000) != 0) {
break;
}
case INDEX_op_ext32u_i64:
@@ -823,111 +877,114 @@ void tcg_optimize(TCGContext *s)
goto and_const;
CASE_OP_32_64(and):
- mask = temps[op->args[2]].mask;
- if (temp_is_const(op->args[2])) {
+ mask = arg_info(op->args[2])->mask;
+ if (arg_is_const(op->args[2])) {
and_const:
- affected = temps[op->args[1]].mask & ~mask;
+ affected = arg_info(op->args[1])->mask & ~mask;
}
- mask = temps[op->args[1]].mask & mask;
+ mask = arg_info(op->args[1])->mask & mask;
break;
case INDEX_op_ext_i32_i64:
- if ((temps[op->args[1]].mask & 0x80000000) != 0) {
+ if ((arg_info(op->args[1])->mask & 0x80000000) != 0) {
break;
}
case INDEX_op_extu_i32_i64:
/* We do not compute affected as it is a size changing op. */
- mask = (uint32_t)temps[op->args[1]].mask;
+ mask = (uint32_t)arg_info(op->args[1])->mask;
break;
CASE_OP_32_64(andc):
/* Known-zeros does not imply known-ones. Therefore unless
op->args[2] is constant, we can't infer anything from it. */
- if (temp_is_const(op->args[2])) {
- mask = ~temps[op->args[2]].mask;
+ if (arg_is_const(op->args[2])) {
+ mask = ~arg_info(op->args[2])->mask;
goto and_const;
}
- /* But we certainly know nothing outside op->args[1] may be set. */
- mask = temps[op->args[1]].mask;
+ /* But we certainly know nothing outside args[1] may be set. */
+ mask = arg_info(op->args[1])->mask;
break;
case INDEX_op_sar_i32:
- if (temp_is_const(op->args[2])) {
- tmp = temps[op->args[2]].val & 31;
- mask = (int32_t)temps[op->args[1]].mask >> tmp;
+ if (arg_is_const(op->args[2])) {
+ tmp = arg_info(op->args[2])->val & 31;
+ mask = (int32_t)arg_info(op->args[1])->mask >> tmp;
}
break;
case INDEX_op_sar_i64:
- if (temp_is_const(op->args[2])) {
- tmp = temps[op->args[2]].val & 63;
- mask = (int64_t)temps[op->args[1]].mask >> tmp;
+ if (arg_is_const(op->args[2])) {
+ tmp = arg_info(op->args[2])->val & 63;
+ mask = (int64_t)arg_info(op->args[1])->mask >> tmp;
}
break;
case INDEX_op_shr_i32:
- if (temp_is_const(op->args[2])) {
- tmp = temps[op->args[2]].val & 31;
- mask = (uint32_t)temps[op->args[1]].mask >> tmp;
+ if (arg_is_const(op->args[2])) {
+ tmp = arg_info(op->args[2])->val & 31;
+ mask = (uint32_t)arg_info(op->args[1])->mask >> tmp;
}
break;
case INDEX_op_shr_i64:
- if (temp_is_const(op->args[2])) {
- tmp = temps[op->args[2]].val & 63;
- mask = (uint64_t)temps[op->args[1]].mask >> tmp;
+ if (arg_is_const(op->args[2])) {
+ tmp = arg_info(op->args[2])->val & 63;
+ mask = (uint64_t)arg_info(op->args[1])->mask >> tmp;
}
break;
case INDEX_op_extrl_i64_i32:
- mask = (uint32_t)temps[op->args[1]].mask;
+ mask = (uint32_t)arg_info(op->args[1])->mask;
break;
case INDEX_op_extrh_i64_i32:
- mask = (uint64_t)temps[op->args[1]].mask >> 32;
+ mask = (uint64_t)arg_info(op->args[1])->mask >> 32;
break;
CASE_OP_32_64(shl):
- if (temp_is_const(op->args[2])) {
- tmp = temps[op->args[2]].val & (TCG_TARGET_REG_BITS - 1);
- mask = temps[op->args[1]].mask << tmp;
+ if (arg_is_const(op->args[2])) {
+ tmp = arg_info(op->args[2])->val & (TCG_TARGET_REG_BITS - 1);
+ mask = arg_info(op->args[1])->mask << tmp;
}
break;
CASE_OP_32_64(neg):
/* Set to 1 all bits to the left of the rightmost. */
- mask = -(temps[op->args[1]].mask & -temps[op->args[1]].mask);
+ mask = -(arg_info(op->args[1])->mask
+ & -arg_info(op->args[1])->mask);
break;
CASE_OP_32_64(deposit):
- mask = deposit64(temps[op->args[1]].mask, op->args[3],
- op->args[4], temps[op->args[2]].mask);
+ mask = deposit64(arg_info(op->args[1])->mask,
+ op->args[3], op->args[4],
+ arg_info(op->args[2])->mask);
break;
CASE_OP_32_64(extract):
- mask = extract64(temps[op->args[1]].mask, op->args[2], op->args[3]);
+ mask = extract64(arg_info(op->args[1])->mask,
+ op->args[2], op->args[3]);
if (op->args[2] == 0) {
- affected = temps[op->args[1]].mask & ~mask;
+ affected = arg_info(op->args[1])->mask & ~mask;
}
break;
CASE_OP_32_64(sextract):
- mask = sextract64(temps[op->args[1]].mask,
+ mask = sextract64(arg_info(op->args[1])->mask,
op->args[2], op->args[3]);
if (op->args[2] == 0 && (tcg_target_long)mask >= 0) {
- affected = temps[op->args[1]].mask & ~mask;
+ affected = arg_info(op->args[1])->mask & ~mask;
}
break;
CASE_OP_32_64(or):
CASE_OP_32_64(xor):
- mask = temps[op->args[1]].mask | temps[op->args[2]].mask;
+ mask = arg_info(op->args[1])->mask | arg_info(op->args[2])->mask;
break;
case INDEX_op_clz_i32:
case INDEX_op_ctz_i32:
- mask = temps[op->args[2]].mask | 31;
+ mask = arg_info(op->args[2])->mask | 31;
break;
case INDEX_op_clz_i64:
case INDEX_op_ctz_i64:
- mask = temps[op->args[2]].mask | 63;
+ mask = arg_info(op->args[2])->mask | 63;
break;
case INDEX_op_ctpop_i32:
@@ -943,7 +1000,7 @@ void tcg_optimize(TCGContext *s)
break;
CASE_OP_32_64(movcond):
- mask = temps[op->args[3]].mask | temps[op->args[4]].mask;
+ mask = arg_info(op->args[3])->mask | arg_info(op->args[4])->mask;
break;
CASE_OP_32_64(ld8u):
@@ -997,7 +1054,8 @@ void tcg_optimize(TCGContext *s)
CASE_OP_32_64(mul):
CASE_OP_32_64(muluh):
CASE_OP_32_64(mulsh):
- if ((temp_is_const(op->args[2]) && temps[op->args[2]].val == 0)) {
+ if (arg_is_const(op->args[2])
+ && arg_info(op->args[2])->val == 0) {
tcg_opt_gen_movi(s, op, op->args[0], 0);
continue;
}
@@ -1010,7 +1068,7 @@ void tcg_optimize(TCGContext *s)
switch (opc) {
CASE_OP_32_64(or):
CASE_OP_32_64(and):
- if (temps_are_copies(op->args[1], op->args[2])) {
+ if (args_are_copies(op->args[1], op->args[2])) {
tcg_opt_gen_mov(s, op, op->args[0], op->args[1]);
continue;
}
@@ -1024,7 +1082,7 @@ void tcg_optimize(TCGContext *s)
CASE_OP_32_64(andc):
CASE_OP_32_64(sub):
CASE_OP_32_64(xor):
- if (temps_are_copies(op->args[1], op->args[2])) {
+ if (args_are_copies(op->args[1], op->args[2])) {
tcg_opt_gen_movi(s, op, op->args[0], 0);
continue;
}
@@ -1057,8 +1115,8 @@ void tcg_optimize(TCGContext *s)
case INDEX_op_extu_i32_i64:
case INDEX_op_extrl_i64_i32:
case INDEX_op_extrh_i64_i32:
- if (temp_is_const(op->args[1])) {
- tmp = do_constant_folding(opc, temps[op->args[1]].val, 0);
+ if (arg_is_const(op->args[1])) {
+ tmp = do_constant_folding(opc, arg_info(op->args[1])->val, 0);
tcg_opt_gen_movi(s, op, op->args[0], tmp);
break;
}
@@ -1086,9 +1144,9 @@ void tcg_optimize(TCGContext *s)
CASE_OP_32_64(divu):
CASE_OP_32_64(rem):
CASE_OP_32_64(remu):
- if (temp_is_const(op->args[1]) && temp_is_const(op->args[2])) {
- tmp = do_constant_folding(opc, temps[op->args[1]].val,
- temps[op->args[2]].val);
+ if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) {
+ tmp = do_constant_folding(opc, arg_info(op->args[1])->val,
+ arg_info(op->args[2])->val);
tcg_opt_gen_movi(s, op, op->args[0], tmp);
break;
}
@@ -1096,8 +1154,8 @@ void tcg_optimize(TCGContext *s)
CASE_OP_32_64(clz):
CASE_OP_32_64(ctz):
- if (temp_is_const(op->args[1])) {
- TCGArg v = temps[op->args[1]].val;
+ if (arg_is_const(op->args[1])) {
+ TCGArg v = arg_info(op->args[1])->val;
if (v != 0) {
tmp = do_constant_folding(opc, v, 0);
tcg_opt_gen_movi(s, op, op->args[0], tmp);
@@ -1109,17 +1167,18 @@ void tcg_optimize(TCGContext *s)
goto do_default;
CASE_OP_32_64(deposit):
- if (temp_is_const(op->args[1]) && temp_is_const(op->args[2])) {
- tmp = deposit64(temps[op->args[1]].val, op->args[3],
- op->args[4], temps[op->args[2]].val);
+ if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) {
+ tmp = deposit64(arg_info(op->args[1])->val,
+ op->args[3], op->args[4],
+ arg_info(op->args[2])->val);
tcg_opt_gen_movi(s, op, op->args[0], tmp);
break;
}
goto do_default;
CASE_OP_32_64(extract):
- if (temp_is_const(op->args[1])) {
- tmp = extract64(temps[op->args[1]].val,
+ if (arg_is_const(op->args[1])) {
+ tmp = extract64(arg_info(op->args[1])->val,
op->args[2], op->args[3]);
tcg_opt_gen_movi(s, op, op->args[0], tmp);
break;
@@ -1127,8 +1186,8 @@ void tcg_optimize(TCGContext *s)
goto do_default;
CASE_OP_32_64(sextract):
- if (temp_is_const(op->args[1])) {
- tmp = sextract64(temps[op->args[1]].val,
+ if (arg_is_const(op->args[1])) {
+ tmp = sextract64(arg_info(op->args[1])->val,
op->args[2], op->args[3]);
tcg_opt_gen_movi(s, op, op->args[0], tmp);
break;
@@ -1166,9 +1225,9 @@ void tcg_optimize(TCGContext *s)
tcg_opt_gen_mov(s, op, op->args[0], op->args[4-tmp]);
break;
}
- if (temp_is_const(op->args[3]) && temp_is_const(op->args[4])) {
- tcg_target_ulong tv = temps[op->args[3]].val;
- tcg_target_ulong fv = temps[op->args[4]].val;
+ if (arg_is_const(op->args[3]) && arg_is_const(op->args[4])) {
+ tcg_target_ulong tv = arg_info(op->args[3])->val;
+ tcg_target_ulong fv = arg_info(op->args[4])->val;
TCGCond cond = op->args[5];
if (fv == 1 && tv == 0) {
cond = tcg_invert_cond(cond);
@@ -1185,12 +1244,12 @@ void tcg_optimize(TCGContext *s)
case INDEX_op_add2_i32:
case INDEX_op_sub2_i32:
- if (temp_is_const(op->args[2]) && temp_is_const(op->args[3])
- && temp_is_const(op->args[4]) && temp_is_const(op->args[5])) {
- uint32_t al = temps[op->args[2]].val;
- uint32_t ah = temps[op->args[3]].val;
- uint32_t bl = temps[op->args[4]].val;
- uint32_t bh = temps[op->args[5]].val;
+ if (arg_is_const(op->args[2]) && arg_is_const(op->args[3])
+ && arg_is_const(op->args[4]) && arg_is_const(op->args[5])) {
+ uint32_t al = arg_info(op->args[2])->val;
+ uint32_t ah = arg_info(op->args[3])->val;
+ uint32_t bl = arg_info(op->args[4])->val;
+ uint32_t bh = arg_info(op->args[5])->val;
uint64_t a = ((uint64_t)ah << 32) | al;
uint64_t b = ((uint64_t)bh << 32) | bl;
TCGArg rl, rh;
@@ -1214,9 +1273,9 @@ void tcg_optimize(TCGContext *s)
goto do_default;
case INDEX_op_mulu2_i32:
- if (temp_is_const(op->args[2]) && temp_is_const(op->args[3])) {
- uint32_t a = temps[op->args[2]].val;
- uint32_t b = temps[op->args[3]].val;
+ if (arg_is_const(op->args[2]) && arg_is_const(op->args[3])) {
+ uint32_t a = arg_info(op->args[2])->val;
+ uint32_t b = arg_info(op->args[3])->val;
uint64_t r = (uint64_t)a * b;
TCGArg rl, rh;
TCGOp *op2 = tcg_op_insert_before(s, op, INDEX_op_movi_i32, 2);
@@ -1247,10 +1306,10 @@ void tcg_optimize(TCGContext *s)
}
} else if ((op->args[4] == TCG_COND_LT
|| op->args[4] == TCG_COND_GE)
- && temp_is_const(op->args[2])
- && temps[op->args[2]].val == 0
- && temp_is_const(op->args[3])
- && temps[op->args[3]].val == 0) {
+ && arg_is_const(op->args[2])
+ && arg_info(op->args[2])->val == 0
+ && arg_is_const(op->args[3])
+ && arg_info(op->args[3])->val == 0) {
/* Simplify LT/GE comparisons vs zero to a single compare
vs the high word of the input. */
do_brcond_high:
@@ -1318,15 +1377,15 @@ void tcg_optimize(TCGContext *s)
tcg_opt_gen_movi(s, op, op->args[0], tmp);
} else if ((op->args[5] == TCG_COND_LT
|| op->args[5] == TCG_COND_GE)
- && temp_is_const(op->args[3])
- && temps[op->args[3]].val == 0
- && temp_is_const(op->args[4])
- && temps[op->args[4]].val == 0) {
+ && arg_is_const(op->args[3])
+ && arg_info(op->args[3])->val == 0
+ && arg_is_const(op->args[4])
+ && arg_info(op->args[4])->val == 0) {
/* Simplify LT/GE comparisons vs zero to a single compare
vs the high word of the input. */
do_setcond_high:
reset_temp(op->args[0]);
- temps[op->args[0]].mask = 1;
+ arg_info(op->args[0])->mask = 1;
op->opc = INDEX_op_setcond_i32;
op->args[1] = op->args[2];
op->args[2] = op->args[4];
@@ -1352,7 +1411,7 @@ void tcg_optimize(TCGContext *s)
}
do_setcond_low:
reset_temp(op->args[0]);
- temps[op->args[0]].mask = 1;
+ arg_info(op->args[0])->mask = 1;
op->opc = INDEX_op_setcond_i32;
op->args[2] = op->args[3];
op->args[3] = op->args[5];
@@ -1386,7 +1445,7 @@ void tcg_optimize(TCGContext *s)
& (TCG_CALL_NO_READ_GLOBALS | TCG_CALL_NO_WRITE_GLOBALS))) {
for (i = 0; i < nb_globals; i++) {
if (test_bit(i, temps_used.l)) {
- reset_temp(i);
+ reset_ts(&s->temps[i]);
}
}
}
@@ -1408,7 +1467,7 @@ void tcg_optimize(TCGContext *s)
/* Save the corresponding known-zero bits mask for the
first output argument (only one supported so far). */
if (i == 0) {
- temps[op->args[i]].mask = mask;
+ arg_info(op->args[i])->mask = mask;
}
}
}
--
2.13.6
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [Qemu-devel] [PULL 14/51] tcg: Push tcg_ctx into generator functions
2017-10-25 9:34 [Qemu-devel] [PULL 00/51] tcg queued patches Richard Henderson
` (12 preceding siblings ...)
2017-10-25 9:34 ` [Qemu-devel] [PULL 13/51] tcg: Use per-temp state data in optimize Richard Henderson
@ 2017-10-25 9:34 ` Richard Henderson
2017-10-25 9:34 ` [Qemu-devel] [PULL 15/51] tcg: Push tcg_ctx into tcg_gen_callN Richard Henderson
` (39 subsequent siblings)
53 siblings, 0 replies; 59+ messages in thread
From: Richard Henderson @ 2017-10-25 9:34 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tcg-op.h | 100 +++++++++++++++++++++++++++--------------------------------
tcg/tcg-op.c | 47 ++++++++++++++--------------
2 files changed, 69 insertions(+), 78 deletions(-)
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index 18d01b2f43..de9a61206a 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -28,173 +28,166 @@
/* Basic output routines. Not for general consumption. */
-void tcg_gen_op1(TCGContext *, TCGOpcode, TCGArg);
-void tcg_gen_op2(TCGContext *, TCGOpcode, TCGArg, TCGArg);
-void tcg_gen_op3(TCGContext *, TCGOpcode, TCGArg, TCGArg, TCGArg);
-void tcg_gen_op4(TCGContext *, TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg);
-void tcg_gen_op5(TCGContext *, TCGOpcode, TCGArg, TCGArg, TCGArg,
- TCGArg, TCGArg);
-void tcg_gen_op6(TCGContext *, TCGOpcode, TCGArg, TCGArg, TCGArg,
- TCGArg, TCGArg, TCGArg);
-
+void tcg_gen_op1(TCGOpcode, TCGArg);
+void tcg_gen_op2(TCGOpcode, TCGArg, TCGArg);
+void tcg_gen_op3(TCGOpcode, TCGArg, TCGArg, TCGArg);
+void tcg_gen_op4(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg);
+void tcg_gen_op5(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg);
+void tcg_gen_op6(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg);
static inline void tcg_gen_op1_i32(TCGOpcode opc, TCGv_i32 a1)
{
- tcg_gen_op1(&tcg_ctx, opc, GET_TCGV_I32(a1));
+ tcg_gen_op1(opc, GET_TCGV_I32(a1));
}
static inline void tcg_gen_op1_i64(TCGOpcode opc, TCGv_i64 a1)
{
- tcg_gen_op1(&tcg_ctx, opc, GET_TCGV_I64(a1));
+ tcg_gen_op1(opc, GET_TCGV_I64(a1));
}
static inline void tcg_gen_op1i(TCGOpcode opc, TCGArg a1)
{
- tcg_gen_op1(&tcg_ctx, opc, a1);
+ tcg_gen_op1(opc, a1);
}
static inline void tcg_gen_op2_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2)
{
- tcg_gen_op2(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2));
+ tcg_gen_op2(opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2));
}
static inline void tcg_gen_op2_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2)
{
- tcg_gen_op2(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2));
+ tcg_gen_op2(opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2));
}
static inline void tcg_gen_op2i_i32(TCGOpcode opc, TCGv_i32 a1, TCGArg a2)
{
- tcg_gen_op2(&tcg_ctx, opc, GET_TCGV_I32(a1), a2);
+ tcg_gen_op2(opc, GET_TCGV_I32(a1), a2);
}
static inline void tcg_gen_op2i_i64(TCGOpcode opc, TCGv_i64 a1, TCGArg a2)
{
- tcg_gen_op2(&tcg_ctx, opc, GET_TCGV_I64(a1), a2);
+ tcg_gen_op2(opc, GET_TCGV_I64(a1), a2);
}
static inline void tcg_gen_op2ii(TCGOpcode opc, TCGArg a1, TCGArg a2)
{
- tcg_gen_op2(&tcg_ctx, opc, a1, a2);
+ tcg_gen_op2(opc, a1, a2);
}
static inline void tcg_gen_op3_i32(TCGOpcode opc, TCGv_i32 a1,
TCGv_i32 a2, TCGv_i32 a3)
{
- tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I32(a1),
- GET_TCGV_I32(a2), GET_TCGV_I32(a3));
+ tcg_gen_op3(opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), GET_TCGV_I32(a3));
}
static inline void tcg_gen_op3_i64(TCGOpcode opc, TCGv_i64 a1,
TCGv_i64 a2, TCGv_i64 a3)
{
- tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I64(a1),
- GET_TCGV_I64(a2), GET_TCGV_I64(a3));
+ tcg_gen_op3(opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), GET_TCGV_I64(a3));
}
static inline void tcg_gen_op3i_i32(TCGOpcode opc, TCGv_i32 a1,
TCGv_i32 a2, TCGArg a3)
{
- tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), a3);
+ tcg_gen_op3(opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), a3);
}
static inline void tcg_gen_op3i_i64(TCGOpcode opc, TCGv_i64 a1,
TCGv_i64 a2, TCGArg a3)
{
- tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), a3);
+ tcg_gen_op3(opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), a3);
}
static inline void tcg_gen_ldst_op_i32(TCGOpcode opc, TCGv_i32 val,
TCGv_ptr base, TCGArg offset)
{
- tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I32(val), GET_TCGV_PTR(base), offset);
+ tcg_gen_op3(opc, GET_TCGV_I32(val), GET_TCGV_PTR(base), offset);
}
static inline void tcg_gen_ldst_op_i64(TCGOpcode opc, TCGv_i64 val,
TCGv_ptr base, TCGArg offset)
{
- tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I64(val), GET_TCGV_PTR(base), offset);
+ tcg_gen_op3(opc, GET_TCGV_I64(val), GET_TCGV_PTR(base), offset);
}
static inline void tcg_gen_op4_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
TCGv_i32 a3, TCGv_i32 a4)
{
- tcg_gen_op4(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2),
+ tcg_gen_op4(opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2),
GET_TCGV_I32(a3), GET_TCGV_I32(a4));
}
static inline void tcg_gen_op4_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
TCGv_i64 a3, TCGv_i64 a4)
{
- tcg_gen_op4(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2),
+ tcg_gen_op4(opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2),
GET_TCGV_I64(a3), GET_TCGV_I64(a4));
}
static inline void tcg_gen_op4i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
TCGv_i32 a3, TCGArg a4)
{
- tcg_gen_op4(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2),
- GET_TCGV_I32(a3), a4);
+ tcg_gen_op4(opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), GET_TCGV_I32(a3), a4);
}
static inline void tcg_gen_op4i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
TCGv_i64 a3, TCGArg a4)
{
- tcg_gen_op4(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2),
- GET_TCGV_I64(a3), a4);
+ tcg_gen_op4(opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), GET_TCGV_I64(a3), a4);
}
static inline void tcg_gen_op4ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
TCGArg a3, TCGArg a4)
{
- tcg_gen_op4(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), a3, a4);
+ tcg_gen_op4(opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), a3, a4);
}
static inline void tcg_gen_op4ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
TCGArg a3, TCGArg a4)
{
- tcg_gen_op4(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), a3, a4);
+ tcg_gen_op4(opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), a3, a4);
}
static inline void tcg_gen_op5_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
TCGv_i32 a3, TCGv_i32 a4, TCGv_i32 a5)
{
- tcg_gen_op5(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2),
+ tcg_gen_op5(opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2),
GET_TCGV_I32(a3), GET_TCGV_I32(a4), GET_TCGV_I32(a5));
}
static inline void tcg_gen_op5_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
TCGv_i64 a3, TCGv_i64 a4, TCGv_i64 a5)
{
- tcg_gen_op5(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2),
+ tcg_gen_op5(opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2),
GET_TCGV_I64(a3), GET_TCGV_I64(a4), GET_TCGV_I64(a5));
}
static inline void tcg_gen_op5i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
TCGv_i32 a3, TCGv_i32 a4, TCGArg a5)
{
- tcg_gen_op5(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2),
+ tcg_gen_op5(opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2),
GET_TCGV_I32(a3), GET_TCGV_I32(a4), a5);
}
static inline void tcg_gen_op5i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
TCGv_i64 a3, TCGv_i64 a4, TCGArg a5)
{
- tcg_gen_op5(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2),
+ tcg_gen_op5(opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2),
GET_TCGV_I64(a3), GET_TCGV_I64(a4), a5);
}
static inline void tcg_gen_op5ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
TCGv_i32 a3, TCGArg a4, TCGArg a5)
{
- tcg_gen_op5(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2),
+ tcg_gen_op5(opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2),
GET_TCGV_I32(a3), a4, a5);
}
static inline void tcg_gen_op5ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
TCGv_i64 a3, TCGArg a4, TCGArg a5)
{
- tcg_gen_op5(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2),
+ tcg_gen_op5(opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2),
GET_TCGV_I64(a3), a4, a5);
}
@@ -202,7 +195,7 @@ static inline void tcg_gen_op6_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
TCGv_i32 a3, TCGv_i32 a4,
TCGv_i32 a5, TCGv_i32 a6)
{
- tcg_gen_op6(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2),
+ tcg_gen_op6(opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2),
GET_TCGV_I32(a3), GET_TCGV_I32(a4), GET_TCGV_I32(a5),
GET_TCGV_I32(a6));
}
@@ -211,7 +204,7 @@ static inline void tcg_gen_op6_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
TCGv_i64 a3, TCGv_i64 a4,
TCGv_i64 a5, TCGv_i64 a6)
{
- tcg_gen_op6(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2),
+ tcg_gen_op6(opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2),
GET_TCGV_I64(a3), GET_TCGV_I64(a4), GET_TCGV_I64(a5),
GET_TCGV_I64(a6));
}
@@ -220,7 +213,7 @@ static inline void tcg_gen_op6i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
TCGv_i32 a3, TCGv_i32 a4,
TCGv_i32 a5, TCGArg a6)
{
- tcg_gen_op6(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2),
+ tcg_gen_op6(opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2),
GET_TCGV_I32(a3), GET_TCGV_I32(a4), GET_TCGV_I32(a5), a6);
}
@@ -228,7 +221,7 @@ static inline void tcg_gen_op6i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
TCGv_i64 a3, TCGv_i64 a4,
TCGv_i64 a5, TCGArg a6)
{
- tcg_gen_op6(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2),
+ tcg_gen_op6(opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2),
GET_TCGV_I64(a3), GET_TCGV_I64(a4), GET_TCGV_I64(a5), a6);
}
@@ -236,7 +229,7 @@ static inline void tcg_gen_op6ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
TCGv_i32 a3, TCGv_i32 a4,
TCGArg a5, TCGArg a6)
{
- tcg_gen_op6(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2),
+ tcg_gen_op6(opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2),
GET_TCGV_I32(a3), GET_TCGV_I32(a4), a5, a6);
}
@@ -244,7 +237,7 @@ static inline void tcg_gen_op6ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
TCGv_i64 a3, TCGv_i64 a4,
TCGArg a5, TCGArg a6)
{
- tcg_gen_op6(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2),
+ tcg_gen_op6(opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2),
GET_TCGV_I64(a3), GET_TCGV_I64(a4), a5, a6);
}
@@ -253,12 +246,12 @@ static inline void tcg_gen_op6ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
static inline void gen_set_label(TCGLabel *l)
{
- tcg_gen_op1(&tcg_ctx, INDEX_op_set_label, label_arg(l));
+ tcg_gen_op1(INDEX_op_set_label, label_arg(l));
}
static inline void tcg_gen_br(TCGLabel *l)
{
- tcg_gen_op1(&tcg_ctx, INDEX_op_br, label_arg(l));
+ tcg_gen_op1(INDEX_op_br, label_arg(l));
}
void tcg_gen_mb(TCGBar);
@@ -732,25 +725,24 @@ static inline void tcg_gen_concat32_i64(TCGv_i64 ret, TCGv_i64 lo, TCGv_i64 hi)
# if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
static inline void tcg_gen_insn_start(target_ulong pc)
{
- tcg_gen_op1(&tcg_ctx, INDEX_op_insn_start, pc);
+ tcg_gen_op1(INDEX_op_insn_start, pc);
}
# else
static inline void tcg_gen_insn_start(target_ulong pc)
{
- tcg_gen_op2(&tcg_ctx, INDEX_op_insn_start,
- (uint32_t)pc, (uint32_t)(pc >> 32));
+ tcg_gen_op2(INDEX_op_insn_start, (uint32_t)pc, (uint32_t)(pc >> 32));
}
# endif
#elif TARGET_INSN_START_WORDS == 2
# if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1)
{
- tcg_gen_op2(&tcg_ctx, INDEX_op_insn_start, pc, a1);
+ tcg_gen_op2(INDEX_op_insn_start, pc, a1);
}
# else
static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1)
{
- tcg_gen_op4(&tcg_ctx, INDEX_op_insn_start,
+ tcg_gen_op4(INDEX_op_insn_start,
(uint32_t)pc, (uint32_t)(pc >> 32),
(uint32_t)a1, (uint32_t)(a1 >> 32));
}
@@ -760,13 +752,13 @@ static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1)
static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1,
target_ulong a2)
{
- tcg_gen_op3(&tcg_ctx, INDEX_op_insn_start, pc, a1, a2);
+ tcg_gen_op3(INDEX_op_insn_start, pc, a1, a2);
}
# else
static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1,
target_ulong a2)
{
- tcg_gen_op6(&tcg_ctx, INDEX_op_insn_start,
+ tcg_gen_op6(INDEX_op_insn_start,
(uint32_t)pc, (uint32_t)(pc >> 32),
(uint32_t)a1, (uint32_t)(a1 >> 32),
(uint32_t)a2, (uint32_t)(a2 >> 32));
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index bd84a782e3..bff4b95097 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -46,8 +46,9 @@ extern TCGv_i32 TCGV_HIGH_link_error(TCGv_i64);
Up to and including filling in the forward link immediately. We'll do
proper termination of the end of the list after we finish translation. */
-static inline TCGOp *tcg_emit_op(TCGContext *ctx, TCGOpcode opc)
+static inline TCGOp *tcg_emit_op(TCGOpcode opc)
{
+ TCGContext *ctx = &tcg_ctx;
int oi = ctx->gen_next_op_idx;
int ni = oi + 1;
int pi = oi - 1;
@@ -65,42 +66,40 @@ static inline TCGOp *tcg_emit_op(TCGContext *ctx, TCGOpcode opc)
return op;
}
-void tcg_gen_op1(TCGContext *ctx, TCGOpcode opc, TCGArg a1)
+void tcg_gen_op1(TCGOpcode opc, TCGArg a1)
{
- TCGOp *op = tcg_emit_op(ctx, opc);
+ TCGOp *op = tcg_emit_op(opc);
op->args[0] = a1;
}
-void tcg_gen_op2(TCGContext *ctx, TCGOpcode opc, TCGArg a1, TCGArg a2)
+void tcg_gen_op2(TCGOpcode opc, TCGArg a1, TCGArg a2)
{
- TCGOp *op = tcg_emit_op(ctx, opc);
+ TCGOp *op = tcg_emit_op(opc);
op->args[0] = a1;
op->args[1] = a2;
}
-void tcg_gen_op3(TCGContext *ctx, TCGOpcode opc, TCGArg a1,
- TCGArg a2, TCGArg a3)
+void tcg_gen_op3(TCGOpcode opc, TCGArg a1, TCGArg a2, TCGArg a3)
{
- TCGOp *op = tcg_emit_op(ctx, opc);
+ TCGOp *op = tcg_emit_op(opc);
op->args[0] = a1;
op->args[1] = a2;
op->args[2] = a3;
}
-void tcg_gen_op4(TCGContext *ctx, TCGOpcode opc, TCGArg a1,
- TCGArg a2, TCGArg a3, TCGArg a4)
+void tcg_gen_op4(TCGOpcode opc, TCGArg a1, TCGArg a2, TCGArg a3, TCGArg a4)
{
- TCGOp *op = tcg_emit_op(ctx, opc);
+ TCGOp *op = tcg_emit_op(opc);
op->args[0] = a1;
op->args[1] = a2;
op->args[2] = a3;
op->args[3] = a4;
}
-void tcg_gen_op5(TCGContext *ctx, TCGOpcode opc, TCGArg a1,
- TCGArg a2, TCGArg a3, TCGArg a4, TCGArg a5)
+void tcg_gen_op5(TCGOpcode opc, TCGArg a1, TCGArg a2, TCGArg a3,
+ TCGArg a4, TCGArg a5)
{
- TCGOp *op = tcg_emit_op(ctx, opc);
+ TCGOp *op = tcg_emit_op(opc);
op->args[0] = a1;
op->args[1] = a2;
op->args[2] = a3;
@@ -108,10 +107,10 @@ void tcg_gen_op5(TCGContext *ctx, TCGOpcode opc, TCGArg a1,
op->args[4] = a5;
}
-void tcg_gen_op6(TCGContext *ctx, TCGOpcode opc, TCGArg a1, TCGArg a2,
- TCGArg a3, TCGArg a4, TCGArg a5, TCGArg a6)
+void tcg_gen_op6(TCGOpcode opc, TCGArg a1, TCGArg a2, TCGArg a3,
+ TCGArg a4, TCGArg a5, TCGArg a6)
{
- TCGOp *op = tcg_emit_op(ctx, opc);
+ TCGOp *op = tcg_emit_op(opc);
op->args[0] = a1;
op->args[1] = a2;
op->args[2] = a3;
@@ -123,7 +122,7 @@ void tcg_gen_op6(TCGContext *ctx, TCGOpcode opc, TCGArg a1, TCGArg a2,
void tcg_gen_mb(TCGBar mb_type)
{
if (parallel_cpus) {
- tcg_gen_op1(&tcg_ctx, INDEX_op_mb, mb_type);
+ tcg_gen_op1(INDEX_op_mb, mb_type);
}
}
@@ -2458,7 +2457,7 @@ void tcg_gen_extrl_i64_i32(TCGv_i32 ret, TCGv_i64 arg)
if (TCG_TARGET_REG_BITS == 32) {
tcg_gen_mov_i32(ret, TCGV_LOW(arg));
} else if (TCG_TARGET_HAS_extrl_i64_i32) {
- tcg_gen_op2(&tcg_ctx, INDEX_op_extrl_i64_i32,
+ tcg_gen_op2(INDEX_op_extrl_i64_i32,
GET_TCGV_I32(ret), GET_TCGV_I64(arg));
} else {
tcg_gen_mov_i32(ret, MAKE_TCGV_I32(GET_TCGV_I64(arg)));
@@ -2470,7 +2469,7 @@ void tcg_gen_extrh_i64_i32(TCGv_i32 ret, TCGv_i64 arg)
if (TCG_TARGET_REG_BITS == 32) {
tcg_gen_mov_i32(ret, TCGV_HIGH(arg));
} else if (TCG_TARGET_HAS_extrh_i64_i32) {
- tcg_gen_op2(&tcg_ctx, INDEX_op_extrh_i64_i32,
+ tcg_gen_op2(INDEX_op_extrh_i64_i32,
GET_TCGV_I32(ret), GET_TCGV_I64(arg));
} else {
TCGv_i64 t = tcg_temp_new_i64();
@@ -2486,7 +2485,7 @@ void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
tcg_gen_mov_i32(TCGV_LOW(ret), arg);
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
} else {
- tcg_gen_op2(&tcg_ctx, INDEX_op_extu_i32_i64,
+ tcg_gen_op2(INDEX_op_extu_i32_i64,
GET_TCGV_I64(ret), GET_TCGV_I32(arg));
}
}
@@ -2497,7 +2496,7 @@ void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
tcg_gen_mov_i32(TCGV_LOW(ret), arg);
tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
} else {
- tcg_gen_op2(&tcg_ctx, INDEX_op_ext_i32_i64,
+ tcg_gen_op2(INDEX_op_ext_i32_i64,
GET_TCGV_I64(ret), GET_TCGV_I32(arg));
}
}
@@ -2609,7 +2608,7 @@ static void gen_ldst_i32(TCGOpcode opc, TCGv_i32 val, TCGv addr,
if (TCG_TARGET_REG_BITS == 32) {
tcg_gen_op4i_i32(opc, val, TCGV_LOW(addr), TCGV_HIGH(addr), oi);
} else {
- tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I32(val), GET_TCGV_I64(addr), oi);
+ tcg_gen_op3(opc, GET_TCGV_I32(val), GET_TCGV_I64(addr), oi);
}
#endif
}
@@ -2622,7 +2621,7 @@ static void gen_ldst_i64(TCGOpcode opc, TCGv_i64 val, TCGv addr,
if (TCG_TARGET_REG_BITS == 32) {
tcg_gen_op4i_i32(opc, TCGV_LOW(val), TCGV_HIGH(val), addr, oi);
} else {
- tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I64(val), GET_TCGV_I32(addr), oi);
+ tcg_gen_op3(opc, GET_TCGV_I64(val), GET_TCGV_I32(addr), oi);
}
#else
if (TCG_TARGET_REG_BITS == 32) {
--
2.13.6
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [Qemu-devel] [PULL 15/51] tcg: Push tcg_ctx into tcg_gen_callN
2017-10-25 9:34 [Qemu-devel] [PULL 00/51] tcg queued patches Richard Henderson
` (13 preceding siblings ...)
2017-10-25 9:34 ` [Qemu-devel] [PULL 14/51] tcg: Push tcg_ctx into generator functions Richard Henderson
@ 2017-10-25 9:34 ` Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 16/51] tcg: Introduce tcgv_{i32, i64, ptr}_{arg, temp} Richard Henderson
` (38 subsequent siblings)
53 siblings, 0 replies; 59+ messages in thread
From: Richard Henderson @ 2017-10-25 9:34 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/helper-gen.h | 12 ++++++------
tcg/tcg.h | 3 +--
tcg/tcg.c | 4 ++--
3 files changed, 9 insertions(+), 10 deletions(-)
diff --git a/include/exec/helper-gen.h b/include/exec/helper-gen.h
index 8239ffc77c..476acd9220 100644
--- a/include/exec/helper-gen.h
+++ b/include/exec/helper-gen.h
@@ -9,7 +9,7 @@
#define DEF_HELPER_FLAGS_0(name, flags, ret) \
static inline void glue(gen_helper_, name)(dh_retvar_decl0(ret)) \
{ \
- tcg_gen_callN(&tcg_ctx, HELPER(name), dh_retvar(ret), 0, NULL); \
+ tcg_gen_callN(HELPER(name), dh_retvar(ret), 0, NULL); \
}
#define DEF_HELPER_FLAGS_1(name, flags, ret, t1) \
@@ -17,7 +17,7 @@ static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \
dh_arg_decl(t1, 1)) \
{ \
TCGArg args[1] = { dh_arg(t1, 1) }; \
- tcg_gen_callN(&tcg_ctx, HELPER(name), dh_retvar(ret), 1, args); \
+ tcg_gen_callN(HELPER(name), dh_retvar(ret), 1, args); \
}
#define DEF_HELPER_FLAGS_2(name, flags, ret, t1, t2) \
@@ -25,7 +25,7 @@ static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \
dh_arg_decl(t1, 1), dh_arg_decl(t2, 2)) \
{ \
TCGArg args[2] = { dh_arg(t1, 1), dh_arg(t2, 2) }; \
- tcg_gen_callN(&tcg_ctx, HELPER(name), dh_retvar(ret), 2, args); \
+ tcg_gen_callN(HELPER(name), dh_retvar(ret), 2, args); \
}
#define DEF_HELPER_FLAGS_3(name, flags, ret, t1, t2, t3) \
@@ -33,7 +33,7 @@ static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \
dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), dh_arg_decl(t3, 3)) \
{ \
TCGArg args[3] = { dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3) }; \
- tcg_gen_callN(&tcg_ctx, HELPER(name), dh_retvar(ret), 3, args); \
+ tcg_gen_callN(HELPER(name), dh_retvar(ret), 3, args); \
}
#define DEF_HELPER_FLAGS_4(name, flags, ret, t1, t2, t3, t4) \
@@ -43,7 +43,7 @@ static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \
{ \
TCGArg args[4] = { dh_arg(t1, 1), dh_arg(t2, 2), \
dh_arg(t3, 3), dh_arg(t4, 4) }; \
- tcg_gen_callN(&tcg_ctx, HELPER(name), dh_retvar(ret), 4, args); \
+ tcg_gen_callN(HELPER(name), dh_retvar(ret), 4, args); \
}
#define DEF_HELPER_FLAGS_5(name, flags, ret, t1, t2, t3, t4, t5) \
@@ -53,7 +53,7 @@ static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \
{ \
TCGArg args[5] = { dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3), \
dh_arg(t4, 4), dh_arg(t5, 5) }; \
- tcg_gen_callN(&tcg_ctx, HELPER(name), dh_retvar(ret), 5, args); \
+ tcg_gen_callN(HELPER(name), dh_retvar(ret), 5, args); \
}
#include "helper.h"
diff --git a/tcg/tcg.h b/tcg/tcg.h
index 563e7d36aa..0d61932301 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -951,8 +951,7 @@ do {\
bool tcg_op_supported(TCGOpcode op);
-void tcg_gen_callN(TCGContext *s, void *func,
- TCGArg ret, int nargs, TCGArg *args);
+void tcg_gen_callN(void *func, TCGArg ret, int nargs, TCGArg *args);
void tcg_op_remove(TCGContext *s, TCGOp *op);
TCGOp *tcg_op_insert_before(TCGContext *s, TCGOp *op, TCGOpcode opc, int narg);
diff --git a/tcg/tcg.c b/tcg/tcg.c
index c10e73babe..dac3e06a5b 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -974,9 +974,9 @@ bool tcg_op_supported(TCGOpcode op)
/* Note: we convert the 64 bit args to 32 bit and do some alignment
and endian swap. Maybe it would be better to do the alignment
and endian swap in tcg_reg_alloc_call(). */
-void tcg_gen_callN(TCGContext *s, void *func, TCGArg ret,
- int nargs, TCGArg *args)
+void tcg_gen_callN(void *func, TCGArg ret, int nargs, TCGArg *args)
{
+ TCGContext *s = &tcg_ctx;
int i, real_args, nb_rets, pi;
unsigned sizemask, flags;
TCGHelperInfo *info;
--
2.13.6
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [Qemu-devel] [PULL 16/51] tcg: Introduce tcgv_{i32, i64, ptr}_{arg, temp}
2017-10-25 9:34 [Qemu-devel] [PULL 00/51] tcg queued patches Richard Henderson
` (14 preceding siblings ...)
2017-10-25 9:34 ` [Qemu-devel] [PULL 15/51] tcg: Push tcg_ctx into tcg_gen_callN Richard Henderson
@ 2017-10-25 9:35 ` Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 17/51] tcg: Introduce temp_tcgv_{i32,i64,ptr} Richard Henderson
` (37 subsequent siblings)
53 siblings, 0 replies; 59+ messages in thread
From: Richard Henderson @ 2017-10-25 9:35 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
Transform TCGv_* to an "argument" or a temporary.
For now, an argument is simply the temporary index.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/helper-gen.h | 10 ++---
include/exec/helper-head.h | 12 +++---
tcg/tcg-op.h | 94 +++++++++++++++++++++++-----------------------
tcg/tcg.h | 32 +++++++++++++++-
tcg/tcg-op.c | 14 +++----
tcg/tcg.c | 50 ++++++++++++------------
6 files changed, 122 insertions(+), 90 deletions(-)
diff --git a/include/exec/helper-gen.h b/include/exec/helper-gen.h
index 476acd9220..15204ab961 100644
--- a/include/exec/helper-gen.h
+++ b/include/exec/helper-gen.h
@@ -16,7 +16,7 @@ static inline void glue(gen_helper_, name)(dh_retvar_decl0(ret)) \
static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \
dh_arg_decl(t1, 1)) \
{ \
- TCGArg args[1] = { dh_arg(t1, 1) }; \
+ TCGTemp *args[1] = { dh_arg(t1, 1) }; \
tcg_gen_callN(HELPER(name), dh_retvar(ret), 1, args); \
}
@@ -24,7 +24,7 @@ static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \
static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \
dh_arg_decl(t1, 1), dh_arg_decl(t2, 2)) \
{ \
- TCGArg args[2] = { dh_arg(t1, 1), dh_arg(t2, 2) }; \
+ TCGTemp *args[2] = { dh_arg(t1, 1), dh_arg(t2, 2) }; \
tcg_gen_callN(HELPER(name), dh_retvar(ret), 2, args); \
}
@@ -32,7 +32,7 @@ static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \
static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \
dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), dh_arg_decl(t3, 3)) \
{ \
- TCGArg args[3] = { dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3) }; \
+ TCGTemp *args[3] = { dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3) }; \
tcg_gen_callN(HELPER(name), dh_retvar(ret), 3, args); \
}
@@ -41,7 +41,7 @@ static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \
dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), \
dh_arg_decl(t3, 3), dh_arg_decl(t4, 4)) \
{ \
- TCGArg args[4] = { dh_arg(t1, 1), dh_arg(t2, 2), \
+ TCGTemp *args[4] = { dh_arg(t1, 1), dh_arg(t2, 2), \
dh_arg(t3, 3), dh_arg(t4, 4) }; \
tcg_gen_callN(HELPER(name), dh_retvar(ret), 4, args); \
}
@@ -51,7 +51,7 @@ static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \
dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), dh_arg_decl(t3, 3), \
dh_arg_decl(t4, 4), dh_arg_decl(t5, 5)) \
{ \
- TCGArg args[5] = { dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3), \
+ TCGTemp *args[5] = { dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3), \
dh_arg(t4, 4), dh_arg(t5, 5) }; \
tcg_gen_callN(HELPER(name), dh_retvar(ret), 5, args); \
}
diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h
index 1cfc43b9ff..13286018fd 100644
--- a/include/exec/helper-head.h
+++ b/include/exec/helper-head.h
@@ -78,11 +78,11 @@
#define dh_retvar_decl_ptr TCGv_ptr retval,
#define dh_retvar_decl(t) glue(dh_retvar_decl_, dh_alias(t))
-#define dh_retvar_void TCG_CALL_DUMMY_ARG
-#define dh_retvar_noreturn TCG_CALL_DUMMY_ARG
-#define dh_retvar_i32 GET_TCGV_i32(retval)
-#define dh_retvar_i64 GET_TCGV_i64(retval)
-#define dh_retvar_ptr GET_TCGV_ptr(retval)
+#define dh_retvar_void NULL
+#define dh_retvar_noreturn NULL
+#define dh_retvar_i32 tcgv_i32_temp(retval)
+#define dh_retvar_i64 tcgv_i64_temp(retval)
+#define dh_retvar_ptr tcgv_ptr_temp(retval)
#define dh_retvar(t) glue(dh_retvar_, dh_alias(t))
#define dh_is_64bit_void 0
@@ -113,7 +113,7 @@
((dh_is_64bit(t) << (n*2)) | (dh_is_signed(t) << (n*2+1)))
#define dh_arg(t, n) \
- glue(GET_TCGV_, dh_alias(t))(glue(arg, n))
+ glue(glue(tcgv_, dh_alias(t)), _temp)(glue(arg, n))
#define dh_arg_decl(t, n) glue(TCGv_, dh_alias(t)) glue(arg, n)
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index de9a61206a..ab2f3c6cee 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -37,12 +37,12 @@ void tcg_gen_op6(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg);
static inline void tcg_gen_op1_i32(TCGOpcode opc, TCGv_i32 a1)
{
- tcg_gen_op1(opc, GET_TCGV_I32(a1));
+ tcg_gen_op1(opc, tcgv_i32_arg(a1));
}
static inline void tcg_gen_op1_i64(TCGOpcode opc, TCGv_i64 a1)
{
- tcg_gen_op1(opc, GET_TCGV_I64(a1));
+ tcg_gen_op1(opc, tcgv_i64_arg(a1));
}
static inline void tcg_gen_op1i(TCGOpcode opc, TCGArg a1)
@@ -52,22 +52,22 @@ static inline void tcg_gen_op1i(TCGOpcode opc, TCGArg a1)
static inline void tcg_gen_op2_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2)
{
- tcg_gen_op2(opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2));
+ tcg_gen_op2(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2));
}
static inline void tcg_gen_op2_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2)
{
- tcg_gen_op2(opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2));
+ tcg_gen_op2(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2));
}
static inline void tcg_gen_op2i_i32(TCGOpcode opc, TCGv_i32 a1, TCGArg a2)
{
- tcg_gen_op2(opc, GET_TCGV_I32(a1), a2);
+ tcg_gen_op2(opc, tcgv_i32_arg(a1), a2);
}
static inline void tcg_gen_op2i_i64(TCGOpcode opc, TCGv_i64 a1, TCGArg a2)
{
- tcg_gen_op2(opc, GET_TCGV_I64(a1), a2);
+ tcg_gen_op2(opc, tcgv_i64_arg(a1), a2);
}
static inline void tcg_gen_op2ii(TCGOpcode opc, TCGArg a1, TCGArg a2)
@@ -78,167 +78,169 @@ static inline void tcg_gen_op2ii(TCGOpcode opc, TCGArg a1, TCGArg a2)
static inline void tcg_gen_op3_i32(TCGOpcode opc, TCGv_i32 a1,
TCGv_i32 a2, TCGv_i32 a3)
{
- tcg_gen_op3(opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), GET_TCGV_I32(a3));
+ tcg_gen_op3(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), tcgv_i32_arg(a3));
}
static inline void tcg_gen_op3_i64(TCGOpcode opc, TCGv_i64 a1,
TCGv_i64 a2, TCGv_i64 a3)
{
- tcg_gen_op3(opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), GET_TCGV_I64(a3));
+ tcg_gen_op3(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), tcgv_i64_arg(a3));
}
static inline void tcg_gen_op3i_i32(TCGOpcode opc, TCGv_i32 a1,
TCGv_i32 a2, TCGArg a3)
{
- tcg_gen_op3(opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), a3);
+ tcg_gen_op3(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), a3);
}
static inline void tcg_gen_op3i_i64(TCGOpcode opc, TCGv_i64 a1,
TCGv_i64 a2, TCGArg a3)
{
- tcg_gen_op3(opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), a3);
+ tcg_gen_op3(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), a3);
}
static inline void tcg_gen_ldst_op_i32(TCGOpcode opc, TCGv_i32 val,
TCGv_ptr base, TCGArg offset)
{
- tcg_gen_op3(opc, GET_TCGV_I32(val), GET_TCGV_PTR(base), offset);
+ tcg_gen_op3(opc, tcgv_i32_arg(val), tcgv_ptr_arg(base), offset);
}
static inline void tcg_gen_ldst_op_i64(TCGOpcode opc, TCGv_i64 val,
TCGv_ptr base, TCGArg offset)
{
- tcg_gen_op3(opc, GET_TCGV_I64(val), GET_TCGV_PTR(base), offset);
+ tcg_gen_op3(opc, tcgv_i64_arg(val), tcgv_ptr_arg(base), offset);
}
static inline void tcg_gen_op4_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
TCGv_i32 a3, TCGv_i32 a4)
{
- tcg_gen_op4(opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2),
- GET_TCGV_I32(a3), GET_TCGV_I32(a4));
+ tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
+ tcgv_i32_arg(a3), tcgv_i32_arg(a4));
}
static inline void tcg_gen_op4_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
TCGv_i64 a3, TCGv_i64 a4)
{
- tcg_gen_op4(opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2),
- GET_TCGV_I64(a3), GET_TCGV_I64(a4));
+ tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
+ tcgv_i64_arg(a3), tcgv_i64_arg(a4));
}
static inline void tcg_gen_op4i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
TCGv_i32 a3, TCGArg a4)
{
- tcg_gen_op4(opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), GET_TCGV_I32(a3), a4);
+ tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
+ tcgv_i32_arg(a3), a4);
}
static inline void tcg_gen_op4i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
TCGv_i64 a3, TCGArg a4)
{
- tcg_gen_op4(opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), GET_TCGV_I64(a3), a4);
+ tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
+ tcgv_i64_arg(a3), a4);
}
static inline void tcg_gen_op4ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
TCGArg a3, TCGArg a4)
{
- tcg_gen_op4(opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), a3, a4);
+ tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), a3, a4);
}
static inline void tcg_gen_op4ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
TCGArg a3, TCGArg a4)
{
- tcg_gen_op4(opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), a3, a4);
+ tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), a3, a4);
}
static inline void tcg_gen_op5_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
TCGv_i32 a3, TCGv_i32 a4, TCGv_i32 a5)
{
- tcg_gen_op5(opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2),
- GET_TCGV_I32(a3), GET_TCGV_I32(a4), GET_TCGV_I32(a5));
+ tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
+ tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5));
}
static inline void tcg_gen_op5_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
TCGv_i64 a3, TCGv_i64 a4, TCGv_i64 a5)
{
- tcg_gen_op5(opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2),
- GET_TCGV_I64(a3), GET_TCGV_I64(a4), GET_TCGV_I64(a5));
+ tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
+ tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5));
}
static inline void tcg_gen_op5i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
TCGv_i32 a3, TCGv_i32 a4, TCGArg a5)
{
- tcg_gen_op5(opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2),
- GET_TCGV_I32(a3), GET_TCGV_I32(a4), a5);
+ tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
+ tcgv_i32_arg(a3), tcgv_i32_arg(a4), a5);
}
static inline void tcg_gen_op5i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
TCGv_i64 a3, TCGv_i64 a4, TCGArg a5)
{
- tcg_gen_op5(opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2),
- GET_TCGV_I64(a3), GET_TCGV_I64(a4), a5);
+ tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
+ tcgv_i64_arg(a3), tcgv_i64_arg(a4), a5);
}
static inline void tcg_gen_op5ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
TCGv_i32 a3, TCGArg a4, TCGArg a5)
{
- tcg_gen_op5(opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2),
- GET_TCGV_I32(a3), a4, a5);
+ tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
+ tcgv_i32_arg(a3), a4, a5);
}
static inline void tcg_gen_op5ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
TCGv_i64 a3, TCGArg a4, TCGArg a5)
{
- tcg_gen_op5(opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2),
- GET_TCGV_I64(a3), a4, a5);
+ tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
+ tcgv_i64_arg(a3), a4, a5);
}
static inline void tcg_gen_op6_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
TCGv_i32 a3, TCGv_i32 a4,
TCGv_i32 a5, TCGv_i32 a6)
{
- tcg_gen_op6(opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2),
- GET_TCGV_I32(a3), GET_TCGV_I32(a4), GET_TCGV_I32(a5),
- GET_TCGV_I32(a6));
+ tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
+ tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5),
+ tcgv_i32_arg(a6));
}
static inline void tcg_gen_op6_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
TCGv_i64 a3, TCGv_i64 a4,
TCGv_i64 a5, TCGv_i64 a6)
{
- tcg_gen_op6(opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2),
- GET_TCGV_I64(a3), GET_TCGV_I64(a4), GET_TCGV_I64(a5),
- GET_TCGV_I64(a6));
+ tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
+ tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5),
+ tcgv_i64_arg(a6));
}
static inline void tcg_gen_op6i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
TCGv_i32 a3, TCGv_i32 a4,
TCGv_i32 a5, TCGArg a6)
{
- tcg_gen_op6(opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2),
- GET_TCGV_I32(a3), GET_TCGV_I32(a4), GET_TCGV_I32(a5), a6);
+ tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
+ tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5), a6);
}
static inline void tcg_gen_op6i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
TCGv_i64 a3, TCGv_i64 a4,
TCGv_i64 a5, TCGArg a6)
{
- tcg_gen_op6(opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2),
- GET_TCGV_I64(a3), GET_TCGV_I64(a4), GET_TCGV_I64(a5), a6);
+ tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
+ tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5), a6);
}
static inline void tcg_gen_op6ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
TCGv_i32 a3, TCGv_i32 a4,
TCGArg a5, TCGArg a6)
{
- tcg_gen_op6(opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2),
- GET_TCGV_I32(a3), GET_TCGV_I32(a4), a5, a6);
+ tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
+ tcgv_i32_arg(a3), tcgv_i32_arg(a4), a5, a6);
}
static inline void tcg_gen_op6ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
TCGv_i64 a3, TCGv_i64 a4,
TCGArg a5, TCGArg a6)
{
- tcg_gen_op6(opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2),
- GET_TCGV_I64(a3), GET_TCGV_I64(a4), a5, a6);
+ tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
+ tcgv_i64_arg(a3), tcgv_i64_arg(a4), a5, a6);
}
diff --git a/tcg/tcg.h b/tcg/tcg.h
index 0d61932301..fb8ce01664 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -756,6 +756,36 @@ static inline size_t arg_index(TCGArg a)
return a;
}
+static inline TCGArg tcgv_i32_arg(TCGv_i32 t)
+{
+ return (intptr_t)t;
+}
+
+static inline TCGArg tcgv_i64_arg(TCGv_i64 t)
+{
+ return (intptr_t)t;
+}
+
+static inline TCGArg tcgv_ptr_arg(TCGv_ptr t)
+{
+ return (intptr_t)t;
+}
+
+static inline TCGTemp *tcgv_i32_temp(TCGv_i32 t)
+{
+ return arg_temp(tcgv_i32_arg(t));
+}
+
+static inline TCGTemp *tcgv_i64_temp(TCGv_i64 t)
+{
+ return arg_temp(tcgv_i64_arg(t));
+}
+
+static inline TCGTemp *tcgv_ptr_temp(TCGv_ptr t)
+{
+ return arg_temp(tcgv_ptr_arg(t));
+}
+
static inline void tcg_set_insn_param(int op_idx, int arg, TCGArg v)
{
tcg_ctx.gen_op_buf[op_idx].args[arg] = v;
@@ -951,7 +981,7 @@ do {\
bool tcg_op_supported(TCGOpcode op);
-void tcg_gen_callN(void *func, TCGArg ret, int nargs, TCGArg *args);
+void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args);
void tcg_op_remove(TCGContext *s, TCGOp *op);
TCGOp *tcg_op_insert_before(TCGContext *s, TCGOp *op, TCGOpcode opc, int narg);
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index bff4b95097..be4b623e82 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -2458,7 +2458,7 @@ void tcg_gen_extrl_i64_i32(TCGv_i32 ret, TCGv_i64 arg)
tcg_gen_mov_i32(ret, TCGV_LOW(arg));
} else if (TCG_TARGET_HAS_extrl_i64_i32) {
tcg_gen_op2(INDEX_op_extrl_i64_i32,
- GET_TCGV_I32(ret), GET_TCGV_I64(arg));
+ tcgv_i32_arg(ret), tcgv_i64_arg(arg));
} else {
tcg_gen_mov_i32(ret, MAKE_TCGV_I32(GET_TCGV_I64(arg)));
}
@@ -2470,7 +2470,7 @@ void tcg_gen_extrh_i64_i32(TCGv_i32 ret, TCGv_i64 arg)
tcg_gen_mov_i32(ret, TCGV_HIGH(arg));
} else if (TCG_TARGET_HAS_extrh_i64_i32) {
tcg_gen_op2(INDEX_op_extrh_i64_i32,
- GET_TCGV_I32(ret), GET_TCGV_I64(arg));
+ tcgv_i32_arg(ret), tcgv_i64_arg(arg));
} else {
TCGv_i64 t = tcg_temp_new_i64();
tcg_gen_shri_i64(t, arg, 32);
@@ -2486,7 +2486,7 @@ void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
} else {
tcg_gen_op2(INDEX_op_extu_i32_i64,
- GET_TCGV_I64(ret), GET_TCGV_I32(arg));
+ tcgv_i64_arg(ret), tcgv_i32_arg(arg));
}
}
@@ -2497,7 +2497,7 @@ void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
} else {
tcg_gen_op2(INDEX_op_ext_i32_i64,
- GET_TCGV_I64(ret), GET_TCGV_I32(arg));
+ tcgv_i64_arg(ret), tcgv_i32_arg(arg));
}
}
@@ -2563,7 +2563,7 @@ void tcg_gen_lookup_and_goto_ptr(void)
if (TCG_TARGET_HAS_goto_ptr && !qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)) {
TCGv_ptr ptr = tcg_temp_new_ptr();
gen_helper_lookup_tb_ptr(ptr, tcg_ctx.tcg_env);
- tcg_gen_op1i(INDEX_op_goto_ptr, GET_TCGV_PTR(ptr));
+ tcg_gen_op1i(INDEX_op_goto_ptr, tcgv_ptr_arg(ptr));
tcg_temp_free_ptr(ptr);
} else {
tcg_gen_exit_tb(0);
@@ -2608,7 +2608,7 @@ static void gen_ldst_i32(TCGOpcode opc, TCGv_i32 val, TCGv addr,
if (TCG_TARGET_REG_BITS == 32) {
tcg_gen_op4i_i32(opc, val, TCGV_LOW(addr), TCGV_HIGH(addr), oi);
} else {
- tcg_gen_op3(opc, GET_TCGV_I32(val), GET_TCGV_I64(addr), oi);
+ tcg_gen_op3(opc, tcgv_i32_arg(val), tcgv_i64_arg(addr), oi);
}
#endif
}
@@ -2621,7 +2621,7 @@ static void gen_ldst_i64(TCGOpcode opc, TCGv_i64 val, TCGv addr,
if (TCG_TARGET_REG_BITS == 32) {
tcg_gen_op4i_i32(opc, TCGV_LOW(val), TCGV_HIGH(val), addr, oi);
} else {
- tcg_gen_op3(opc, GET_TCGV_I64(val), GET_TCGV_I32(addr), oi);
+ tcg_gen_op3(opc, tcgv_i64_arg(val), tcgv_i32_arg(addr), oi);
}
#else
if (TCG_TARGET_REG_BITS == 32) {
diff --git a/tcg/tcg.c b/tcg/tcg.c
index dac3e06a5b..cb985aabdc 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -974,7 +974,7 @@ bool tcg_op_supported(TCGOpcode op)
/* Note: we convert the 64 bit args to 32 bit and do some alignment
and endian swap. Maybe it would be better to do the alignment
and endian swap in tcg_reg_alloc_call(). */
-void tcg_gen_callN(void *func, TCGArg ret, int nargs, TCGArg *args)
+void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args)
{
TCGContext *s = &tcg_ctx;
int i, real_args, nb_rets, pi;
@@ -993,7 +993,7 @@ void tcg_gen_callN(void *func, TCGArg ret, int nargs, TCGArg *args)
int orig_sizemask = sizemask;
int orig_nargs = nargs;
TCGv_i64 retl, reth;
- TCGArg split_args[MAX_OPC_PARAM];
+ TCGTemp *split_args[MAX_OPC_PARAM];
TCGV_UNUSED_I64(retl);
TCGV_UNUSED_I64(reth);
@@ -1001,12 +1001,12 @@ void tcg_gen_callN(void *func, TCGArg ret, int nargs, TCGArg *args)
for (i = real_args = 0; i < nargs; ++i) {
int is_64bit = sizemask & (1 << (i+1)*2);
if (is_64bit) {
- TCGv_i64 orig = MAKE_TCGV_I64(args[i]);
+ TCGv_i64 orig = MAKE_TCGV_I64(temp_idx(args[i]));
TCGv_i32 h = tcg_temp_new_i32();
TCGv_i32 l = tcg_temp_new_i32();
tcg_gen_extr_i64_i32(l, h, orig);
- split_args[real_args++] = GET_TCGV_I32(h);
- split_args[real_args++] = GET_TCGV_I32(l);
+ split_args[real_args++] = tcgv_i32_temp(h);
+ split_args[real_args++] = tcgv_i32_temp(l);
} else {
split_args[real_args++] = args[i];
}
@@ -1021,13 +1021,13 @@ void tcg_gen_callN(void *func, TCGArg ret, int nargs, TCGArg *args)
int is_signed = sizemask & (2 << (i+1)*2);
if (!is_64bit) {
TCGv_i64 temp = tcg_temp_new_i64();
- TCGv_i64 orig = MAKE_TCGV_I64(args[i]);
+ TCGv_i64 orig = MAKE_TCGV_I64(temp_idx(args[i]));
if (is_signed) {
tcg_gen_ext32s_i64(temp, orig);
} else {
tcg_gen_ext32u_i64(temp, orig);
}
- args[i] = GET_TCGV_I64(temp);
+ args[i] = tcgv_i64_temp(temp);
}
}
#endif /* TCG_TARGET_EXTEND_ARGS */
@@ -1045,7 +1045,7 @@ void tcg_gen_callN(void *func, TCGArg ret, int nargs, TCGArg *args)
op->next = i + 1;
pi = 0;
- if (ret != TCG_CALL_DUMMY_ARG) {
+ if (ret != NULL) {
#if defined(__sparc__) && !defined(__arch64__) \
&& !defined(CONFIG_TCG_INTERPRETER)
if (orig_sizemask & 1) {
@@ -1054,25 +1054,25 @@ void tcg_gen_callN(void *func, TCGArg ret, int nargs, TCGArg *args)
two return temporaries, and reassemble below. */
retl = tcg_temp_new_i64();
reth = tcg_temp_new_i64();
- op->args[pi++] = GET_TCGV_I64(reth);
- op->args[pi++] = GET_TCGV_I64(retl);
+ op->args[pi++] = tcgv_i64_arg(reth);
+ op->args[pi++] = tcgv_i64_arg(retl);
nb_rets = 2;
} else {
- op->args[pi++] = ret;
+ op->args[pi++] = temp_arg(ret);
nb_rets = 1;
}
#else
if (TCG_TARGET_REG_BITS < 64 && (sizemask & 1)) {
#ifdef HOST_WORDS_BIGENDIAN
- op->args[pi++] = ret + 1;
- op->args[pi++] = ret;
+ op->args[pi++] = temp_arg(ret + 1);
+ op->args[pi++] = temp_arg(ret);
#else
- op->args[pi++] = ret;
- op->args[pi++] = ret + 1;
+ op->args[pi++] = temp_arg(ret);
+ op->args[pi++] = temp_arg(ret + 1);
#endif
nb_rets = 2;
} else {
- op->args[pi++] = ret;
+ op->args[pi++] = temp_arg(ret);
nb_rets = 1;
}
#endif
@@ -1103,17 +1103,17 @@ void tcg_gen_callN(void *func, TCGArg ret, int nargs, TCGArg *args)
have to get more complicated to differentiate between
stack arguments and register arguments. */
#if defined(HOST_WORDS_BIGENDIAN) != defined(TCG_TARGET_STACK_GROWSUP)
- op->args[pi++] = args[i] + 1;
- op->args[pi++] = args[i];
+ op->args[pi++] = temp_arg(args[i] + 1);
+ op->args[pi++] = temp_arg(args[i]);
#else
- op->args[pi++] = args[i];
- op->args[pi++] = args[i] + 1;
+ op->args[pi++] = temp_arg(args[i]);
+ op->args[pi++] = temp_arg(args[i] + 1);
#endif
real_args += 2;
continue;
}
- op->args[pi++] = args[i];
+ op->args[pi++] = temp_arg(args[i]);
real_args++;
}
op->args[pi++] = (uintptr_t)func;
@@ -1130,8 +1130,8 @@ void tcg_gen_callN(void *func, TCGArg ret, int nargs, TCGArg *args)
for (i = real_args = 0; i < orig_nargs; ++i) {
int is_64bit = orig_sizemask & (1 << (i+1)*2);
if (is_64bit) {
- TCGv_i32 h = MAKE_TCGV_I32(args[real_args++]);
- TCGv_i32 l = MAKE_TCGV_I32(args[real_args++]);
+ TCGv_i32 h = MAKE_TCGV_I32(temp_idx(args[real_args++]));
+ TCGv_i32 l = MAKE_TCGV_I32(temp_idx(args[real_args++]));
tcg_temp_free_i32(h);
tcg_temp_free_i32(l);
} else {
@@ -1142,7 +1142,7 @@ void tcg_gen_callN(void *func, TCGArg ret, int nargs, TCGArg *args)
/* The 32-bit ABI returned two 32-bit pieces. Re-assemble them.
Note that describing these as TCGv_i64 eliminates an unnecessary
zero-extension that tcg_gen_concat_i32_i64 would create. */
- tcg_gen_concat32_i64(MAKE_TCGV_I64(ret), retl, reth);
+ tcg_gen_concat32_i64(MAKE_TCGV_I64(temp_idx(ret)), retl, reth);
tcg_temp_free_i64(retl);
tcg_temp_free_i64(reth);
}
@@ -1150,7 +1150,7 @@ void tcg_gen_callN(void *func, TCGArg ret, int nargs, TCGArg *args)
for (i = 0; i < nargs; ++i) {
int is_64bit = sizemask & (1 << (i+1)*2);
if (!is_64bit) {
- TCGv_i64 temp = MAKE_TCGV_I64(args[i]);
+ TCGv_i64 temp = MAKE_TCGV_I64(temp_idx(args[i]));
tcg_temp_free_i64(temp);
}
}
--
2.13.6
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [Qemu-devel] [PULL 17/51] tcg: Introduce temp_tcgv_{i32,i64,ptr}
2017-10-25 9:34 [Qemu-devel] [PULL 00/51] tcg queued patches Richard Henderson
` (15 preceding siblings ...)
2017-10-25 9:35 ` [Qemu-devel] [PULL 16/51] tcg: Introduce tcgv_{i32, i64, ptr}_{arg, temp} Richard Henderson
@ 2017-10-25 9:35 ` Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 18/51] tcg: Remove GET_TCGV_* and MAKE_TCGV_* Richard Henderson
` (36 subsequent siblings)
53 siblings, 0 replies; 59+ messages in thread
From: Richard Henderson @ 2017-10-25 9:35 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tcg.h | 26 +++++++++++++++++-----
tcg/tcg.c | 74 +++++++++++++++++++++++++++------------------------------------
2 files changed, 53 insertions(+), 47 deletions(-)
diff --git a/tcg/tcg.h b/tcg/tcg.h
index fb8ce01664..9432962d7b 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -786,6 +786,21 @@ static inline TCGTemp *tcgv_ptr_temp(TCGv_ptr t)
return arg_temp(tcgv_ptr_arg(t));
}
+static inline TCGv_i32 temp_tcgv_i32(TCGTemp *t)
+{
+ return (TCGv_i32)temp_idx(t);
+}
+
+static inline TCGv_i64 temp_tcgv_i64(TCGTemp *t)
+{
+ return (TCGv_i64)temp_idx(t);
+}
+
+static inline TCGv_ptr temp_tcgv_ptr(TCGTemp *t)
+{
+ return (TCGv_ptr)temp_idx(t);
+}
+
static inline void tcg_set_insn_param(int op_idx, int arg, TCGArg v)
{
tcg_ctx.gen_op_buf[op_idx].args[arg] = v;
@@ -837,7 +852,8 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb);
void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size);
-int tcg_global_mem_new_internal(TCGType, TCGv_ptr, intptr_t, const char *);
+TCGTemp *tcg_global_mem_new_internal(TCGType, TCGv_ptr,
+ intptr_t, const char *);
TCGv_i32 tcg_global_reg_new_i32(TCGReg reg, const char *name);
TCGv_i64 tcg_global_reg_new_i64(TCGReg reg, const char *name);
@@ -851,8 +867,8 @@ void tcg_temp_free_i64(TCGv_i64 arg);
static inline TCGv_i32 tcg_global_mem_new_i32(TCGv_ptr reg, intptr_t offset,
const char *name)
{
- int idx = tcg_global_mem_new_internal(TCG_TYPE_I32, reg, offset, name);
- return MAKE_TCGV_I32(idx);
+ TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_I32, reg, offset, name);
+ return temp_tcgv_i32(t);
}
static inline TCGv_i32 tcg_temp_new_i32(void)
@@ -868,8 +884,8 @@ static inline TCGv_i32 tcg_temp_local_new_i32(void)
static inline TCGv_i64 tcg_global_mem_new_i64(TCGv_ptr reg, intptr_t offset,
const char *name)
{
- int idx = tcg_global_mem_new_internal(TCG_TYPE_I64, reg, offset, name);
- return MAKE_TCGV_I64(idx);
+ TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_I64, reg, offset, name);
+ return temp_tcgv_i64(t);
}
static inline TCGv_i64 tcg_temp_new_i64(void)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index cb985aabdc..0a9bfa4236 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -492,8 +492,8 @@ static inline TCGTemp *tcg_global_alloc(TCGContext *s)
return ts;
}
-static int tcg_global_reg_new_internal(TCGContext *s, TCGType type,
- TCGReg reg, const char *name)
+static TCGTemp *tcg_global_reg_new_internal(TCGContext *s, TCGType type,
+ TCGReg reg, const char *name)
{
TCGTemp *ts;
@@ -509,44 +509,43 @@ static int tcg_global_reg_new_internal(TCGContext *s, TCGType type,
ts->name = name;
tcg_regset_set_reg(s->reserved_regs, reg);
- return temp_idx(ts);
+ return ts;
}
void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size)
{
- int idx;
s->frame_start = start;
s->frame_end = start + size;
- idx = tcg_global_reg_new_internal(s, TCG_TYPE_PTR, reg, "_frame");
- s->frame_temp = &s->temps[idx];
+ s->frame_temp
+ = tcg_global_reg_new_internal(s, TCG_TYPE_PTR, reg, "_frame");
}
TCGv_i32 tcg_global_reg_new_i32(TCGReg reg, const char *name)
{
TCGContext *s = &tcg_ctx;
- int idx;
+ TCGTemp *t;
if (tcg_regset_test_reg(s->reserved_regs, reg)) {
tcg_abort();
}
- idx = tcg_global_reg_new_internal(s, TCG_TYPE_I32, reg, name);
- return MAKE_TCGV_I32(idx);
+ t = tcg_global_reg_new_internal(s, TCG_TYPE_I32, reg, name);
+ return temp_tcgv_i32(t);
}
TCGv_i64 tcg_global_reg_new_i64(TCGReg reg, const char *name)
{
TCGContext *s = &tcg_ctx;
- int idx;
+ TCGTemp *t;
if (tcg_regset_test_reg(s->reserved_regs, reg)) {
tcg_abort();
}
- idx = tcg_global_reg_new_internal(s, TCG_TYPE_I64, reg, name);
- return MAKE_TCGV_I64(idx);
+ t = tcg_global_reg_new_internal(s, TCG_TYPE_I64, reg, name);
+ return temp_tcgv_i64(t);
}
-int tcg_global_mem_new_internal(TCGType type, TCGv_ptr base,
- intptr_t offset, const char *name)
+TCGTemp *tcg_global_mem_new_internal(TCGType type, TCGv_ptr base,
+ intptr_t offset, const char *name)
{
TCGContext *s = &tcg_ctx;
TCGTemp *base_ts = &s->temps[GET_TCGV_PTR(base)];
@@ -598,10 +597,10 @@ int tcg_global_mem_new_internal(TCGType type, TCGv_ptr base,
ts->mem_offset = offset;
ts->name = name;
}
- return temp_idx(ts);
+ return ts;
}
-static int tcg_temp_new_internal(TCGType type, int temp_local)
+static TCGTemp *tcg_temp_new_internal(TCGType type, int temp_local)
{
TCGContext *s = &tcg_ctx;
TCGTemp *ts;
@@ -638,36 +637,30 @@ static int tcg_temp_new_internal(TCGType type, int temp_local)
ts->temp_allocated = 1;
ts->temp_local = temp_local;
}
- idx = temp_idx(ts);
}
#if defined(CONFIG_DEBUG_TCG)
s->temps_in_use++;
#endif
- return idx;
+ return ts;
}
TCGv_i32 tcg_temp_new_internal_i32(int temp_local)
{
- int idx;
-
- idx = tcg_temp_new_internal(TCG_TYPE_I32, temp_local);
- return MAKE_TCGV_I32(idx);
+ TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, temp_local);
+ return temp_tcgv_i32(t);
}
TCGv_i64 tcg_temp_new_internal_i64(int temp_local)
{
- int idx;
-
- idx = tcg_temp_new_internal(TCG_TYPE_I64, temp_local);
- return MAKE_TCGV_I64(idx);
+ TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, temp_local);
+ return temp_tcgv_i64(t);
}
-static void tcg_temp_free_internal(int idx)
+static void tcg_temp_free_internal(TCGTemp *ts)
{
TCGContext *s = &tcg_ctx;
- TCGTemp *ts;
- int k;
+ int k, idx;
#if defined(CONFIG_DEBUG_TCG)
s->temps_in_use--;
@@ -676,23 +669,23 @@ static void tcg_temp_free_internal(int idx)
}
#endif
- tcg_debug_assert(idx >= s->nb_globals && idx < s->nb_temps);
- ts = &s->temps[idx];
+ tcg_debug_assert(ts->temp_global == 0);
tcg_debug_assert(ts->temp_allocated != 0);
ts->temp_allocated = 0;
+ idx = temp_idx(ts);
k = ts->base_type + (ts->temp_local ? TCG_TYPE_COUNT : 0);
set_bit(idx, s->free_temps[k].l);
}
void tcg_temp_free_i32(TCGv_i32 arg)
{
- tcg_temp_free_internal(GET_TCGV_I32(arg));
+ tcg_temp_free_internal(tcgv_i32_temp(arg));
}
void tcg_temp_free_i64(TCGv_i64 arg)
{
- tcg_temp_free_internal(GET_TCGV_I64(arg));
+ tcg_temp_free_internal(tcgv_i64_temp(arg));
}
TCGv_i32 tcg_const_i32(int32_t val)
@@ -1001,7 +994,7 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args)
for (i = real_args = 0; i < nargs; ++i) {
int is_64bit = sizemask & (1 << (i+1)*2);
if (is_64bit) {
- TCGv_i64 orig = MAKE_TCGV_I64(temp_idx(args[i]));
+ TCGv_i64 orig = temp_tcgv_i64(args[i]);
TCGv_i32 h = tcg_temp_new_i32();
TCGv_i32 l = tcg_temp_new_i32();
tcg_gen_extr_i64_i32(l, h, orig);
@@ -1021,7 +1014,7 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args)
int is_signed = sizemask & (2 << (i+1)*2);
if (!is_64bit) {
TCGv_i64 temp = tcg_temp_new_i64();
- TCGv_i64 orig = MAKE_TCGV_I64(temp_idx(args[i]));
+ TCGv_i64 orig = temp_tcgv_i64(args[i]);
if (is_signed) {
tcg_gen_ext32s_i64(temp, orig);
} else {
@@ -1130,10 +1123,8 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args)
for (i = real_args = 0; i < orig_nargs; ++i) {
int is_64bit = orig_sizemask & (1 << (i+1)*2);
if (is_64bit) {
- TCGv_i32 h = MAKE_TCGV_I32(temp_idx(args[real_args++]));
- TCGv_i32 l = MAKE_TCGV_I32(temp_idx(args[real_args++]));
- tcg_temp_free_i32(h);
- tcg_temp_free_i32(l);
+ tcg_temp_free_internal(args[real_args++]);
+ tcg_temp_free_internal(args[real_args++]);
} else {
real_args++;
}
@@ -1142,7 +1133,7 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args)
/* The 32-bit ABI returned two 32-bit pieces. Re-assemble them.
Note that describing these as TCGv_i64 eliminates an unnecessary
zero-extension that tcg_gen_concat_i32_i64 would create. */
- tcg_gen_concat32_i64(MAKE_TCGV_I64(temp_idx(ret)), retl, reth);
+ tcg_gen_concat32_i64(temp_tcgv_i64(ret), retl, reth);
tcg_temp_free_i64(retl);
tcg_temp_free_i64(reth);
}
@@ -1150,8 +1141,7 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args)
for (i = 0; i < nargs; ++i) {
int is_64bit = sizemask & (1 << (i+1)*2);
if (!is_64bit) {
- TCGv_i64 temp = MAKE_TCGV_I64(temp_idx(args[i]));
- tcg_temp_free_i64(temp);
+ tcg_temp_free_internal(args[i]);
}
}
#endif /* TCG_TARGET_EXTEND_ARGS */
--
2.13.6
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [Qemu-devel] [PULL 18/51] tcg: Remove GET_TCGV_* and MAKE_TCGV_*
2017-10-25 9:34 [Qemu-devel] [PULL 00/51] tcg queued patches Richard Henderson
` (16 preceding siblings ...)
2017-10-25 9:35 ` [Qemu-devel] [PULL 17/51] tcg: Introduce temp_tcgv_{i32,i64,ptr} Richard Henderson
@ 2017-10-25 9:35 ` Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 19/51] tcg: Remove TCGV_EQUAL* Richard Henderson
` (35 subsequent siblings)
53 siblings, 0 replies; 59+ messages in thread
From: Richard Henderson @ 2017-10-25 9:35 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
The GET and MAKE functions weren't really specific enough.
We now have a full complement of functions that convert exactly
between temporaries, arguments, tcgv pointers, and indices.
The target/sparc change is also a bug fix, which would have affected
a host that defines TCG_TARGET_HAS_extr[lh]_i64_i32, i.e. MIPS64.
Reviewed-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/helper-head.h | 4 ---
tcg/tcg.h | 78 ++++++++++++++++------------------------------
target/sparc/translate.c | 15 +++------
tcg/tcg-op.c | 4 +--
tcg/tcg.c | 2 +-
5 files changed, 34 insertions(+), 69 deletions(-)
diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h
index 13286018fd..639eefdbc0 100644
--- a/include/exec/helper-head.h
+++ b/include/exec/helper-head.h
@@ -20,10 +20,6 @@
#define HELPER(name) glue(helper_, name)
-#define GET_TCGV_i32 GET_TCGV_I32
-#define GET_TCGV_i64 GET_TCGV_I64
-#define GET_TCGV_ptr GET_TCGV_PTR
-
/* Some types that make sense in C, but not for TCG. */
#define dh_alias_i32 i32
#define dh_alias_s32 i32
diff --git a/tcg/tcg.h b/tcg/tcg.h
index 9432962d7b..b7fac0db8a 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -414,10 +414,7 @@ typedef tcg_target_ulong TCGArg;
integers, but keeping them in pointer types like this means that the
compiler will complain if you accidentally pass a TCGv_i32 to a
function which takes a TCGv_i64, and so on. Only the internals of
- TCG need to care about the actual contents of the types, and they always
- box and unbox via the MAKE_TCGV_* and GET_TCGV_* functions.
- Converting to and from intptr_t rather than int reduces the number
- of sign-extension instructions that get implied on 64-bit hosts. */
+ TCG need to care about the actual contents of the types. */
typedef struct TCGv_i32_d *TCGv_i32;
typedef struct TCGv_i64_d *TCGv_i64;
@@ -431,53 +428,18 @@ typedef TCGv_ptr TCGv_env;
#error Unhandled TARGET_LONG_BITS value
#endif
-static inline TCGv_i32 QEMU_ARTIFICIAL MAKE_TCGV_I32(intptr_t i)
-{
- return (TCGv_i32)i;
-}
-
-static inline TCGv_i64 QEMU_ARTIFICIAL MAKE_TCGV_I64(intptr_t i)
-{
- return (TCGv_i64)i;
-}
-
-static inline TCGv_ptr QEMU_ARTIFICIAL MAKE_TCGV_PTR(intptr_t i)
-{
- return (TCGv_ptr)i;
-}
-
-static inline intptr_t QEMU_ARTIFICIAL GET_TCGV_I32(TCGv_i32 t)
-{
- return (intptr_t)t;
-}
-
-static inline intptr_t QEMU_ARTIFICIAL GET_TCGV_I64(TCGv_i64 t)
-{
- return (intptr_t)t;
-}
-
-static inline intptr_t QEMU_ARTIFICIAL GET_TCGV_PTR(TCGv_ptr t)
-{
- return (intptr_t)t;
-}
-
-#if TCG_TARGET_REG_BITS == 32
-#define TCGV_LOW(t) MAKE_TCGV_I32(GET_TCGV_I64(t))
-#define TCGV_HIGH(t) MAKE_TCGV_I32(GET_TCGV_I64(t) + 1)
-#endif
-
-#define TCGV_EQUAL_I32(a, b) (GET_TCGV_I32(a) == GET_TCGV_I32(b))
-#define TCGV_EQUAL_I64(a, b) (GET_TCGV_I64(a) == GET_TCGV_I64(b))
-#define TCGV_EQUAL_PTR(a, b) (GET_TCGV_PTR(a) == GET_TCGV_PTR(b))
+#define TCGV_EQUAL_I32(a, b) ((a) == (b))
+#define TCGV_EQUAL_I64(a, b) ((a) == (b))
+#define TCGV_EQUAL_PTR(a, b) ((a) == (b))
/* Dummy definition to avoid compiler warnings. */
-#define TCGV_UNUSED_I32(x) x = MAKE_TCGV_I32(-1)
-#define TCGV_UNUSED_I64(x) x = MAKE_TCGV_I64(-1)
-#define TCGV_UNUSED_PTR(x) x = MAKE_TCGV_PTR(-1)
+#define TCGV_UNUSED_I32(x) (x = (TCGv_i32)-1)
+#define TCGV_UNUSED_I64(x) (x = (TCGv_i64)-1)
+#define TCGV_UNUSED_PTR(x) (x = (TCGv_ptr)-1)
-#define TCGV_IS_UNUSED_I32(x) (GET_TCGV_I32(x) == -1)
-#define TCGV_IS_UNUSED_I64(x) (GET_TCGV_I64(x) == -1)
-#define TCGV_IS_UNUSED_PTR(x) (GET_TCGV_PTR(x) == -1)
+#define TCGV_IS_UNUSED_I32(x) ((x) == (TCGv_i32)-1)
+#define TCGV_IS_UNUSED_I64(x) ((x) == (TCGv_i64)-1)
+#define TCGV_IS_UNUSED_PTR(x) ((x) == (TCGv_ptr)-1)
/* call flags */
/* Helper does not read globals (either directly or through an exception). It
@@ -801,6 +763,18 @@ static inline TCGv_ptr temp_tcgv_ptr(TCGTemp *t)
return (TCGv_ptr)temp_idx(t);
}
+#if TCG_TARGET_REG_BITS == 32
+static inline TCGv_i32 TCGV_LOW(TCGv_i64 t)
+{
+ return temp_tcgv_i32(tcgv_i64_temp(t));
+}
+
+static inline TCGv_i32 TCGV_HIGH(TCGv_i64 t)
+{
+ return temp_tcgv_i32(tcgv_i64_temp(t) + 1);
+}
+#endif
+
static inline void tcg_set_insn_param(int op_idx, int arg, TCGArg v)
{
tcg_ctx.gen_op_buf[op_idx].args[arg] = v;
@@ -972,8 +946,8 @@ do {\
} while (0)
#if UINTPTR_MAX == UINT32_MAX
-#define TCGV_NAT_TO_PTR(n) MAKE_TCGV_PTR(GET_TCGV_I32(n))
-#define TCGV_PTR_TO_NAT(n) MAKE_TCGV_I32(GET_TCGV_PTR(n))
+static inline TCGv_ptr TCGV_NAT_TO_PTR(TCGv_i32 n) { return (TCGv_ptr)n; }
+static inline TCGv_i32 TCGV_PTR_TO_NAT(TCGv_ptr n) { return (TCGv_i32)n; }
#define tcg_const_ptr(V) TCGV_NAT_TO_PTR(tcg_const_i32((intptr_t)(V)))
#define tcg_global_reg_new_ptr(R, N) \
@@ -983,8 +957,8 @@ do {\
#define tcg_temp_new_ptr() TCGV_NAT_TO_PTR(tcg_temp_new_i32())
#define tcg_temp_free_ptr(T) tcg_temp_free_i32(TCGV_PTR_TO_NAT(T))
#else
-#define TCGV_NAT_TO_PTR(n) MAKE_TCGV_PTR(GET_TCGV_I64(n))
-#define TCGV_PTR_TO_NAT(n) MAKE_TCGV_I64(GET_TCGV_PTR(n))
+static inline TCGv_ptr TCGV_NAT_TO_PTR(TCGv_i64 n) { return (TCGv_ptr)n; }
+static inline TCGv_i64 TCGV_PTR_TO_NAT(TCGv_ptr n) { return (TCGv_i64)n; }
#define tcg_const_ptr(V) TCGV_NAT_TO_PTR(tcg_const_i64((intptr_t)(V)))
#define tcg_global_reg_new_ptr(R, N) \
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 6290705b11..83a7d8e3ee 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -171,18 +171,13 @@ static TCGv_i32 gen_load_fpr_F(DisasContext *dc, unsigned int src)
return TCGV_HIGH(cpu_fpr[src / 2]);
}
#else
+ TCGv_i32 ret = get_temp_i32(dc);
if (src & 1) {
- return MAKE_TCGV_I32(GET_TCGV_I64(cpu_fpr[src / 2]));
+ tcg_gen_extrl_i64_i32(ret, cpu_fpr[src / 2]);
} else {
- TCGv_i32 ret = get_temp_i32(dc);
- TCGv_i64 t = tcg_temp_new_i64();
-
- tcg_gen_shri_i64(t, cpu_fpr[src / 2], 32);
- tcg_gen_extrl_i64_i32(ret, t);
- tcg_temp_free_i64(t);
-
- return ret;
+ tcg_gen_extrh_i64_i32(ret, cpu_fpr[src / 2]);
}
+ return ret;
#endif
}
@@ -195,7 +190,7 @@ static void gen_store_fpr_F(DisasContext *dc, unsigned int dst, TCGv_i32 v)
tcg_gen_mov_i32(TCGV_HIGH(cpu_fpr[dst / 2]), v);
}
#else
- TCGv_i64 t = MAKE_TCGV_I64(GET_TCGV_I32(v));
+ TCGv_i64 t = (TCGv_i64)v;
tcg_gen_deposit_i64(cpu_fpr[dst / 2], cpu_fpr[dst / 2], t,
(dst & 1 ? 0 : 32), 32);
#endif
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index be4b623e82..9561510d9c 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -2460,7 +2460,7 @@ void tcg_gen_extrl_i64_i32(TCGv_i32 ret, TCGv_i64 arg)
tcg_gen_op2(INDEX_op_extrl_i64_i32,
tcgv_i32_arg(ret), tcgv_i64_arg(arg));
} else {
- tcg_gen_mov_i32(ret, MAKE_TCGV_I32(GET_TCGV_I64(arg)));
+ tcg_gen_mov_i32(ret, (TCGv_i32)arg);
}
}
@@ -2474,7 +2474,7 @@ void tcg_gen_extrh_i64_i32(TCGv_i32 ret, TCGv_i64 arg)
} else {
TCGv_i64 t = tcg_temp_new_i64();
tcg_gen_shri_i64(t, arg, 32);
- tcg_gen_mov_i32(ret, MAKE_TCGV_I32(GET_TCGV_I64(t)));
+ tcg_gen_mov_i32(ret, (TCGv_i32)t);
tcg_temp_free_i64(t);
}
}
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 0a9bfa4236..3a73912827 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -548,7 +548,7 @@ TCGTemp *tcg_global_mem_new_internal(TCGType type, TCGv_ptr base,
intptr_t offset, const char *name)
{
TCGContext *s = &tcg_ctx;
- TCGTemp *base_ts = &s->temps[GET_TCGV_PTR(base)];
+ TCGTemp *base_ts = tcgv_ptr_temp(base);
TCGTemp *ts = tcg_global_alloc(s);
int indirect_reg = 0, bigendian = 0;
#ifdef HOST_WORDS_BIGENDIAN
--
2.13.6
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [Qemu-devel] [PULL 19/51] tcg: Remove TCGV_EQUAL*
2017-10-25 9:34 [Qemu-devel] [PULL 00/51] tcg queued patches Richard Henderson
` (17 preceding siblings ...)
2017-10-25 9:35 ` [Qemu-devel] [PULL 18/51] tcg: Remove GET_TCGV_* and MAKE_TCGV_* Richard Henderson
@ 2017-10-25 9:35 ` Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 20/51] qom: Introduce CPUClass.tcg_initialize Richard Henderson
` (34 subsequent siblings)
53 siblings, 0 replies; 59+ messages in thread
From: Richard Henderson @ 2017-10-25 9:35 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
When we used structures for TCGv_*, we needed a macro in order to
perform a comparison. Now that we use pointers, this is just clutter.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tcg-op.h | 6 ++----
tcg/tcg.h | 4 ----
target/cris/translate.c | 6 +++---
target/i386/translate.c | 6 +++---
target/m68k/translate.c | 2 +-
target/ppc/translate.c | 4 ++--
6 files changed, 11 insertions(+), 17 deletions(-)
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index ab2f3c6cee..3129159907 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -328,7 +328,7 @@ static inline void tcg_gen_discard_i32(TCGv_i32 arg)
static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg)
{
- if (!TCGV_EQUAL_I32(ret, arg)) {
+ if (ret != arg) {
tcg_gen_op2_i32(INDEX_op_mov_i32, ret, arg);
}
}
@@ -522,7 +522,7 @@ static inline void tcg_gen_discard_i64(TCGv_i64 arg)
static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg)
{
- if (!TCGV_EQUAL_I64(ret, arg)) {
+ if (ret != arg) {
tcg_gen_op2_i64(INDEX_op_mov_i64, ret, arg);
}
}
@@ -809,7 +809,6 @@ void tcg_gen_lookup_and_goto_ptr(void);
#define tcg_temp_free tcg_temp_free_i32
#define TCGV_UNUSED(x) TCGV_UNUSED_I32(x)
#define TCGV_IS_UNUSED(x) TCGV_IS_UNUSED_I32(x)
-#define TCGV_EQUAL(a, b) TCGV_EQUAL_I32(a, b)
#define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i32
#define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i32
#else
@@ -820,7 +819,6 @@ void tcg_gen_lookup_and_goto_ptr(void);
#define tcg_temp_free tcg_temp_free_i64
#define TCGV_UNUSED(x) TCGV_UNUSED_I64(x)
#define TCGV_IS_UNUSED(x) TCGV_IS_UNUSED_I64(x)
-#define TCGV_EQUAL(a, b) TCGV_EQUAL_I64(a, b)
#define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i64
#define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i64
#endif
diff --git a/tcg/tcg.h b/tcg/tcg.h
index b7fac0db8a..8f692bc6cf 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -428,10 +428,6 @@ typedef TCGv_ptr TCGv_env;
#error Unhandled TARGET_LONG_BITS value
#endif
-#define TCGV_EQUAL_I32(a, b) ((a) == (b))
-#define TCGV_EQUAL_I64(a, b) ((a) == (b))
-#define TCGV_EQUAL_PTR(a, b) ((a) == (b))
-
/* Dummy definition to avoid compiler warnings. */
#define TCGV_UNUSED_I32(x) (x = (TCGv_i32)-1)
#define TCGV_UNUSED_I64(x) (x = (TCGv_i64)-1)
diff --git a/target/cris/translate.c b/target/cris/translate.c
index 38a999e6f1..55a9202777 100644
--- a/target/cris/translate.c
+++ b/target/cris/translate.c
@@ -839,7 +839,7 @@ static void cris_alu(DisasContext *dc, int op,
}
tcg_gen_or_tl(d, d, tmp);
}
- if (!TCGV_EQUAL(tmp, d)) {
+ if (tmp != d) {
tcg_temp_free(tmp);
}
}
@@ -1162,7 +1162,7 @@ static inline void t_gen_sext(TCGv d, TCGv s, int size)
tcg_gen_ext8s_i32(d, s);
} else if (size == 2) {
tcg_gen_ext16s_i32(d, s);
- } else if (!TCGV_EQUAL(d, s)) {
+ } else {
tcg_gen_mov_tl(d, s);
}
}
@@ -1173,7 +1173,7 @@ static inline void t_gen_zext(TCGv d, TCGv s, int size)
tcg_gen_ext8u_i32(d, s);
} else if (size == 2) {
tcg_gen_ext16u_i32(d, s);
- } else if (!TCGV_EQUAL(d, s)) {
+ } else {
tcg_gen_mov_tl(d, s);
}
}
diff --git a/target/i386/translate.c b/target/i386/translate.c
index 5f24a2de3c..d6697f721c 100644
--- a/target/i386/translate.c
+++ b/target/i386/translate.c
@@ -742,7 +742,7 @@ static CCPrepare gen_prepare_eflags_c(DisasContext *s, TCGv reg)
size = s->cc_op - CC_OP_SUBB;
t1 = gen_ext_tl(cpu_tmp0, cpu_cc_src, size, false);
/* If no temporary was used, be careful not to alias t1 and t0. */
- t0 = TCGV_EQUAL(t1, cpu_cc_src) ? cpu_tmp0 : reg;
+ t0 = t1 == cpu_cc_src ? cpu_tmp0 : reg;
tcg_gen_mov_tl(t0, cpu_cc_srcT);
gen_extu(size, t0);
goto add_sub;
@@ -951,7 +951,7 @@ static CCPrepare gen_prepare_cc(DisasContext *s, int b, TCGv reg)
break;
case JCC_L:
gen_compute_eflags(s);
- if (TCGV_EQUAL(reg, cpu_cc_src)) {
+ if (reg == cpu_cc_src) {
reg = cpu_tmp0;
}
tcg_gen_shri_tl(reg, cpu_cc_src, 4); /* CC_O -> CC_S */
@@ -962,7 +962,7 @@ static CCPrepare gen_prepare_cc(DisasContext *s, int b, TCGv reg)
default:
case JCC_LE:
gen_compute_eflags(s);
- if (TCGV_EQUAL(reg, cpu_cc_src)) {
+ if (reg == cpu_cc_src) {
reg = cpu_tmp0;
}
tcg_gen_shri_tl(reg, cpu_cc_src, 4); /* CC_O -> CC_S */
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index d738f32f9c..63b1552669 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -58,7 +58,7 @@ static TCGv_i64 cpu_macc[4];
#define QREG_SP get_areg(s, 7)
static TCGv NULL_QREG;
-#define IS_NULL_QREG(t) (TCGV_EQUAL(t, NULL_QREG))
+#define IS_NULL_QREG(t) (t == NULL_QREG)
/* Used to distinguish stores from bad addressing modes. */
static TCGv store_dummy;
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index a81ff69d75..616cf8f50e 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -902,7 +902,7 @@ static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
gen_set_Rc0(ctx, t0);
}
- if (!TCGV_EQUAL(t0, ret)) {
+ if (t0 != ret) {
tcg_gen_mov_tl(ret, t0);
tcg_temp_free(t0);
}
@@ -1438,7 +1438,7 @@ static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
gen_set_Rc0(ctx, t0);
}
- if (!TCGV_EQUAL(t0, ret)) {
+ if (t0 != ret) {
tcg_gen_mov_tl(ret, t0);
tcg_temp_free(t0);
}
--
2.13.6
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [Qemu-devel] [PULL 20/51] qom: Introduce CPUClass.tcg_initialize
2017-10-25 9:34 [Qemu-devel] [PULL 00/51] tcg queued patches Richard Henderson
` (18 preceding siblings ...)
2017-10-25 9:35 ` [Qemu-devel] [PULL 19/51] tcg: Remove TCGV_EQUAL* Richard Henderson
@ 2017-10-25 9:35 ` Richard Henderson
2017-10-26 12:45 ` Eduardo Habkost
2017-10-25 9:35 ` [Qemu-devel] [PULL 21/51] tcg: Use offsets not indices for TCGv_* Richard Henderson
` (33 subsequent siblings)
53 siblings, 1 reply; 59+ messages in thread
From: Richard Henderson @ 2017-10-25 9:35 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
Move target cpu tcg initialization to common code,
called from cpu_exec_realizefn.
Acked-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Emilio G. Cota <cota@braap.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/qom/cpu.h | 8 ++++++--
target/sparc/cpu.h | 2 +-
exec.c | 7 ++++++-
target/alpha/cpu.c | 3 +--
target/alpha/translate.c | 6 ------
target/arm/cpu.c | 6 +-----
target/cris/cpu.c | 16 ++++++----------
target/hppa/cpu.c | 3 +--
target/hppa/translate.c | 6 ------
target/i386/cpu.c | 5 +----
target/i386/translate.c | 6 ------
target/lm32/cpu.c | 7 +------
target/m68k/cpu.c | 7 +------
target/microblaze/cpu.c | 7 +------
target/mips/cpu.c | 5 +----
target/mips/translate.c | 7 -------
target/moxie/cpu.c | 7 +------
target/moxie/translate.c | 6 ------
target/nios2/cpu.c | 7 +------
target/openrisc/cpu.c | 7 +------
target/ppc/translate.c | 6 ------
target/ppc/translate_init.c | 5 +----
target/s390x/cpu.c | 7 +------
target/sh4/cpu.c | 5 +----
target/sh4/translate.c | 7 -------
target/sparc/cpu.c | 5 +----
target/sparc/translate.c | 9 +--------
target/tilegx/cpu.c | 7 +------
target/tricore/cpu.c | 5 +----
target/tricore/translate.c | 5 +----
target/unicore32/cpu.c | 7 +------
target/xtensa/cpu.c | 7 +------
32 files changed, 40 insertions(+), 163 deletions(-)
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index 0efebdbcf4..df0ba86202 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -195,10 +195,8 @@ typedef struct CPUClass {
void *opaque);
const struct VMStateDescription *vmsd;
- int gdb_num_core_regs;
const char *gdb_core_xml_file;
gchar * (*gdb_arch_name)(CPUState *cpu);
- bool gdb_stop_before_watchpoint;
void (*cpu_exec_enter)(CPUState *cpu);
void (*cpu_exec_exit)(CPUState *cpu);
@@ -206,6 +204,12 @@ typedef struct CPUClass {
void (*disas_set_info)(CPUState *cpu, disassemble_info *info);
vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len);
+ void (*tcg_initialize)(void);
+
+ /* Keep non-pointer data at the end to minimize holes. */
+ int gdb_num_core_regs;
+ bool gdb_stop_before_watchpoint;
+ bool tcg_initialized;
} CPUClass;
#ifdef HOST_WORDS_BIGENDIAN
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index 1598f65927..bf2b8931cc 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -594,7 +594,7 @@ int sparc_cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
/* translate.c */
-void gen_intermediate_code_init(CPUSPARCState *env);
+void sparc_tcg_init(void);
/* cpu-exec.c */
diff --git a/exec.c b/exec.c
index db5ae23118..de03053d32 100644
--- a/exec.c
+++ b/exec.c
@@ -791,10 +791,15 @@ void cpu_exec_initfn(CPUState *cpu)
void cpu_exec_realizefn(CPUState *cpu, Error **errp)
{
- CPUClass *cc ATTRIBUTE_UNUSED = CPU_GET_CLASS(cpu);
+ CPUClass *cc = CPU_GET_CLASS(cpu);
cpu_list_add(cpu);
+ if (tcg_enabled() && !cc->tcg_initialized) {
+ cc->tcg_initialized = true;
+ cc->tcg_initialize();
+ }
+
#ifndef CONFIG_USER_ONLY
if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index b8a21f4e01..bc9520535b 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -260,8 +260,6 @@ static void alpha_cpu_initfn(Object *obj)
cs->env_ptr = env;
tlb_flush(cs);
- alpha_translate_init();
-
env->lock_addr = -1;
#if defined(CONFIG_USER_ONLY)
env->flags = ENV_FLAG_PS_USER | ENV_FLAG_FEN;
@@ -299,6 +297,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
dc->vmsd = &vmstate_alpha_cpu;
#endif
cc->disas_set_info = alpha_cpu_disas_set_info;
+ cc->tcg_initialize = alpha_translate_init;
cc->gdb_num_core_regs = 67;
}
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
index f32c95b9a1..3c8d1dc333 100644
--- a/target/alpha/translate.c
+++ b/target/alpha/translate.c
@@ -124,14 +124,8 @@ void alpha_translate_init(void)
};
#endif
- static bool done_init = 0;
int i;
- if (done_init) {
- return;
- }
- done_init = 1;
-
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
tcg_ctx.tcg_env = cpu_env;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 88578f360e..056284985d 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -534,7 +534,6 @@ static void arm_cpu_initfn(Object *obj)
{
CPUState *cs = CPU(obj);
ARMCPU *cpu = ARM_CPU(obj);
- static bool inited;
cs->env_ptr = &cpu->env;
cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
@@ -578,10 +577,6 @@ static void arm_cpu_initfn(Object *obj)
if (tcg_enabled()) {
cpu->psci_version = 2; /* TCG implements PSCI 0.2 */
- if (!inited) {
- inited = true;
- arm_translate_init();
- }
}
}
@@ -1765,6 +1760,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
#endif
cc->disas_set_info = arm_disas_set_info;
+ cc->tcg_initialize = arm_translate_init;
}
static void cpu_register(const ARMCPUInfo *info)
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
index 88d93f2d11..527a3448bf 100644
--- a/target/cris/cpu.c
+++ b/target/cris/cpu.c
@@ -181,7 +181,6 @@ static void cris_cpu_initfn(Object *obj)
CRISCPU *cpu = CRIS_CPU(obj);
CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(obj);
CPUCRISState *env = &cpu->env;
- static bool tcg_initialized;
cs->env_ptr = env;
@@ -191,15 +190,6 @@ static void cris_cpu_initfn(Object *obj)
/* IRQ and NMI lines. */
qdev_init_gpio_in(DEVICE(cpu), cris_cpu_set_irq, 2);
#endif
-
- if (tcg_enabled() && !tcg_initialized) {
- tcg_initialized = true;
- if (env->pregs[PR_VR] < 32) {
- cris_initialize_crisv10_tcg();
- } else {
- cris_initialize_tcg();
- }
- }
}
static void crisv8_cpu_class_init(ObjectClass *oc, void *data)
@@ -210,6 +200,7 @@ static void crisv8_cpu_class_init(ObjectClass *oc, void *data)
ccc->vr = 8;
cc->do_interrupt = crisv10_cpu_do_interrupt;
cc->gdb_read_register = crisv10_cpu_gdb_read_register;
+ cc->tcg_initialize = cris_initialize_crisv10_tcg;
}
static void crisv9_cpu_class_init(ObjectClass *oc, void *data)
@@ -220,6 +211,7 @@ static void crisv9_cpu_class_init(ObjectClass *oc, void *data)
ccc->vr = 9;
cc->do_interrupt = crisv10_cpu_do_interrupt;
cc->gdb_read_register = crisv10_cpu_gdb_read_register;
+ cc->tcg_initialize = cris_initialize_crisv10_tcg;
}
static void crisv10_cpu_class_init(ObjectClass *oc, void *data)
@@ -230,6 +222,7 @@ static void crisv10_cpu_class_init(ObjectClass *oc, void *data)
ccc->vr = 10;
cc->do_interrupt = crisv10_cpu_do_interrupt;
cc->gdb_read_register = crisv10_cpu_gdb_read_register;
+ cc->tcg_initialize = cris_initialize_crisv10_tcg;
}
static void crisv11_cpu_class_init(ObjectClass *oc, void *data)
@@ -240,6 +233,7 @@ static void crisv11_cpu_class_init(ObjectClass *oc, void *data)
ccc->vr = 11;
cc->do_interrupt = crisv10_cpu_do_interrupt;
cc->gdb_read_register = crisv10_cpu_gdb_read_register;
+ cc->tcg_initialize = cris_initialize_crisv10_tcg;
}
static void crisv17_cpu_class_init(ObjectClass *oc, void *data)
@@ -250,6 +244,7 @@ static void crisv17_cpu_class_init(ObjectClass *oc, void *data)
ccc->vr = 17;
cc->do_interrupt = crisv10_cpu_do_interrupt;
cc->gdb_read_register = crisv10_cpu_gdb_read_register;
+ cc->tcg_initialize = cris_initialize_crisv10_tcg;
}
static void crisv32_cpu_class_init(ObjectClass *oc, void *data)
@@ -322,6 +317,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_stop_before_watchpoint = true;
cc->disas_set_info = cris_disas_set_info;
+ cc->tcg_initialize = cris_initialize_tcg;
}
static const TypeInfo cris_cpu_type_info = {
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index a477b452f0..9e7b0d4ccb 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -108,8 +108,6 @@ static void hppa_cpu_initfn(Object *obj)
cs->env_ptr = env;
cpu_hppa_loaded_fr0(env);
set_snan_bit_is_one(true, &env->fp_status);
-
- hppa_translate_init();
}
static ObjectClass *hppa_cpu_class_by_name(const char *cpu_model)
@@ -136,6 +134,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = hppa_cpu_gdb_write_register;
cc->handle_mmu_fault = hppa_cpu_handle_mmu_fault;
cc->disas_set_info = hppa_cpu_disas_set_info;
+ cc->tcg_initialize = hppa_translate_init;
cc->gdb_num_core_regs = 128;
}
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 26242f4b3c..334ee74e4c 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -124,14 +124,8 @@ void hppa_translate_init(void)
"r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
};
- static bool done_init = 0;
int i;
- if (done_init) {
- return;
- }
- done_init = 1;
-
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
tcg_ctx.tcg_env = cpu_env;
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 98732cd65f..53ec94ac9b 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -3719,10 +3719,6 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
return;
}
- if (tcg_enabled()) {
- tcg_x86_init();
- }
-
#ifndef CONFIG_USER_ONLY
qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
@@ -4216,6 +4212,7 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
#endif
cc->cpu_exec_enter = x86_cpu_exec_enter;
cc->cpu_exec_exit = x86_cpu_exec_exit;
+ cc->tcg_initialize = tcg_x86_init;
dc->user_creatable = true;
}
diff --git a/target/i386/translate.c b/target/i386/translate.c
index d6697f721c..da13fe4d11 100644
--- a/target/i386/translate.c
+++ b/target/i386/translate.c
@@ -8366,12 +8366,6 @@ void tcg_x86_init(void)
"bnd0_ub", "bnd1_ub", "bnd2_ub", "bnd3_ub"
};
int i;
- static bool initialized;
-
- if (initialized) {
- return;
- }
- initialized = true;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
tcg_ctx.tcg_env = cpu_env;
diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c
index bf081f56d2..7f3a292f2b 100644
--- a/target/lm32/cpu.c
+++ b/target/lm32/cpu.c
@@ -163,16 +163,10 @@ static void lm32_cpu_initfn(Object *obj)
CPUState *cs = CPU(obj);
LM32CPU *cpu = LM32_CPU(obj);
CPULM32State *env = &cpu->env;
- static bool tcg_initialized;
cs->env_ptr = env;
env->flags = 0;
-
- if (tcg_enabled() && !tcg_initialized) {
- tcg_initialized = true;
- lm32_translate_init();
- }
}
static void lm32_basic_cpu_initfn(Object *obj)
@@ -286,6 +280,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_stop_before_watchpoint = true;
cc->debug_excp_handler = lm32_debug_excp_handler;
cc->disas_set_info = lm32_cpu_disas_set_info;
+ cc->tcg_initialize = lm32_translate_init;
}
static void lm32_register_cpu_type(const LM32CPUInfo *info)
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index 8c70e0805c..5da19e570b 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -247,14 +247,8 @@ static void m68k_cpu_initfn(Object *obj)
CPUState *cs = CPU(obj);
M68kCPU *cpu = M68K_CPU(obj);
CPUM68KState *env = &cpu->env;
- static bool inited;
cs->env_ptr = env;
-
- if (tcg_enabled() && !inited) {
- inited = true;
- m68k_tcg_init();
- }
}
static const VMStateDescription vmstate_m68k_cpu = {
@@ -288,6 +282,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
cc->get_phys_page_debug = m68k_cpu_get_phys_page_debug;
#endif
cc->disas_set_info = m68k_cpu_disas_set_info;
+ cc->tcg_initialize = m68k_tcg_init;
cc->gdb_num_core_regs = 18;
cc->gdb_core_xml_file = "cf-core.xml";
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index ddffe86e9b..5700652e06 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -205,7 +205,6 @@ static void mb_cpu_initfn(Object *obj)
CPUState *cs = CPU(obj);
MicroBlazeCPU *cpu = MICROBLAZE_CPU(obj);
CPUMBState *env = &cpu->env;
- static bool tcg_initialized;
cs->env_ptr = env;
@@ -215,11 +214,6 @@ static void mb_cpu_initfn(Object *obj)
/* Inbound IRQ and FIR lines */
qdev_init_gpio_in(DEVICE(cpu), microblaze_cpu_set_irq, 2);
#endif
-
- if (tcg_enabled() && !tcg_initialized) {
- tcg_initialized = true;
- mb_tcg_init();
- }
}
static const VMStateDescription vmstate_mb_cpu = {
@@ -289,6 +283,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_num_core_regs = 32 + 5;
cc->disas_set_info = mb_disas_set_info;
+ cc->tcg_initialize = mb_tcg_init;
}
static const TypeInfo mb_cpu_type_info = {
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index c15b894362..0ae70288dd 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -150,10 +150,6 @@ static void mips_cpu_initfn(Object *obj)
cs->env_ptr = env;
env->cpu_model = mcc->cpu_def;
-
- if (tcg_enabled()) {
- mips_tcg_init();
- }
}
static char *mips_cpu_type_name(const char *cpu_model)
@@ -202,6 +198,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->vmsd = &vmstate_mips_cpu;
#endif
cc->disas_set_info = mips_cpu_disas_set_info;
+ cc->tcg_initialize = mips_tcg_init;
cc->gdb_num_core_regs = 73;
cc->gdb_stop_before_watchpoint = true;
diff --git a/target/mips/translate.c b/target/mips/translate.c
index ac05f3aa09..ef07fa827e 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -20453,11 +20453,6 @@ void mips_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
void mips_tcg_init(void)
{
int i;
- static int inited;
-
- /* Initialize various static tables. */
- if (inited)
- return;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
tcg_ctx.tcg_env = cpu_env;
@@ -20506,8 +20501,6 @@ void mips_tcg_init(void)
fpu_fcr31 = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUMIPSState, active_fpu.fcr31),
"fcr31");
-
- inited = 1;
}
#include "translate_init.c"
diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c
index 30bd44fcad..24ab3f3708 100644
--- a/target/moxie/cpu.c
+++ b/target/moxie/cpu.c
@@ -77,14 +77,8 @@ static void moxie_cpu_initfn(Object *obj)
{
CPUState *cs = CPU(obj);
MoxieCPU *cpu = MOXIE_CPU(obj);
- static int inited;
cs->env_ptr = &cpu->env;
-
- if (tcg_enabled() && !inited) {
- inited = 1;
- moxie_translate_init();
- }
}
static ObjectClass *moxie_cpu_class_by_name(const char *cpu_model)
@@ -122,6 +116,7 @@ static void moxie_cpu_class_init(ObjectClass *oc, void *data)
cc->vmsd = &vmstate_moxie_cpu;
#endif
cc->disas_set_info = moxie_cpu_disas_set_info;
+ cc->tcg_initialize = moxie_translate_init;
}
static void moxielite_initfn(Object *obj)
diff --git a/target/moxie/translate.c b/target/moxie/translate.c
index 3cfd232558..eaf5103920 100644
--- a/target/moxie/translate.c
+++ b/target/moxie/translate.c
@@ -94,7 +94,6 @@ void moxie_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
void moxie_translate_init(void)
{
int i;
- static int done_init;
static const char * const gregnames[16] = {
"$fp", "$sp", "$r0", "$r1",
"$r2", "$r3", "$r4", "$r5",
@@ -102,9 +101,6 @@ void moxie_translate_init(void)
"$r10", "$r11", "$r12", "$r13"
};
- if (done_init) {
- return;
- }
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
tcg_ctx.tcg_env = cpu_env;
cpu_pc = tcg_global_mem_new_i32(cpu_env,
@@ -118,8 +114,6 @@ void moxie_translate_init(void)
offsetof(CPUMoxieState, cc_a), "cc_a");
cc_b = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUMoxieState, cc_b), "cc_b");
-
- done_init = 1;
}
static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index 5b02fb67ea..4742e52c78 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -69,18 +69,12 @@ static void nios2_cpu_initfn(Object *obj)
CPUState *cs = CPU(obj);
Nios2CPU *cpu = NIOS2_CPU(obj);
CPUNios2State *env = &cpu->env;
- static bool tcg_initialized;
cs->env_ptr = env;
#if !defined(CONFIG_USER_ONLY)
mmu_init(env);
#endif
-
- if (tcg_enabled() && !tcg_initialized) {
- tcg_initialized = true;
- nios2_tcg_init();
- }
}
static ObjectClass *nios2_cpu_class_by_name(const char *cpu_model)
@@ -215,6 +209,7 @@ static void nios2_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = nios2_cpu_gdb_read_register;
cc->gdb_write_register = nios2_cpu_gdb_write_register;
cc->gdb_num_core_regs = 49;
+ cc->tcg_initialize = nios2_tcg_init;
}
static const TypeInfo nios2_cpu_type_info = {
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index a6d2049684..a8db869e50 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -86,18 +86,12 @@ static void openrisc_cpu_initfn(Object *obj)
{
CPUState *cs = CPU(obj);
OpenRISCCPU *cpu = OPENRISC_CPU(obj);
- static int inited;
cs->env_ptr = &cpu->env;
#ifndef CONFIG_USER_ONLY
cpu_openrisc_mmu_init(cpu);
#endif
-
- if (tcg_enabled() && !inited) {
- inited = 1;
- openrisc_translate_init();
- }
}
/* CPU models */
@@ -169,6 +163,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
dc->vmsd = &vmstate_openrisc_cpu;
#endif
cc->gdb_num_core_regs = 32 + 3;
+ cc->tcg_initialize = openrisc_translate_init;
}
static void cpu_register(const OpenRISCCPUInfo *info)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 616cf8f50e..b61f4f0bad 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -84,10 +84,6 @@ void ppc_translate_init(void)
int i;
char* p;
size_t cpu_reg_names_size;
- static int done_init = 0;
-
- if (done_init)
- return;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
tcg_ctx.tcg_env = cpu_env;
@@ -191,8 +187,6 @@ void ppc_translate_init(void)
cpu_access_type = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUPPCState, access_type), "access_type");
-
- done_init = 1;
}
/* internal defines */
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index 7b9bf6a773..2cb58b855b 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -10499,10 +10499,6 @@ static void ppc_cpu_initfn(Object *obj)
env->sps = (env->mmu_model & POWERPC_MMU_64K) ? defsps_64k : defsps_4k;
}
#endif /* defined(TARGET_PPC64) */
-
- if (tcg_enabled()) {
- ppc_translate_init();
- }
}
static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr)
@@ -10582,6 +10578,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->virtio_is_big_endian = ppc_cpu_is_big_endian;
#endif
+ cc->tcg_initialize = ppc_translate_init;
dc->fw_name = "PowerPC,UNKNOWN";
}
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index 95f4283188..824dfd6b65 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -241,7 +241,6 @@ static void s390_cpu_initfn(Object *obj)
CPUState *cs = CPU(obj);
S390CPU *cpu = S390_CPU(obj);
CPUS390XState *env = &cpu->env;
- static bool inited;
#if !defined(CONFIG_USER_ONLY)
struct tm tm;
#endif
@@ -259,11 +258,6 @@ static void s390_cpu_initfn(Object *obj)
env->cpu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, s390x_cpu_timer, cpu);
s390_cpu_set_state(CPU_STATE_STOPPED, cpu);
#endif
-
- if (tcg_enabled() && !inited) {
- inited = true;
- s390x_translate_init();
- }
}
static void s390_cpu_finalize(Object *obj)
@@ -503,6 +497,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
#endif
#endif
cc->disas_set_info = s390_cpu_disas_set_info;
+ cc->tcg_initialize = s390x_translate_init;
cc->gdb_num_core_regs = S390_NUM_CORE_REGS;
cc->gdb_core_xml_file = "s390x-core64.xml";
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index 252440e019..89abce2472 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -258,10 +258,6 @@ static void superh_cpu_initfn(Object *obj)
cs->env_ptr = env;
env->movcal_backup_tail = &(env->movcal_backup);
-
- if (tcg_enabled()) {
- sh4_translate_init();
- }
}
static const VMStateDescription vmstate_sh_cpu = {
@@ -297,6 +293,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
cc->get_phys_page_debug = superh_cpu_get_phys_page_debug;
#endif
cc->disas_set_info = superh_cpu_disas_set_info;
+ cc->tcg_initialize = sh4_translate_init;
cc->gdb_num_core_regs = 59;
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index 8db9fba26e..b4e4fd3782 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -81,7 +81,6 @@ static TCGv cpu_flags, cpu_delayed_pc, cpu_delayed_cond;
void sh4_translate_init(void)
{
int i;
- static int done_init = 0;
static const char * const gregnames[24] = {
"R0_BANK0", "R1_BANK0", "R2_BANK0", "R3_BANK0",
"R4_BANK0", "R5_BANK0", "R6_BANK0", "R7_BANK0",
@@ -100,10 +99,6 @@ void sh4_translate_init(void)
"FPR12_BANK1", "FPR13_BANK1", "FPR14_BANK1", "FPR15_BANK1",
};
- if (done_init) {
- return;
- }
-
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
tcg_ctx.tcg_env = cpu_env;
@@ -163,8 +158,6 @@ void sh4_translate_init(void)
cpu_fregs[i] = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUSH4State, fregs[i]),
fregnames[i]);
-
- done_init = 1;
}
void superh_cpu_dump_state(CPUState *cs, FILE *f,
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index beab90f3e6..47d0927707 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -784,10 +784,6 @@ static void sparc_cpu_initfn(Object *obj)
cs->env_ptr = env;
- if (tcg_enabled()) {
- gen_intermediate_code_init(env);
- }
-
if (scc->cpu_def) {
env->def = *scc->cpu_def;
}
@@ -891,6 +887,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
cc->vmsd = &vmstate_sparc_cpu;
#endif
cc->disas_set_info = cpu_sparc_disas_set_info;
+ cc->tcg_initialize = sparc_tcg_init;
#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
cc->gdb_num_core_regs = 86;
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 83a7d8e3ee..65939693d7 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -5857,9 +5857,8 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock * tb)
#endif
}
-void gen_intermediate_code_init(CPUSPARCState *env)
+void sparc_tcg_init(void)
{
- static int inited;
static const char gregnames[32][4] = {
"g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
"o0", "o1", "o2", "o3", "o4", "o5", "o6", "o7",
@@ -5912,12 +5911,6 @@ void gen_intermediate_code_init(CPUSPARCState *env)
unsigned int i;
- /* init various static tables */
- if (inited) {
- return;
- }
- inited = 1;
-
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
tcg_ctx.tcg_env = cpu_env;
diff --git a/target/tilegx/cpu.c b/target/tilegx/cpu.c
index 7345f5a8b5..2ef8ea7daa 100644
--- a/target/tilegx/cpu.c
+++ b/target/tilegx/cpu.c
@@ -103,14 +103,8 @@ static void tilegx_cpu_initfn(Object *obj)
CPUState *cs = CPU(obj);
TileGXCPU *cpu = TILEGX_CPU(obj);
CPUTLGState *env = &cpu->env;
- static bool tcg_initialized;
cs->env_ptr = env;
-
- if (tcg_enabled() && !tcg_initialized) {
- tcg_initialized = true;
- tilegx_tcg_init();
- }
}
static void tilegx_cpu_do_interrupt(CPUState *cs)
@@ -161,6 +155,7 @@ static void tilegx_cpu_class_init(ObjectClass *oc, void *data)
cc->set_pc = tilegx_cpu_set_pc;
cc->handle_mmu_fault = tilegx_cpu_handle_mmu_fault;
cc->gdb_num_core_regs = 0;
+ cc->tcg_initialize = tilegx_tcg_init;
}
static const TypeInfo tilegx_cpu_type_info = {
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index 871eb35453..cd93806d47 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -109,10 +109,6 @@ static void tricore_cpu_initfn(Object *obj)
CPUTriCoreState *env = &cpu->env;
cs->env_ptr = env;
-
- if (tcg_enabled()) {
- tricore_tcg_init();
- }
}
static ObjectClass *tricore_cpu_class_by_name(const char *cpu_model)
@@ -182,6 +178,7 @@ static void tricore_cpu_class_init(ObjectClass *c, void *data)
cc->set_pc = tricore_cpu_set_pc;
cc->synchronize_from_tb = tricore_cpu_synchronize_from_tb;
cc->get_phys_page_attrs_debug = tricore_cpu_get_phys_page_attrs_debug;
+ cc->tcg_initialize = tricore_tcg_init;
}
static void cpu_register(const TriCoreCPUInfo *info)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 4e4198e887..b6cfbdfa9f 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -8880,10 +8880,7 @@ static void tricore_tcg_init_csfr(void)
void tricore_tcg_init(void)
{
int i;
- static int inited;
- if (inited) {
- return;
- }
+
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
tcg_ctx.tcg_env = cpu_env;
/* reg init */
diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c
index 138acc9dd8..526604ff78 100644
--- a/target/unicore32/cpu.c
+++ b/target/unicore32/cpu.c
@@ -117,7 +117,6 @@ static void uc32_cpu_initfn(Object *obj)
CPUState *cs = CPU(obj);
UniCore32CPU *cpu = UNICORE32_CPU(obj);
CPUUniCore32State *env = &cpu->env;
- static bool inited;
cs->env_ptr = env;
@@ -130,11 +129,6 @@ static void uc32_cpu_initfn(Object *obj)
#endif
tlb_flush(cs);
-
- if (tcg_enabled() && !inited) {
- inited = true;
- uc32_translate_init();
- }
}
static const VMStateDescription vmstate_uc32_cpu = {
@@ -162,6 +156,7 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *data)
#else
cc->get_phys_page_debug = uc32_cpu_get_phys_page_debug;
#endif
+ cc->tcg_initialize = uc32_translate_init;
dc->vmsd = &vmstate_uc32_cpu;
}
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index dcdc765a86..a5651e5dab 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -121,7 +121,6 @@ static void xtensa_cpu_initfn(Object *obj)
XtensaCPU *cpu = XTENSA_CPU(obj);
XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(obj);
CPUXtensaState *env = &cpu->env;
- static bool tcg_inited;
cs->env_ptr = env;
env->config = xcc->config;
@@ -131,11 +130,6 @@ static void xtensa_cpu_initfn(Object *obj)
memory_region_init_io(env->system_er, NULL, NULL, env, "er",
UINT64_C(0x100000000));
address_space_init(env->address_space_er, env->system_er, "ER");
-
- if (tcg_enabled() && !tcg_inited) {
- tcg_inited = true;
- xtensa_translate_init();
- }
}
static const VMStateDescription vmstate_xtensa_cpu = {
@@ -170,6 +164,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
cc->do_unassigned_access = xtensa_cpu_do_unassigned_access;
#endif
cc->debug_excp_handler = xtensa_breakpoint_handler;
+ cc->tcg_initialize = xtensa_translate_init;
dc->vmsd = &vmstate_xtensa_cpu;
}
--
2.13.6
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [Qemu-devel] [PULL 21/51] tcg: Use offsets not indices for TCGv_*
2017-10-25 9:34 [Qemu-devel] [PULL 00/51] tcg queued patches Richard Henderson
` (19 preceding siblings ...)
2017-10-25 9:35 ` [Qemu-devel] [PULL 20/51] qom: Introduce CPUClass.tcg_initialize Richard Henderson
@ 2017-10-25 9:35 ` Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 22/51] tcg: define CF_PARALLEL and use it for TB hashing along with CF_COUNT_MASK Richard Henderson
` (32 subsequent siblings)
53 siblings, 0 replies; 59+ messages in thread
From: Richard Henderson @ 2017-10-25 9:35 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
Using the offset of a temporary, relative to TCGContext, rather than
its index means that we don't use 0. That leaves offset 0 free for
a NULL representation without having to leave index 0 unused.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tcg.h | 64 ++++++++++++++++++++++++++++++++-------------------------------
1 file changed, 33 insertions(+), 31 deletions(-)
diff --git a/tcg/tcg.h b/tcg/tcg.h
index 8f692bc6cf..c85786fb47 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -428,14 +428,14 @@ typedef TCGv_ptr TCGv_env;
#error Unhandled TARGET_LONG_BITS value
#endif
-/* Dummy definition to avoid compiler warnings. */
-#define TCGV_UNUSED_I32(x) (x = (TCGv_i32)-1)
-#define TCGV_UNUSED_I64(x) (x = (TCGv_i64)-1)
-#define TCGV_UNUSED_PTR(x) (x = (TCGv_ptr)-1)
+/* See the comment before tcgv_i32_temp. */
+#define TCGV_UNUSED_I32(x) (x = (TCGv_i32)NULL)
+#define TCGV_UNUSED_I64(x) (x = (TCGv_i64)NULL)
+#define TCGV_UNUSED_PTR(x) (x = (TCGv_ptr)NULL)
-#define TCGV_IS_UNUSED_I32(x) ((x) == (TCGv_i32)-1)
-#define TCGV_IS_UNUSED_I64(x) ((x) == (TCGv_i64)-1)
-#define TCGV_IS_UNUSED_PTR(x) ((x) == (TCGv_ptr)-1)
+#define TCGV_IS_UNUSED_I32(x) ((x) == (TCGv_i32)NULL)
+#define TCGV_IS_UNUSED_I64(x) ((x) == (TCGv_i64)NULL)
+#define TCGV_IS_UNUSED_PTR(x) ((x) == (TCGv_ptr)NULL)
/* call flags */
/* Helper does not read globals (either directly or through an exception). It
@@ -453,8 +453,8 @@ typedef TCGv_ptr TCGv_env;
#define TCG_CALL_NO_RWG_SE (TCG_CALL_NO_RWG | TCG_CALL_NO_SE)
#define TCG_CALL_NO_WG_SE (TCG_CALL_NO_WG | TCG_CALL_NO_SE)
-/* used to align parameters */
-#define TCG_CALL_DUMMY_ARG ((TCGArg)(-1))
+/* Used to align parameters. See the comment before tcgv_i32_temp. */
+#define TCG_CALL_DUMMY_ARG ((TCGArg)0)
/* Conditions. Note that these are laid out for easy manipulation by
the functions below:
@@ -701,62 +701,64 @@ static inline size_t temp_idx(TCGTemp *ts)
static inline TCGArg temp_arg(TCGTemp *ts)
{
- return temp_idx(ts);
+ return (uintptr_t)ts;
}
static inline TCGTemp *arg_temp(TCGArg a)
{
- return a == TCG_CALL_DUMMY_ARG ? NULL : &tcg_ctx.temps[a];
+ return (TCGTemp *)(uintptr_t)a;
}
-static inline size_t arg_index(TCGArg a)
+/* Using the offset of a temporary, relative to TCGContext, rather than
+ its index means that we don't use 0. That leaves offset 0 free for
+ a NULL representation without having to leave index 0 unused. */
+static inline TCGTemp *tcgv_i32_temp(TCGv_i32 v)
{
- return a;
-}
-
-static inline TCGArg tcgv_i32_arg(TCGv_i32 t)
-{
- return (intptr_t)t;
+ uintptr_t o = (uintptr_t)v;
+ TCGTemp *t = (void *)&tcg_ctx + o;
+ tcg_debug_assert(offsetof(TCGContext, temps[temp_idx(t)]) == o);
+ return t;
}
-static inline TCGArg tcgv_i64_arg(TCGv_i64 t)
+static inline TCGTemp *tcgv_i64_temp(TCGv_i64 v)
{
- return (intptr_t)t;
+ return tcgv_i32_temp((TCGv_i32)v);
}
-static inline TCGArg tcgv_ptr_arg(TCGv_ptr t)
+static inline TCGTemp *tcgv_ptr_temp(TCGv_ptr v)
{
- return (intptr_t)t;
+ return tcgv_i32_temp((TCGv_i32)v);
}
-static inline TCGTemp *tcgv_i32_temp(TCGv_i32 t)
+static inline TCGArg tcgv_i32_arg(TCGv_i32 v)
{
- return arg_temp(tcgv_i32_arg(t));
+ return temp_arg(tcgv_i32_temp(v));
}
-static inline TCGTemp *tcgv_i64_temp(TCGv_i64 t)
+static inline TCGArg tcgv_i64_arg(TCGv_i64 v)
{
- return arg_temp(tcgv_i64_arg(t));
+ return temp_arg(tcgv_i64_temp(v));
}
-static inline TCGTemp *tcgv_ptr_temp(TCGv_ptr t)
+static inline TCGArg tcgv_ptr_arg(TCGv_ptr v)
{
- return arg_temp(tcgv_ptr_arg(t));
+ return temp_arg(tcgv_ptr_temp(v));
}
static inline TCGv_i32 temp_tcgv_i32(TCGTemp *t)
{
- return (TCGv_i32)temp_idx(t);
+ (void)temp_idx(t); /* trigger embedded assert */
+ return (TCGv_i32)((void *)t - (void *)&tcg_ctx);
}
static inline TCGv_i64 temp_tcgv_i64(TCGTemp *t)
{
- return (TCGv_i64)temp_idx(t);
+ return (TCGv_i64)temp_tcgv_i32(t);
}
static inline TCGv_ptr temp_tcgv_ptr(TCGTemp *t)
{
- return (TCGv_ptr)temp_idx(t);
+ return (TCGv_ptr)temp_tcgv_i32(t);
}
#if TCG_TARGET_REG_BITS == 32
--
2.13.6
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [Qemu-devel] [PULL 22/51] tcg: define CF_PARALLEL and use it for TB hashing along with CF_COUNT_MASK
2017-10-25 9:34 [Qemu-devel] [PULL 00/51] tcg queued patches Richard Henderson
` (20 preceding siblings ...)
2017-10-25 9:35 ` [Qemu-devel] [PULL 21/51] tcg: Use offsets not indices for TCGv_* Richard Henderson
@ 2017-10-25 9:35 ` Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 23/51] tcg: Add CPUState cflags_next_tb Richard Henderson
` (31 subsequent siblings)
53 siblings, 0 replies; 59+ messages in thread
From: Richard Henderson @ 2017-10-25 9:35 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Emilio G. Cota
From: "Emilio G. Cota" <cota@braap.org>
This will enable us to decouple code translation from the value
of parallel_cpus at any given time. It will also help us minimize
TB flushes when generating code via EXCP_ATOMIC.
Note that the declaration of parallel_cpus is brought to exec-all.h
to be able to define there the "curr_cflags" inline.
Signed-off-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/exec-all.h | 20 +++++++++++++++++++-
include/exec/tb-hash-xx.h | 9 ++++++---
include/exec/tb-hash.h | 4 ++--
include/exec/tb-lookup.h | 6 +++---
tcg/tcg.h | 1 -
accel/tcg/cpu-exec.c | 45 +++++++++++++++++++++++----------------------
accel/tcg/tcg-runtime.c | 2 +-
accel/tcg/translate-all.c | 13 +++++++++----
exec.c | 2 +-
tests/qht-bench.c | 2 +-
10 files changed, 65 insertions(+), 39 deletions(-)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 53f1835c43..352abc7450 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -325,6 +325,9 @@ struct TranslationBlock {
#define CF_USE_ICOUNT 0x20000
#define CF_IGNORE_ICOUNT 0x40000 /* Do not generate icount code */
#define CF_INVALID 0x80000 /* TB is stale. Setters must acquire tb_lock */
+#define CF_PARALLEL 0x100000 /* Generate code for a parallel context */
+/* cflags' mask for hashing/comparison */
+#define CF_HASH_MASK (CF_PARALLEL)
/* Per-vCPU dynamic tracing state used to generate this TB */
uint32_t trace_vcpu_dstate;
@@ -365,11 +368,26 @@ struct TranslationBlock {
uintptr_t jmp_list_first;
};
+extern bool parallel_cpus;
+
+/* Hide the atomic_read to make code a little easier on the eyes */
+static inline uint32_t tb_cflags(const TranslationBlock *tb)
+{
+ return atomic_read(&tb->cflags);
+}
+
+/* current cflags for hashing/comparison */
+static inline uint32_t curr_cflags(void)
+{
+ return parallel_cpus ? CF_PARALLEL : 0;
+}
+
void tb_free(TranslationBlock *tb);
void tb_flush(CPUState *cpu);
void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr);
TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc,
- target_ulong cs_base, uint32_t flags);
+ target_ulong cs_base, uint32_t flags,
+ uint32_t cf_mask);
void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr);
/* GETPC is the true target of the return instruction that we'll execute. */
diff --git a/include/exec/tb-hash-xx.h b/include/exec/tb-hash-xx.h
index 6cd3022c07..747a9a612c 100644
--- a/include/exec/tb-hash-xx.h
+++ b/include/exec/tb-hash-xx.h
@@ -48,8 +48,8 @@
* xxhash32, customized for input variables that are not guaranteed to be
* contiguous in memory.
*/
-static inline
-uint32_t tb_hash_func6(uint64_t a0, uint64_t b0, uint32_t e, uint32_t f)
+static inline uint32_t
+tb_hash_func7(uint64_t a0, uint64_t b0, uint32_t e, uint32_t f, uint32_t g)
{
uint32_t v1 = TB_HASH_XX_SEED + PRIME32_1 + PRIME32_2;
uint32_t v2 = TB_HASH_XX_SEED + PRIME32_2;
@@ -78,7 +78,7 @@ uint32_t tb_hash_func6(uint64_t a0, uint64_t b0, uint32_t e, uint32_t f)
v4 *= PRIME32_1;
h32 = rol32(v1, 1) + rol32(v2, 7) + rol32(v3, 12) + rol32(v4, 18);
- h32 += 24;
+ h32 += 28;
h32 += e * PRIME32_3;
h32 = rol32(h32, 17) * PRIME32_4;
@@ -86,6 +86,9 @@ uint32_t tb_hash_func6(uint64_t a0, uint64_t b0, uint32_t e, uint32_t f)
h32 += f * PRIME32_3;
h32 = rol32(h32, 17) * PRIME32_4;
+ h32 += g * PRIME32_3;
+ h32 = rol32(h32, 17) * PRIME32_4;
+
h32 ^= h32 >> 15;
h32 *= PRIME32_2;
h32 ^= h32 >> 13;
diff --git a/include/exec/tb-hash.h b/include/exec/tb-hash.h
index 17b5ee0edf..0526c4f678 100644
--- a/include/exec/tb-hash.h
+++ b/include/exec/tb-hash.h
@@ -59,9 +59,9 @@ static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
static inline
uint32_t tb_hash_func(tb_page_addr_t phys_pc, target_ulong pc, uint32_t flags,
- uint32_t trace_vcpu_dstate)
+ uint32_t cf_mask, uint32_t trace_vcpu_dstate)
{
- return tb_hash_func6(phys_pc, pc, flags, trace_vcpu_dstate);
+ return tb_hash_func7(phys_pc, pc, flags, cf_mask, trace_vcpu_dstate);
}
#endif
diff --git a/include/exec/tb-lookup.h b/include/exec/tb-lookup.h
index 436b6d5ecf..296138591a 100644
--- a/include/exec/tb-lookup.h
+++ b/include/exec/tb-lookup.h
@@ -21,7 +21,7 @@
/* Might cause an exception, so have a longjmp destination ready */
static inline TranslationBlock *
tb_lookup__cpu_state(CPUState *cpu, target_ulong *pc, target_ulong *cs_base,
- uint32_t *flags)
+ uint32_t *flags, uint32_t cf_mask)
{
CPUArchState *env = (CPUArchState *)cpu->env_ptr;
TranslationBlock *tb;
@@ -35,10 +35,10 @@ tb_lookup__cpu_state(CPUState *cpu, target_ulong *pc, target_ulong *cs_base,
tb->cs_base == *cs_base &&
tb->flags == *flags &&
tb->trace_vcpu_dstate == *cpu->trace_dstate &&
- !(atomic_read(&tb->cflags) & CF_INVALID))) {
+ (tb_cflags(tb) & (CF_HASH_MASK | CF_INVALID)) == cf_mask)) {
return tb;
}
- tb = tb_htable_lookup(cpu, *pc, *cs_base, *flags);
+ tb = tb_htable_lookup(cpu, *pc, *cs_base, *flags, cf_mask);
if (tb == NULL) {
return NULL;
}
diff --git a/tcg/tcg.h b/tcg/tcg.h
index c85786fb47..92d7468cec 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -690,7 +690,6 @@ struct TCGContext {
};
extern TCGContext tcg_ctx;
-extern bool parallel_cpus;
static inline size_t temp_idx(TCGTemp *ts)
{
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 363dfa208a..39ec9508d1 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -207,7 +207,8 @@ static void cpu_exec_nocache(CPUState *cpu, int max_cycles,
tb_lock();
tb = tb_gen_code(cpu, orig_tb->pc, orig_tb->cs_base, orig_tb->flags,
max_cycles | CF_NOCACHE
- | (ignore_icount ? CF_IGNORE_ICOUNT : 0));
+ | (ignore_icount ? CF_IGNORE_ICOUNT : 0)
+ | curr_cflags());
tb->orig_tb = orig_tb;
tb_unlock();
@@ -225,31 +226,27 @@ static void cpu_exec_nocache(CPUState *cpu, int max_cycles,
static void cpu_exec_step(CPUState *cpu)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- CPUArchState *env = (CPUArchState *)cpu->env_ptr;
TranslationBlock *tb;
target_ulong cs_base, pc;
uint32_t flags;
+ uint32_t cflags = 1 | CF_IGNORE_ICOUNT;
- cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
if (sigsetjmp(cpu->jmp_env, 0) == 0) {
- mmap_lock();
- tb_lock();
- tb = tb_gen_code(cpu, pc, cs_base, flags,
- 1 | CF_NOCACHE | CF_IGNORE_ICOUNT);
- tb->orig_tb = NULL;
- tb_unlock();
- mmap_unlock();
+ tb = tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags,
+ cflags & CF_HASH_MASK);
+ if (tb == NULL) {
+ mmap_lock();
+ tb_lock();
+ tb = tb_gen_code(cpu, pc, cs_base, flags, cflags);
+ tb_unlock();
+ mmap_unlock();
+ }
cc->cpu_exec_enter(cpu);
/* execute the generated code */
- trace_exec_tb_nocache(tb, pc);
+ trace_exec_tb(tb, pc);
cpu_tb_exec(cpu, tb);
cc->cpu_exec_exit(cpu);
-
- tb_lock();
- tb_phys_invalidate(tb, -1);
- tb_free(tb);
- tb_unlock();
} else {
/* We may have exited due to another problem here, so we need
* to reset any tb_locks we may have taken but didn't release.
@@ -281,6 +278,7 @@ struct tb_desc {
CPUArchState *env;
tb_page_addr_t phys_page1;
uint32_t flags;
+ uint32_t cf_mask;
uint32_t trace_vcpu_dstate;
};
@@ -294,7 +292,7 @@ static bool tb_cmp(const void *p, const void *d)
tb->cs_base == desc->cs_base &&
tb->flags == desc->flags &&
tb->trace_vcpu_dstate == desc->trace_vcpu_dstate &&
- !(atomic_read(&tb->cflags) & CF_INVALID)) {
+ (tb_cflags(tb) & (CF_HASH_MASK | CF_INVALID)) == desc->cf_mask) {
/* check next page if needed */
if (tb->page_addr[1] == -1) {
return true;
@@ -313,7 +311,8 @@ static bool tb_cmp(const void *p, const void *d)
}
TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc,
- target_ulong cs_base, uint32_t flags)
+ target_ulong cs_base, uint32_t flags,
+ uint32_t cf_mask)
{
tb_page_addr_t phys_pc;
struct tb_desc desc;
@@ -322,11 +321,12 @@ TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc,
desc.env = (CPUArchState *)cpu->env_ptr;
desc.cs_base = cs_base;
desc.flags = flags;
+ desc.cf_mask = cf_mask;
desc.trace_vcpu_dstate = *cpu->trace_dstate;
desc.pc = pc;
phys_pc = get_page_addr_code(desc.env, pc);
desc.phys_page1 = phys_pc & TARGET_PAGE_MASK;
- h = tb_hash_func(phys_pc, pc, flags, *cpu->trace_dstate);
+ h = tb_hash_func(phys_pc, pc, flags, cf_mask, *cpu->trace_dstate);
return qht_lookup(&tcg_ctx.tb_ctx.htable, tb_cmp, &desc, h);
}
@@ -373,8 +373,9 @@ static inline TranslationBlock *tb_find(CPUState *cpu,
target_ulong cs_base, pc;
uint32_t flags;
bool acquired_tb_lock = false;
+ uint32_t cf_mask = curr_cflags();
- tb = tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags);
+ tb = tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags, cf_mask);
if (tb == NULL) {
/* mmap_lock is needed by tb_gen_code, and mmap_lock must be
* taken outside tb_lock. As system emulation is currently
@@ -387,10 +388,10 @@ static inline TranslationBlock *tb_find(CPUState *cpu,
/* There's a chance that our desired tb has been translated while
* taking the locks so we check again inside the lock.
*/
- tb = tb_htable_lookup(cpu, pc, cs_base, flags);
+ tb = tb_htable_lookup(cpu, pc, cs_base, flags, cf_mask);
if (likely(tb == NULL)) {
/* if no translated code available, then translate it now */
- tb = tb_gen_code(cpu, pc, cs_base, flags, 0);
+ tb = tb_gen_code(cpu, pc, cs_base, flags, cf_mask);
}
mmap_unlock();
diff --git a/accel/tcg/tcg-runtime.c b/accel/tcg/tcg-runtime.c
index 54d89100d9..25f0cabfed 100644
--- a/accel/tcg/tcg-runtime.c
+++ b/accel/tcg/tcg-runtime.c
@@ -151,7 +151,7 @@ void *HELPER(lookup_tb_ptr)(CPUArchState *env)
target_ulong cs_base, pc;
uint32_t flags;
- tb = tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags);
+ tb = tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags, curr_cflags());
if (tb == NULL) {
return tcg_ctx.code_gen_epilogue;
}
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index 1b43deb0cd..7ad65bc705 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -1101,7 +1101,8 @@ void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr)
/* remove the TB from the hash list */
phys_pc = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK);
- h = tb_hash_func(phys_pc, tb->pc, tb->flags, tb->trace_vcpu_dstate);
+ h = tb_hash_func(phys_pc, tb->pc, tb->flags, tb->cflags & CF_HASH_MASK,
+ tb->trace_vcpu_dstate);
qht_remove(&tcg_ctx.tb_ctx.htable, tb, h);
/* remove the TB from the page list */
@@ -1245,7 +1246,8 @@ static void tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc,
}
/* add in the hash table */
- h = tb_hash_func(phys_pc, tb->pc, tb->flags, tb->trace_vcpu_dstate);
+ h = tb_hash_func(phys_pc, tb->pc, tb->flags, tb->cflags & CF_HASH_MASK,
+ tb->trace_vcpu_dstate);
qht_insert(&tcg_ctx.tb_ctx.htable, tb, h);
#ifdef CONFIG_USER_ONLY
@@ -1548,7 +1550,8 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
/* we generate a block containing just the instruction
modifying the memory. It will ensure that it cannot modify
itself */
- tb_gen_code(cpu, current_pc, current_cs_base, current_flags, 1);
+ tb_gen_code(cpu, current_pc, current_cs_base, current_flags,
+ 1 | curr_cflags());
cpu_loop_exit_noexc(cpu);
}
#endif
@@ -1666,7 +1669,8 @@ static bool tb_invalidate_phys_page(tb_page_addr_t addr, uintptr_t pc)
/* we generate a block containing just the instruction
modifying the memory. It will ensure that it cannot modify
itself */
- tb_gen_code(cpu, current_pc, current_cs_base, current_flags, 1);
+ tb_gen_code(cpu, current_pc, current_cs_base, current_flags,
+ 1 | curr_cflags());
/* tb_lock will be reset after cpu_loop_exit_noexc longjmps
* back into the cpu_exec loop. */
return true;
@@ -1810,6 +1814,7 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr)
}
cflags = n | CF_LAST_IO;
+ cflags |= curr_cflags();
pc = tb->pc;
cs_base = tb->cs_base;
flags = tb->flags;
diff --git a/exec.c b/exec.c
index de03053d32..3e0a3dae46 100644
--- a/exec.c
+++ b/exec.c
@@ -2476,7 +2476,7 @@ static void check_watchpoint(int offset, int len, MemTxAttrs attrs, int flags)
cpu_loop_exit(cpu);
} else {
cpu_get_tb_cpu_state(env, &pc, &cs_base, &cpu_flags);
- tb_gen_code(cpu, pc, cs_base, cpu_flags, 1);
+ tb_gen_code(cpu, pc, cs_base, cpu_flags, 1 | curr_cflags());
cpu_loop_exit_noexc(cpu);
}
}
diff --git a/tests/qht-bench.c b/tests/qht-bench.c
index 11c1cec766..4cabdfd62a 100644
--- a/tests/qht-bench.c
+++ b/tests/qht-bench.c
@@ -103,7 +103,7 @@ static bool is_equal(const void *obj, const void *userp)
static inline uint32_t h(unsigned long v)
{
- return tb_hash_func6(v, 0, 0, 0);
+ return tb_hash_func7(v, 0, 0, 0, 0);
}
/*
--
2.13.6
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [Qemu-devel] [PULL 23/51] tcg: Add CPUState cflags_next_tb
2017-10-25 9:34 [Qemu-devel] [PULL 00/51] tcg queued patches Richard Henderson
` (21 preceding siblings ...)
2017-10-25 9:35 ` [Qemu-devel] [PULL 22/51] tcg: define CF_PARALLEL and use it for TB hashing along with CF_COUNT_MASK Richard Henderson
@ 2017-10-25 9:35 ` Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 24/51] tcg: Include CF_COUNT_MASK in CF_HASH_MASK Richard Henderson
` (30 subsequent siblings)
53 siblings, 0 replies; 59+ messages in thread
From: Richard Henderson @ 2017-10-25 9:35 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
We were generating code during tb_invalidate_phys_page_range,
check_watchpoint, cpu_io_recompile, and (seemingly) discarding
the TB, assuming that it would magically be picked up during
the next iteration through the cpu_exec loop.
Instead, record the desired cflags in CPUState so that we request
the proper TB so that there is no more magic.
Reviewed-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/qom/cpu.h | 1 +
accel/tcg/cpu-exec.c | 21 +++++++++++++++++----
accel/tcg/translate-all.c | 36 ++++++++++--------------------------
exec.c | 7 ++-----
qom/cpu.c | 1 +
5 files changed, 31 insertions(+), 35 deletions(-)
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index df0ba86202..fa4b0c9dba 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -344,6 +344,7 @@ struct CPUState {
bool unplug;
bool crash_occurred;
bool exit_request;
+ uint32_t cflags_next_tb;
/* updates protected by BQL */
uint32_t interrupt_request;
int singlestep_enabled;
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 39ec9508d1..1c64977849 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -367,13 +367,12 @@ static inline void tb_add_jump(TranslationBlock *tb, int n,
static inline TranslationBlock *tb_find(CPUState *cpu,
TranslationBlock *last_tb,
- int tb_exit)
+ int tb_exit, uint32_t cf_mask)
{
TranslationBlock *tb;
target_ulong cs_base, pc;
uint32_t flags;
bool acquired_tb_lock = false;
- uint32_t cf_mask = curr_cflags();
tb = tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags, cf_mask);
if (tb == NULL) {
@@ -501,7 +500,7 @@ static inline bool cpu_handle_exception(CPUState *cpu, int *ret)
} else if (replay_has_exception()
&& cpu->icount_decr.u16.low + cpu->icount_extra == 0) {
/* try to cause an exception pending in the log */
- cpu_exec_nocache(cpu, 1, tb_find(cpu, NULL, 0), true);
+ cpu_exec_nocache(cpu, 1, tb_find(cpu, NULL, 0, curr_cflags()), true);
*ret = -1;
return true;
#endif
@@ -697,7 +696,21 @@ int cpu_exec(CPUState *cpu)
int tb_exit = 0;
while (!cpu_handle_interrupt(cpu, &last_tb)) {
- TranslationBlock *tb = tb_find(cpu, last_tb, tb_exit);
+ uint32_t cflags = cpu->cflags_next_tb;
+ TranslationBlock *tb;
+
+ /* When requested, use an exact setting for cflags for the next
+ execution. This is used for icount, precise smc, and stop-
+ after-access watchpoints. Since this request should never
+ have CF_INVALID set, -1 is a convenient invalid value that
+ does not require tcg headers for cpu_common_reset. */
+ if (cflags == -1) {
+ cflags = curr_cflags();
+ } else {
+ cpu->cflags_next_tb = -1;
+ }
+
+ tb = tb_find(cpu, last_tb, tb_exit, cflags);
cpu_loop_exec_tb(cpu, tb, &last_tb, &tb_exit);
/* Try to align the host and virtual clocks
if the guest is in advance */
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index 7ad65bc705..91fd6e444b 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -1463,14 +1463,12 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
int is_cpu_write_access)
{
TranslationBlock *tb, *tb_next;
-#if defined(TARGET_HAS_PRECISE_SMC)
- CPUState *cpu = current_cpu;
- CPUArchState *env = NULL;
-#endif
tb_page_addr_t tb_start, tb_end;
PageDesc *p;
int n;
#ifdef TARGET_HAS_PRECISE_SMC
+ CPUState *cpu = current_cpu;
+ CPUArchState *env = NULL;
int current_tb_not_found = is_cpu_write_access;
TranslationBlock *current_tb = NULL;
int current_tb_modified = 0;
@@ -1547,11 +1545,8 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
#endif
#ifdef TARGET_HAS_PRECISE_SMC
if (current_tb_modified) {
- /* we generate a block containing just the instruction
- modifying the memory. It will ensure that it cannot modify
- itself */
- tb_gen_code(cpu, current_pc, current_cs_base, current_flags,
- 1 | curr_cflags());
+ /* Force execution of one insn next time. */
+ cpu->cflags_next_tb = 1 | curr_cflags();
cpu_loop_exit_noexc(cpu);
}
#endif
@@ -1666,11 +1661,8 @@ static bool tb_invalidate_phys_page(tb_page_addr_t addr, uintptr_t pc)
p->first_tb = NULL;
#ifdef TARGET_HAS_PRECISE_SMC
if (current_tb_modified) {
- /* we generate a block containing just the instruction
- modifying the memory. It will ensure that it cannot modify
- itself */
- tb_gen_code(cpu, current_pc, current_cs_base, current_flags,
- 1 | curr_cflags());
+ /* Force execution of one insn next time. */
+ cpu->cflags_next_tb = 1 | curr_cflags();
/* tb_lock will be reset after cpu_loop_exit_noexc longjmps
* back into the cpu_exec loop. */
return true;
@@ -1773,9 +1765,7 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr)
CPUArchState *env = cpu->env_ptr;
#endif
TranslationBlock *tb;
- uint32_t n, cflags;
- target_ulong pc, cs_base;
- uint32_t flags;
+ uint32_t n;
tb_lock();
tb = tb_find_pc(retaddr);
@@ -1813,12 +1803,9 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr)
cpu_abort(cpu, "TB too big during recompile");
}
- cflags = n | CF_LAST_IO;
- cflags |= curr_cflags();
- pc = tb->pc;
- cs_base = tb->cs_base;
- flags = tb->flags;
- tb_phys_invalidate(tb, -1);
+ /* Adjust the execution state of the next TB. */
+ cpu->cflags_next_tb = curr_cflags() | CF_LAST_IO | n;
+
if (tb->cflags & CF_NOCACHE) {
if (tb->orig_tb) {
/* Invalidate original TB if this TB was generated in
@@ -1827,9 +1814,6 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr)
}
tb_free(tb);
}
- /* FIXME: In theory this could raise an exception. In practice
- we have already translated the block once so it's probably ok. */
- tb_gen_code(cpu, pc, cs_base, flags, cflags);
/* TODO: If env->pc != tb->pc (i.e. the faulting instruction was not
* the first in the TB) then we end up generating a whole new TB and
diff --git a/exec.c b/exec.c
index 3e0a3dae46..97a24a875e 100644
--- a/exec.c
+++ b/exec.c
@@ -2431,11 +2431,8 @@ static void check_watchpoint(int offset, int len, MemTxAttrs attrs, int flags)
{
CPUState *cpu = current_cpu;
CPUClass *cc = CPU_GET_CLASS(cpu);
- CPUArchState *env = cpu->env_ptr;
- target_ulong pc, cs_base;
target_ulong vaddr;
CPUWatchpoint *wp;
- uint32_t cpu_flags;
assert(tcg_enabled());
if (cpu->watchpoint_hit) {
@@ -2475,8 +2472,8 @@ static void check_watchpoint(int offset, int len, MemTxAttrs attrs, int flags)
cpu->exception_index = EXCP_DEBUG;
cpu_loop_exit(cpu);
} else {
- cpu_get_tb_cpu_state(env, &pc, &cs_base, &cpu_flags);
- tb_gen_code(cpu, pc, cs_base, cpu_flags, 1 | curr_cflags());
+ /* Force execution of one insn next time. */
+ cpu->cflags_next_tb = 1 | curr_cflags();
cpu_loop_exit_noexc(cpu);
}
}
diff --git a/qom/cpu.c b/qom/cpu.c
index 54c9452b1c..e42d9a7f9e 100644
--- a/qom/cpu.c
+++ b/qom/cpu.c
@@ -301,6 +301,7 @@ static void cpu_common_reset(CPUState *cpu)
cpu->can_do_io = 1;
cpu->exception_index = -1;
cpu->crash_occurred = false;
+ cpu->cflags_next_tb = -1;
if (tcg_enabled()) {
cpu_tb_jmp_cache_clear(cpu);
--
2.13.6
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [Qemu-devel] [PULL 24/51] tcg: Include CF_COUNT_MASK in CF_HASH_MASK
2017-10-25 9:34 [Qemu-devel] [PULL 00/51] tcg queued patches Richard Henderson
` (22 preceding siblings ...)
2017-10-25 9:35 ` [Qemu-devel] [PULL 23/51] tcg: Add CPUState cflags_next_tb Richard Henderson
@ 2017-10-25 9:35 ` Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 25/51] tcg: convert tb->cflags reads to tb_cflags(tb) Richard Henderson
` (29 subsequent siblings)
53 siblings, 0 replies; 59+ messages in thread
From: Richard Henderson @ 2017-10-25 9:35 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
Reviewed-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/exec-all.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 352abc7450..0fdb72bb22 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -327,7 +327,7 @@ struct TranslationBlock {
#define CF_INVALID 0x80000 /* TB is stale. Setters must acquire tb_lock */
#define CF_PARALLEL 0x100000 /* Generate code for a parallel context */
/* cflags' mask for hashing/comparison */
-#define CF_HASH_MASK (CF_PARALLEL)
+#define CF_HASH_MASK (CF_COUNT_MASK | CF_PARALLEL)
/* Per-vCPU dynamic tracing state used to generate this TB */
uint32_t trace_vcpu_dstate;
--
2.13.6
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [Qemu-devel] [PULL 25/51] tcg: convert tb->cflags reads to tb_cflags(tb)
2017-10-25 9:34 [Qemu-devel] [PULL 00/51] tcg queued patches Richard Henderson
` (23 preceding siblings ...)
2017-10-25 9:35 ` [Qemu-devel] [PULL 24/51] tcg: Include CF_COUNT_MASK in CF_HASH_MASK Richard Henderson
@ 2017-10-25 9:35 ` Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 26/51] target/arm: check CF_PARALLEL instead of parallel_cpus Richard Henderson
` (28 subsequent siblings)
53 siblings, 0 replies; 59+ messages in thread
From: Richard Henderson @ 2017-10-25 9:35 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Emilio G. Cota
From: "Emilio G. Cota" <cota@braap.org>
Convert all existing readers of tb->cflags to tb_cflags, so that we
use atomic_read and therefore avoid undefined behaviour in C11.
Note that the remaining setters/getters of the field are protected
by tb_lock, and therefore do not need conversion.
Luckily all readers access the field via 'tb->cflags' (so no foo.cflags,
bar->cflags in the code base), which makes the conversion easily
scriptable:
FILES=$(git grep 'tb->cflags' target include/exec/gen-icount.h \
accel/tcg/translator.c | cut -f1 -d':' | sort | uniq)
perl -pi -e 's/([^.>])tb->cflags/$1tb_cflags(tb)/g' $FILES
perl -pi -e 's/([a-z->.]*)(->|\.)tb->cflags/tb_cflags($1$2tb)/g' $FILES
Then manually fixed the few errors that checkpatch reported.
Compile-tested for all targets.
Suggested-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/gen-icount.h | 8 ++++----
accel/tcg/translator.c | 4 ++--
target/alpha/translate.c | 4 ++--
target/arm/translate-a64.c | 7 ++++---
target/arm/translate.c | 6 +++---
target/cris/translate.c | 6 +++---
target/hppa/translate.c | 2 +-
target/i386/translate.c | 48 +++++++++++++++++++++----------------------
target/lm32/translate.c | 14 ++++++-------
target/m68k/translate.c | 6 +++---
target/microblaze/translate.c | 6 +++---
target/mips/translate.c | 26 +++++++++++------------
target/moxie/translate.c | 2 +-
target/nios2/translate.c | 6 +++---
target/openrisc/translate.c | 6 +++---
target/ppc/translate.c | 6 +++---
target/ppc/translate_init.c | 32 ++++++++++++++---------------
target/s390x/translate.c | 8 ++++----
target/sh4/translate.c | 6 +++---
target/sparc/translate.c | 6 +++---
target/tilegx/translate.c | 2 +-
target/tricore/translate.c | 2 +-
target/unicore32/translate.c | 6 +++---
target/xtensa/translate.c | 28 ++++++++++++-------------
24 files changed, 124 insertions(+), 123 deletions(-)
diff --git a/include/exec/gen-icount.h b/include/exec/gen-icount.h
index 9b3cb14dfa..48b566c1c9 100644
--- a/include/exec/gen-icount.h
+++ b/include/exec/gen-icount.h
@@ -13,7 +13,7 @@ static inline void gen_tb_start(TranslationBlock *tb)
TCGv_i32 count, imm;
exitreq_label = gen_new_label();
- if (tb->cflags & CF_USE_ICOUNT) {
+ if (tb_cflags(tb) & CF_USE_ICOUNT) {
count = tcg_temp_local_new_i32();
} else {
count = tcg_temp_new_i32();
@@ -22,7 +22,7 @@ static inline void gen_tb_start(TranslationBlock *tb)
tcg_gen_ld_i32(count, tcg_ctx.tcg_env,
-ENV_OFFSET + offsetof(CPUState, icount_decr.u32));
- if (tb->cflags & CF_USE_ICOUNT) {
+ if (tb_cflags(tb) & CF_USE_ICOUNT) {
imm = tcg_temp_new_i32();
/* We emit a movi with a dummy immediate argument. Keep the insn index
* of the movi so that we later (when we know the actual insn count)
@@ -36,7 +36,7 @@ static inline void gen_tb_start(TranslationBlock *tb)
tcg_gen_brcondi_i32(TCG_COND_LT, count, 0, exitreq_label);
- if (tb->cflags & CF_USE_ICOUNT) {
+ if (tb_cflags(tb) & CF_USE_ICOUNT) {
tcg_gen_st16_i32(count, tcg_ctx.tcg_env,
-ENV_OFFSET + offsetof(CPUState, icount_decr.u16.low));
}
@@ -46,7 +46,7 @@ static inline void gen_tb_start(TranslationBlock *tb)
static inline void gen_tb_end(TranslationBlock *tb, int num_insns)
{
- if (tb->cflags & CF_USE_ICOUNT) {
+ if (tb_cflags(tb) & CF_USE_ICOUNT) {
/* Update the num_insn immediate parameter now that we know
* the actual insn count. */
tcg_set_insn_param(icount_start_insn_idx, 1, num_insns);
diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c
index afa3af478a..23c6602cd9 100644
--- a/accel/tcg/translator.c
+++ b/accel/tcg/translator.c
@@ -45,7 +45,7 @@ void translator_loop(const TranslatorOps *ops, DisasContextBase *db,
db->singlestep_enabled = cpu->singlestep_enabled;
/* Instruction counting */
- max_insns = db->tb->cflags & CF_COUNT_MASK;
+ max_insns = tb_cflags(db->tb) & CF_COUNT_MASK;
if (max_insns == 0) {
max_insns = CF_COUNT_MASK;
}
@@ -95,7 +95,7 @@ void translator_loop(const TranslatorOps *ops, DisasContextBase *db,
update db->pc_next and db->is_jmp to indicate what should be
done next -- either exiting this loop or locate the start of
the next instruction. */
- if (db->num_insns == max_insns && (db->tb->cflags & CF_LAST_IO)) {
+ if (db->num_insns == max_insns && (tb_cflags(db->tb) & CF_LAST_IO)) {
/* Accept I/O on the last instruction. */
gen_io_start();
ops->translate_insn(db, cpu);
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
index 3c8d1dc333..53b8c036e2 100644
--- a/target/alpha/translate.c
+++ b/target/alpha/translate.c
@@ -455,7 +455,7 @@ static bool in_superpage(DisasContext *ctx, int64_t addr)
static bool use_exit_tb(DisasContext *ctx)
{
- return ((ctx->base.tb->cflags & CF_LAST_IO)
+ return ((tb_cflags(ctx->base.tb) & CF_LAST_IO)
|| ctx->base.singlestep_enabled
|| singlestep);
}
@@ -2399,7 +2399,7 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
case 0xC000:
/* RPCC */
va = dest_gpr(ctx, ra);
- if (ctx->base.tb->cflags & CF_USE_ICOUNT) {
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
gen_helper_load_pcc(va, cpu_env);
gen_io_end();
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index a39b9d3633..e9bee8c196 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -348,7 +348,8 @@ static inline bool use_goto_tb(DisasContext *s, int n, uint64_t dest)
/* No direct tb linking with singlestep (either QEMU's or the ARM
* debug architecture kind) or deterministic io
*/
- if (s->base.singlestep_enabled || s->ss_active || (s->base.tb->cflags & CF_LAST_IO)) {
+ if (s->base.singlestep_enabled || s->ss_active ||
+ (tb_cflags(s->base.tb) & CF_LAST_IO)) {
return false;
}
@@ -1561,7 +1562,7 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
break;
}
- if ((s->base.tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) {
+ if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) {
gen_io_start();
}
@@ -1592,7 +1593,7 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
}
}
- if ((s->base.tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) {
+ if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) {
/* I/O operations must end the TB here (whether read or write) */
gen_io_end();
s->base.is_jmp = DISAS_UPDATE;
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 4da1a4cbc6..dfa547b1db 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -7704,7 +7704,7 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn)
break;
}
- if ((s->base.tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) {
+ if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) {
gen_io_start();
}
@@ -7795,7 +7795,7 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn)
}
}
- if ((s->base.tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) {
+ if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) {
/* I/O operations must end the TB here (whether read or write) */
gen_io_end();
gen_lookup_tb(s);
@@ -12253,7 +12253,7 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
- if (dc->base.tb->cflags & CF_LAST_IO && dc->condjmp) {
+ if (tb_cflags(dc->base.tb) & CF_LAST_IO && dc->condjmp) {
/* FIXME: This can theoretically happen with self-modifying code. */
cpu_abort(cpu, "IO on conditional branch instruction");
}
diff --git a/target/cris/translate.c b/target/cris/translate.c
index 55a9202777..6774acc7af 100644
--- a/target/cris/translate.c
+++ b/target/cris/translate.c
@@ -3141,7 +3141,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
num_insns = 0;
- max_insns = tb->cflags & CF_COUNT_MASK;
+ max_insns = tb_cflags(tb) & CF_COUNT_MASK;
if (max_insns == 0) {
max_insns = CF_COUNT_MASK;
}
@@ -3171,7 +3171,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
/* Pretty disas. */
LOG_DIS("%8.8x:\t", dc->pc);
- if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
+ if (num_insns == max_insns && (tb_cflags(tb) & CF_LAST_IO)) {
gen_io_start();
}
dc->clear_x = 1;
@@ -3244,7 +3244,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
npc = dc->pc;
- if (tb->cflags & CF_LAST_IO)
+ if (tb_cflags(tb) & CF_LAST_IO)
gen_io_end();
/* Force an update if the per-tb cpu state has changed. */
if (dc->is_jmp == DISAS_NEXT
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 334ee74e4c..460b4d3154 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -469,7 +469,7 @@ static DisasJumpType gen_illegal(DisasContext *ctx)
static bool use_goto_tb(DisasContext *ctx, target_ulong dest)
{
/* Suppress goto_tb in the case of single-steping and IO. */
- if ((ctx->base.tb->cflags & CF_LAST_IO) || ctx->base.singlestep_enabled) {
+ if ((tb_cflags(ctx->base.tb) & CF_LAST_IO) || ctx->base.singlestep_enabled) {
return false;
}
return true;
diff --git a/target/i386/translate.c b/target/i386/translate.c
index da13fe4d11..2e2e0dbddc 100644
--- a/target/i386/translate.c
+++ b/target/i386/translate.c
@@ -1118,7 +1118,7 @@ static void gen_bpt_io(DisasContext *s, TCGv_i32 t_port, int ot)
static inline void gen_ins(DisasContext *s, TCGMemOp ot)
{
- if (s->base.tb->cflags & CF_USE_ICOUNT) {
+ if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
}
gen_string_movl_A0_EDI(s);
@@ -1133,14 +1133,14 @@ static inline void gen_ins(DisasContext *s, TCGMemOp ot)
gen_op_movl_T0_Dshift(ot);
gen_op_add_reg_T0(s->aflag, R_EDI);
gen_bpt_io(s, cpu_tmp2_i32, ot);
- if (s->base.tb->cflags & CF_USE_ICOUNT) {
+ if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
gen_io_end();
}
}
static inline void gen_outs(DisasContext *s, TCGMemOp ot)
{
- if (s->base.tb->cflags & CF_USE_ICOUNT) {
+ if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
}
gen_string_movl_A0_ESI(s);
@@ -1153,7 +1153,7 @@ static inline void gen_outs(DisasContext *s, TCGMemOp ot)
gen_op_movl_T0_Dshift(ot);
gen_op_add_reg_T0(s->aflag, R_ESI);
gen_bpt_io(s, cpu_tmp2_i32, ot);
- if (s->base.tb->cflags & CF_USE_ICOUNT) {
+ if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
gen_io_end();
}
}
@@ -6340,7 +6340,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
gen_repz_ins(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
} else {
gen_ins(s, ot);
- if (s->base.tb->cflags & CF_USE_ICOUNT) {
+ if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
gen_jmp(s, s->pc - s->cs_base);
}
}
@@ -6355,7 +6355,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
gen_repz_outs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
} else {
gen_outs(s, ot);
- if (s->base.tb->cflags & CF_USE_ICOUNT) {
+ if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
gen_jmp(s, s->pc - s->cs_base);
}
}
@@ -6371,14 +6371,14 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
tcg_gen_movi_tl(cpu_T0, val);
gen_check_io(s, ot, pc_start - s->cs_base,
SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes));
- if (s->base.tb->cflags & CF_USE_ICOUNT) {
+ if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
}
tcg_gen_movi_i32(cpu_tmp2_i32, val);
gen_helper_in_func(ot, cpu_T1, cpu_tmp2_i32);
gen_op_mov_reg_v(ot, R_EAX, cpu_T1);
gen_bpt_io(s, cpu_tmp2_i32, ot);
- if (s->base.tb->cflags & CF_USE_ICOUNT) {
+ if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
gen_io_end();
gen_jmp(s, s->pc - s->cs_base);
}
@@ -6392,14 +6392,14 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
svm_is_rep(prefixes));
gen_op_mov_v_reg(ot, cpu_T1, R_EAX);
- if (s->base.tb->cflags & CF_USE_ICOUNT) {
+ if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
}
tcg_gen_movi_i32(cpu_tmp2_i32, val);
tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T1);
gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32);
gen_bpt_io(s, cpu_tmp2_i32, ot);
- if (s->base.tb->cflags & CF_USE_ICOUNT) {
+ if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
gen_io_end();
gen_jmp(s, s->pc - s->cs_base);
}
@@ -6410,14 +6410,14 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
tcg_gen_ext16u_tl(cpu_T0, cpu_regs[R_EDX]);
gen_check_io(s, ot, pc_start - s->cs_base,
SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes));
- if (s->base.tb->cflags & CF_USE_ICOUNT) {
+ if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
}
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T0);
gen_helper_in_func(ot, cpu_T1, cpu_tmp2_i32);
gen_op_mov_reg_v(ot, R_EAX, cpu_T1);
gen_bpt_io(s, cpu_tmp2_i32, ot);
- if (s->base.tb->cflags & CF_USE_ICOUNT) {
+ if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
gen_io_end();
gen_jmp(s, s->pc - s->cs_base);
}
@@ -6430,14 +6430,14 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
svm_is_rep(prefixes));
gen_op_mov_v_reg(ot, cpu_T1, R_EAX);
- if (s->base.tb->cflags & CF_USE_ICOUNT) {
+ if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
}
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T0);
tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T1);
gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32);
gen_bpt_io(s, cpu_tmp2_i32, ot);
- if (s->base.tb->cflags & CF_USE_ICOUNT) {
+ if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
gen_io_end();
gen_jmp(s, s->pc - s->cs_base);
}
@@ -7143,11 +7143,11 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
case 0x131: /* rdtsc */
gen_update_cc_op(s);
gen_jmp_im(pc_start - s->cs_base);
- if (s->base.tb->cflags & CF_USE_ICOUNT) {
+ if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
}
gen_helper_rdtsc(cpu_env);
- if (s->base.tb->cflags & CF_USE_ICOUNT) {
+ if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
gen_io_end();
gen_jmp(s, s->pc - s->cs_base);
}
@@ -7602,11 +7602,11 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
}
gen_update_cc_op(s);
gen_jmp_im(pc_start - s->cs_base);
- if (s->base.tb->cflags & CF_USE_ICOUNT) {
+ if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
}
gen_helper_rdtscp(cpu_env);
- if (s->base.tb->cflags & CF_USE_ICOUNT) {
+ if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
gen_io_end();
gen_jmp(s, s->pc - s->cs_base);
}
@@ -7971,24 +7971,24 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
gen_update_cc_op(s);
gen_jmp_im(pc_start - s->cs_base);
if (b & 2) {
- if (s->base.tb->cflags & CF_USE_ICOUNT) {
+ if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
}
gen_op_mov_v_reg(ot, cpu_T0, rm);
gen_helper_write_crN(cpu_env, tcg_const_i32(reg),
cpu_T0);
- if (s->base.tb->cflags & CF_USE_ICOUNT) {
+ if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
gen_io_end();
}
gen_jmp_im(s->pc - s->cs_base);
gen_eob(s);
} else {
- if (s->base.tb->cflags & CF_USE_ICOUNT) {
+ if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
}
gen_helper_read_crN(cpu_T0, cpu_env, tcg_const_i32(reg));
gen_op_mov_reg_v(ot, rm, cpu_T0);
- if (s->base.tb->cflags & CF_USE_ICOUNT) {
+ if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
gen_io_end();
}
}
@@ -8452,7 +8452,7 @@ static int i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu,
record/replay modes and there will always be an
additional step for ecx=0 when icount is enabled.
*/
- dc->repz_opt = !dc->jmp_opt && !(dc->base.tb->cflags & CF_USE_ICOUNT);
+ dc->repz_opt = !dc->jmp_opt && !(tb_cflags(dc->base.tb) & CF_USE_ICOUNT);
#if 0
/* check addseg logic */
if (!dc->addseg && (dc->vm86 || !dc->pe || !dc->code32))
@@ -8518,7 +8518,7 @@ static void i386_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
the flag and abort the translation to give the irqs a
chance to happen */
dc->base.is_jmp = DISAS_TOO_MANY;
- } else if ((dc->base.tb->cflags & CF_USE_ICOUNT)
+ } else if ((tb_cflags(dc->base.tb) & CF_USE_ICOUNT)
&& ((dc->base.pc_next & TARGET_PAGE_MASK)
!= ((dc->base.pc_next + TARGET_MAX_INSN_SIZE - 1)
& TARGET_PAGE_MASK)
diff --git a/target/lm32/translate.c b/target/lm32/translate.c
index 65bc9c0bf6..d4a2e00165 100644
--- a/target/lm32/translate.c
+++ b/target/lm32/translate.c
@@ -880,24 +880,24 @@ static void dec_wcsr(DisasContext *dc)
break;
case CSR_IM:
/* mark as an io operation because it could cause an interrupt */
- if (dc->tb->cflags & CF_USE_ICOUNT) {
+ if (tb_cflags(dc->tb) & CF_USE_ICOUNT) {
gen_io_start();
}
gen_helper_wcsr_im(cpu_env, cpu_R[dc->r1]);
tcg_gen_movi_tl(cpu_pc, dc->pc + 4);
- if (dc->tb->cflags & CF_USE_ICOUNT) {
+ if (tb_cflags(dc->tb) & CF_USE_ICOUNT) {
gen_io_end();
}
dc->is_jmp = DISAS_UPDATE;
break;
case CSR_IP:
/* mark as an io operation because it could cause an interrupt */
- if (dc->tb->cflags & CF_USE_ICOUNT) {
+ if (tb_cflags(dc->tb) & CF_USE_ICOUNT) {
gen_io_start();
}
gen_helper_wcsr_ip(cpu_env, cpu_R[dc->r1]);
tcg_gen_movi_tl(cpu_pc, dc->pc + 4);
- if (dc->tb->cflags & CF_USE_ICOUNT) {
+ if (tb_cflags(dc->tb) & CF_USE_ICOUNT) {
gen_io_end();
}
dc->is_jmp = DISAS_UPDATE;
@@ -1078,7 +1078,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
num_insns = 0;
- max_insns = tb->cflags & CF_COUNT_MASK;
+ max_insns = tb_cflags(tb) & CF_COUNT_MASK;
if (max_insns == 0) {
max_insns = CF_COUNT_MASK;
}
@@ -1106,7 +1106,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
/* Pretty disas. */
LOG_DIS("%8.8x:\t", dc->pc);
- if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
+ if (num_insns == max_insns && (tb_cflags(tb) & CF_LAST_IO)) {
gen_io_start();
}
@@ -1119,7 +1119,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
&& (dc->pc < next_page_start)
&& num_insns < max_insns);
- if (tb->cflags & CF_LAST_IO) {
+ if (tb_cflags(tb) & CF_LAST_IO) {
gen_io_end();
}
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index 63b1552669..fdc26268d0 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -5547,7 +5547,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
dc->done_mac = 0;
dc->writeback_mask = 0;
num_insns = 0;
- max_insns = tb->cflags & CF_COUNT_MASK;
+ max_insns = tb_cflags(tb) & CF_COUNT_MASK;
if (max_insns == 0) {
max_insns = CF_COUNT_MASK;
}
@@ -5573,7 +5573,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
break;
}
- if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
+ if (num_insns == max_insns && (tb_cflags(tb) & CF_LAST_IO)) {
gen_io_start();
}
@@ -5585,7 +5585,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
(pc_offset) < (TARGET_PAGE_SIZE - 32) &&
num_insns < max_insns);
- if (tb->cflags & CF_LAST_IO)
+ if (tb_cflags(tb) & CF_LAST_IO)
gen_io_end();
if (unlikely(cs->singlestep_enabled)) {
/* Make sure the pc is updated, and raise a debug exception. */
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 067b0878d6..c70a2d6644 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -1666,7 +1666,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
num_insns = 0;
- max_insns = tb->cflags & CF_COUNT_MASK;
+ max_insns = tb_cflags(tb) & CF_COUNT_MASK;
if (max_insns == 0) {
max_insns = CF_COUNT_MASK;
}
@@ -1701,7 +1701,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
/* Pretty disas. */
LOG_DIS("%8.8x:\t", dc->pc);
- if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
+ if (num_insns == max_insns && (tb_cflags(tb) & CF_LAST_IO)) {
gen_io_start();
}
@@ -1763,7 +1763,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
npc = dc->jmp_pc;
}
- if (tb->cflags & CF_LAST_IO)
+ if (tb_cflags(tb) & CF_LAST_IO)
gen_io_end();
/* Force an update if the per-tb cpu state has changed. */
if (dc->is_jmp == DISAS_NEXT
diff --git a/target/mips/translate.c b/target/mips/translate.c
index ef07fa827e..aadffbec39 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -5327,11 +5327,11 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
/* Mark as an IO operation because we read the time. */
- if (ctx->tb->cflags & CF_USE_ICOUNT) {
+ if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) {
gen_io_start();
}
gen_helper_mfc0_count(arg, cpu_env);
- if (ctx->tb->cflags & CF_USE_ICOUNT) {
+ if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) {
gen_io_end();
}
/* Break the TB to be able to take timer interrupts immediately
@@ -5734,7 +5734,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
if (sel != 0)
check_insn(ctx, ISA_MIPS32);
- if (ctx->tb->cflags & CF_USE_ICOUNT) {
+ if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) {
gen_io_start();
}
@@ -6401,7 +6401,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
trace_mips_translate_c0("mtc0", rn, reg, sel);
/* For simplicity assume that all writes can cause interrupts. */
- if (ctx->tb->cflags & CF_USE_ICOUNT) {
+ if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) {
gen_io_end();
/* BS_STOP isn't sufficient, we need to ensure we break out of
* translated code to check for pending interrupts. */
@@ -6679,11 +6679,11 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
/* Mark as an IO operation because we read the time. */
- if (ctx->tb->cflags & CF_USE_ICOUNT) {
+ if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) {
gen_io_start();
}
gen_helper_mfc0_count(arg, cpu_env);
- if (ctx->tb->cflags & CF_USE_ICOUNT) {
+ if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) {
gen_io_end();
}
/* Break the TB to be able to take timer interrupts immediately
@@ -7072,7 +7072,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
if (sel != 0)
check_insn(ctx, ISA_MIPS64);
- if (ctx->tb->cflags & CF_USE_ICOUNT) {
+ if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) {
gen_io_start();
}
@@ -7727,7 +7727,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
trace_mips_translate_c0("dmtc0", rn, reg, sel);
/* For simplicity assume that all writes can cause interrupts. */
- if (ctx->tb->cflags & CF_USE_ICOUNT) {
+ if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) {
gen_io_end();
/* BS_STOP isn't sufficient, we need to ensure we break out of
* translated code to check for pending interrupts. */
@@ -10756,11 +10756,11 @@ static void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel)
gen_store_gpr(t0, rt);
break;
case 2:
- if (ctx->tb->cflags & CF_USE_ICOUNT) {
+ if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) {
gen_io_start();
}
gen_helper_rdhwr_cc(t0, cpu_env);
- if (ctx->tb->cflags & CF_USE_ICOUNT) {
+ if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) {
gen_io_end();
}
gen_store_gpr(t0, rt);
@@ -20248,7 +20248,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
ctx.default_tcg_memop_mask = (ctx.insn_flags & ISA_MIPS32R6) ?
MO_UNALN : MO_ALIGN;
num_insns = 0;
- max_insns = tb->cflags & CF_COUNT_MASK;
+ max_insns = tb_cflags(tb) & CF_COUNT_MASK;
if (max_insns == 0) {
max_insns = CF_COUNT_MASK;
}
@@ -20274,7 +20274,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
goto done_generating;
}
- if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
+ if (num_insns == max_insns && (tb_cflags(tb) & CF_LAST_IO)) {
gen_io_start();
}
@@ -20335,7 +20335,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
if (singlestep)
break;
}
- if (tb->cflags & CF_LAST_IO) {
+ if (tb_cflags(tb) & CF_LAST_IO) {
gen_io_end();
}
if (cs->singlestep_enabled && ctx.bstate != BS_BRANCH) {
diff --git a/target/moxie/translate.c b/target/moxie/translate.c
index eaf5103920..3f1e609028 100644
--- a/target/moxie/translate.c
+++ b/target/moxie/translate.c
@@ -832,7 +832,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
ctx.singlestep_enabled = 0;
ctx.bstate = BS_NONE;
num_insns = 0;
- max_insns = tb->cflags & CF_COUNT_MASK;
+ max_insns = tb_cflags(tb) & CF_COUNT_MASK;
if (max_insns == 0) {
max_insns = CF_COUNT_MASK;
}
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
index 54fbe898df..d33e365892 100644
--- a/target/nios2/translate.c
+++ b/target/nios2/translate.c
@@ -827,7 +827,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
max_insns = 1;
} else {
int page_insns = (TARGET_PAGE_SIZE - (tb->pc & TARGET_PAGE_MASK)) / 4;
- max_insns = tb->cflags & CF_COUNT_MASK;
+ max_insns = tb_cflags(tb) & CF_COUNT_MASK;
if (max_insns == 0) {
max_insns = CF_COUNT_MASK;
}
@@ -854,7 +854,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
break;
}
- if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
+ if (num_insns == max_insns && (tb_cflags(tb) & CF_LAST_IO)) {
gen_io_start();
}
@@ -871,7 +871,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
!tcg_op_buf_full() &&
num_insns < max_insns);
- if (tb->cflags & CF_LAST_IO) {
+ if (tb_cflags(tb) & CF_LAST_IO) {
gen_io_end();
}
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index 112db1ad0f..666d050650 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -1546,7 +1546,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
num_insns = 0;
- max_insns = tb->cflags & CF_COUNT_MASK;
+ max_insns = tb_cflags(tb) & CF_COUNT_MASK;
if (max_insns == 0) {
max_insns = CF_COUNT_MASK;
@@ -1589,7 +1589,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
break;
}
- if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
+ if (num_insns == max_insns && (tb_cflags(tb) & CF_LAST_IO)) {
gen_io_start();
}
disas_openrisc_insn(dc, cpu);
@@ -1612,7 +1612,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
&& (dc->pc < next_page_start)
&& num_insns < max_insns);
- if (tb->cflags & CF_LAST_IO) {
+ if (tb_cflags(tb) & CF_LAST_IO) {
gen_io_end();
}
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index b61f4f0bad..ac5b8ea9a5 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -7273,7 +7273,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
msr_se = 1;
#endif
num_insns = 0;
- max_insns = tb->cflags & CF_COUNT_MASK;
+ max_insns = tb_cflags(tb) & CF_COUNT_MASK;
if (max_insns == 0) {
max_insns = CF_COUNT_MASK;
}
@@ -7301,7 +7301,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
LOG_DISAS("----------------\n");
LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
ctx.nip, ctx.mem_idx, (int)msr_ir);
- if (num_insns == max_insns && (tb->cflags & CF_LAST_IO))
+ if (num_insns == max_insns && (tb_cflags(tb) & CF_LAST_IO))
gen_io_start();
if (unlikely(need_byteswap(&ctx))) {
ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
@@ -7382,7 +7382,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
exit(1);
}
}
- if (tb->cflags & CF_LAST_IO)
+ if (tb_cflags(tb) & CF_LAST_IO)
gen_io_end();
if (ctx.exception == POWERPC_EXCP_NONE) {
gen_goto_tb(&ctx, 0, ctx.nip);
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index 2cb58b855b..13436e4760 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -176,11 +176,11 @@ static void spr_write_ureg(DisasContext *ctx, int sprn, int gprn)
#if !defined(CONFIG_USER_ONLY)
static void spr_read_decr(DisasContext *ctx, int gprn, int sprn)
{
- if (ctx->tb->cflags & CF_USE_ICOUNT) {
+ if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) {
gen_io_start();
}
gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
- if (ctx->tb->cflags & CF_USE_ICOUNT) {
+ if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) {
gen_io_end();
gen_stop_exception(ctx);
}
@@ -188,11 +188,11 @@ static void spr_read_decr(DisasContext *ctx, int gprn, int sprn)
static void spr_write_decr(DisasContext *ctx, int sprn, int gprn)
{
- if (ctx->tb->cflags & CF_USE_ICOUNT) {
+ if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) {
gen_io_start();
}
gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
- if (ctx->tb->cflags & CF_USE_ICOUNT) {
+ if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) {
gen_io_end();
gen_stop_exception(ctx);
}
@@ -203,11 +203,11 @@ static void spr_write_decr(DisasContext *ctx, int sprn, int gprn)
/* Time base */
static void spr_read_tbl(DisasContext *ctx, int gprn, int sprn)
{
- if (ctx->tb->cflags & CF_USE_ICOUNT) {
+ if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) {
gen_io_start();
}
gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
- if (ctx->tb->cflags & CF_USE_ICOUNT) {
+ if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) {
gen_io_end();
gen_stop_exception(ctx);
}
@@ -215,11 +215,11 @@ static void spr_read_tbl(DisasContext *ctx, int gprn, int sprn)
static void spr_read_tbu(DisasContext *ctx, int gprn, int sprn)
{
- if (ctx->tb->cflags & CF_USE_ICOUNT) {
+ if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) {
gen_io_start();
}
gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
- if (ctx->tb->cflags & CF_USE_ICOUNT) {
+ if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) {
gen_io_end();
gen_stop_exception(ctx);
}
@@ -240,11 +240,11 @@ static void spr_read_atbu(DisasContext *ctx, int gprn, int sprn)
#if !defined(CONFIG_USER_ONLY)
static void spr_write_tbl(DisasContext *ctx, int sprn, int gprn)
{
- if (ctx->tb->cflags & CF_USE_ICOUNT) {
+ if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) {
gen_io_start();
}
gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
- if (ctx->tb->cflags & CF_USE_ICOUNT) {
+ if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) {
gen_io_end();
gen_stop_exception(ctx);
}
@@ -252,11 +252,11 @@ static void spr_write_tbl(DisasContext *ctx, int sprn, int gprn)
static void spr_write_tbu(DisasContext *ctx, int sprn, int gprn)
{
- if (ctx->tb->cflags & CF_USE_ICOUNT) {
+ if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) {
gen_io_start();
}
gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
- if (ctx->tb->cflags & CF_USE_ICOUNT) {
+ if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) {
gen_io_end();
gen_stop_exception(ctx);
}
@@ -284,11 +284,11 @@ static void spr_read_purr(DisasContext *ctx, int gprn, int sprn)
/* HDECR */
static void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn)
{
- if (ctx->tb->cflags & CF_USE_ICOUNT) {
+ if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) {
gen_io_start();
}
gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env);
- if (ctx->tb->cflags & CF_USE_ICOUNT) {
+ if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) {
gen_io_end();
gen_stop_exception(ctx);
}
@@ -296,11 +296,11 @@ static void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn)
static void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn)
{
- if (ctx->tb->cflags & CF_USE_ICOUNT) {
+ if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) {
gen_io_start();
}
gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]);
- if (ctx->tb->cflags & CF_USE_ICOUNT) {
+ if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) {
gen_io_end();
gen_stop_exception(ctx);
}
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index 6ecf764a98..d589fb2459 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -554,7 +554,7 @@ static void gen_op_calc_cc(DisasContext *s)
static bool use_exit_tb(DisasContext *s)
{
return (s->singlestep_enabled ||
- (s->tb->cflags & CF_LAST_IO) ||
+ (tb_cflags(s->tb) & CF_LAST_IO) ||
(s->tb->flags & FLAG_MASK_PER));
}
@@ -5883,7 +5883,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
num_insns = 0;
- max_insns = tb->cflags & CF_COUNT_MASK;
+ max_insns = tb_cflags(tb) & CF_COUNT_MASK;
if (max_insns == 0) {
max_insns = CF_COUNT_MASK;
}
@@ -5908,7 +5908,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
break;
}
- if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
+ if (num_insns == max_insns && (tb_cflags(tb) & CF_LAST_IO)) {
gen_io_start();
}
@@ -5927,7 +5927,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
}
} while (status == NO_EXIT);
- if (tb->cflags & CF_LAST_IO) {
+ if (tb_cflags(tb) & CF_LAST_IO) {
gen_io_end();
}
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index b4e4fd3782..33176c9926 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -2248,7 +2248,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
(ctx.tbflags & (1 << SR_RB))) * 0x10;
ctx.fbank = ctx.tbflags & FPSCR_FR ? 0x10 : 0;
- max_insns = tb->cflags & CF_COUNT_MASK;
+ max_insns = tb_cflags(tb) & CF_COUNT_MASK;
if (max_insns == 0) {
max_insns = CF_COUNT_MASK;
}
@@ -2292,7 +2292,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
break;
}
- if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
+ if (num_insns == max_insns && (tb_cflags(tb) & CF_LAST_IO)) {
gen_io_start();
}
@@ -2300,7 +2300,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
decode_opc(&ctx);
ctx.pc += 2;
}
- if (tb->cflags & CF_LAST_IO) {
+ if (tb_cflags(tb) & CF_LAST_IO) {
gen_io_end();
}
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 65939693d7..f2b5cdbf34 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -5767,7 +5767,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock * tb)
#endif
num_insns = 0;
- max_insns = tb->cflags & CF_COUNT_MASK;
+ max_insns = tb_cflags(tb) & CF_COUNT_MASK;
if (max_insns == 0) {
max_insns = CF_COUNT_MASK;
}
@@ -5796,7 +5796,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock * tb)
goto exit_gen_loop;
}
- if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
+ if (num_insns == max_insns && (tb_cflags(tb) & CF_LAST_IO)) {
gen_io_start();
}
@@ -5823,7 +5823,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock * tb)
num_insns < max_insns);
exit_gen_loop:
- if (tb->cflags & CF_LAST_IO) {
+ if (tb_cflags(tb) & CF_LAST_IO) {
gen_io_end();
}
if (!dc->is_br) {
diff --git a/target/tilegx/translate.c b/target/tilegx/translate.c
index ace2830a84..5cd84f6b25 100644
--- a/target/tilegx/translate.c
+++ b/target/tilegx/translate.c
@@ -2378,7 +2378,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
uint64_t pc_start = tb->pc;
uint64_t next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
int num_insns = 0;
- int max_insns = tb->cflags & CF_COUNT_MASK;
+ int max_insns = tb_cflags(tb) & CF_COUNT_MASK;
dc->pc = pc_start;
dc->mmuidx = 0;
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index b6cfbdfa9f..042c0e69bc 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -8790,7 +8790,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
int num_insns, max_insns;
num_insns = 0;
- max_insns = tb->cflags & CF_COUNT_MASK;
+ max_insns = tb_cflags(tb) & CF_COUNT_MASK;
if (max_insns == 0) {
max_insns = CF_COUNT_MASK;
}
diff --git a/target/unicore32/translate.c b/target/unicore32/translate.c
index 6c094d59d7..d717de0335 100644
--- a/target/unicore32/translate.c
+++ b/target/unicore32/translate.c
@@ -1900,7 +1900,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
cpu_F1d = tcg_temp_new_i64();
next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
num_insns = 0;
- max_insns = tb->cflags & CF_COUNT_MASK;
+ max_insns = tb_cflags(tb) & CF_COUNT_MASK;
if (max_insns == 0) {
max_insns = CF_COUNT_MASK;
}
@@ -1933,7 +1933,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
goto done_generating;
}
- if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
+ if (num_insns == max_insns && (tb_cflags(tb) & CF_LAST_IO)) {
gen_io_start();
}
@@ -1958,7 +1958,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
dc->pc < next_page_start &&
num_insns < max_insns);
- if (tb->cflags & CF_LAST_IO) {
+ if (tb_cflags(tb) & CF_LAST_IO) {
if (dc->condjmp) {
/* FIXME: This can theoretically happen with self-modifying
code. */
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index d7bf07e8e6..f62319eddd 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -517,12 +517,12 @@ static bool gen_check_sr(DisasContext *dc, uint32_t sr, unsigned access)
static bool gen_rsr_ccount(DisasContext *dc, TCGv_i32 d, uint32_t sr)
{
- if (dc->tb->cflags & CF_USE_ICOUNT) {
+ if (tb_cflags(dc->tb) & CF_USE_ICOUNT) {
gen_io_start();
}
gen_helper_update_ccount(cpu_env);
tcg_gen_mov_i32(d, cpu_SR[sr]);
- if (dc->tb->cflags & CF_USE_ICOUNT) {
+ if (tb_cflags(dc->tb) & CF_USE_ICOUNT) {
gen_io_end();
return true;
}
@@ -702,11 +702,11 @@ static bool gen_wsr_cpenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
static void gen_check_interrupts(DisasContext *dc)
{
- if (dc->tb->cflags & CF_USE_ICOUNT) {
+ if (tb_cflags(dc->tb) & CF_USE_ICOUNT) {
gen_io_start();
}
gen_helper_check_interrupts(cpu_env);
- if (dc->tb->cflags & CF_USE_ICOUNT) {
+ if (tb_cflags(dc->tb) & CF_USE_ICOUNT) {
gen_io_end();
}
}
@@ -760,11 +760,11 @@ static bool gen_wsr_ps(DisasContext *dc, uint32_t sr, TCGv_i32 v)
static bool gen_wsr_ccount(DisasContext *dc, uint32_t sr, TCGv_i32 v)
{
- if (dc->tb->cflags & CF_USE_ICOUNT) {
+ if (tb_cflags(dc->tb) & CF_USE_ICOUNT) {
gen_io_start();
}
gen_helper_wsr_ccount(cpu_env, v);
- if (dc->tb->cflags & CF_USE_ICOUNT) {
+ if (tb_cflags(dc->tb) & CF_USE_ICOUNT) {
gen_io_end();
gen_jumpi_check_loop_end(dc, 0);
return true;
@@ -801,11 +801,11 @@ static bool gen_wsr_ccompare(DisasContext *dc, uint32_t sr, TCGv_i32 v)
tcg_gen_mov_i32(cpu_SR[sr], v);
tcg_gen_andi_i32(cpu_SR[INTSET], cpu_SR[INTSET], ~int_bit);
- if (dc->tb->cflags & CF_USE_ICOUNT) {
+ if (tb_cflags(dc->tb) & CF_USE_ICOUNT) {
gen_io_start();
}
gen_helper_update_ccompare(cpu_env, tmp);
- if (dc->tb->cflags & CF_USE_ICOUNT) {
+ if (tb_cflags(dc->tb) & CF_USE_ICOUNT) {
gen_io_end();
gen_jumpi_check_loop_end(dc, 0);
ret = true;
@@ -900,11 +900,11 @@ static void gen_waiti(DisasContext *dc, uint32_t imm4)
TCGv_i32 pc = tcg_const_i32(dc->next_pc);
TCGv_i32 intlevel = tcg_const_i32(imm4);
- if (dc->tb->cflags & CF_USE_ICOUNT) {
+ if (tb_cflags(dc->tb) & CF_USE_ICOUNT) {
gen_io_start();
}
gen_helper_waiti(cpu_env, pc, intlevel);
- if (dc->tb->cflags & CF_USE_ICOUNT) {
+ if (tb_cflags(dc->tb) & CF_USE_ICOUNT) {
gen_io_end();
}
tcg_temp_free(pc);
@@ -3126,7 +3126,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
CPUXtensaState *env = cs->env_ptr;
DisasContext dc;
int insn_count = 0;
- int max_insns = tb->cflags & CF_COUNT_MASK;
+ int max_insns = tb_cflags(tb) & CF_COUNT_MASK;
uint32_t pc_start = tb->pc;
uint32_t next_page_start =
(pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
@@ -3162,7 +3162,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
gen_tb_start(tb);
- if ((tb->cflags & CF_USE_ICOUNT) &&
+ if ((tb_cflags(tb) & CF_USE_ICOUNT) &&
(tb->flags & XTENSA_TBFLAG_YIELD)) {
tcg_gen_insn_start(dc.pc);
++insn_count;
@@ -3194,7 +3194,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
break;
}
- if (insn_count == max_insns && (tb->cflags & CF_LAST_IO)) {
+ if (insn_count == max_insns && (tb_cflags(tb) & CF_LAST_IO)) {
gen_io_start();
}
@@ -3235,7 +3235,7 @@ done:
tcg_temp_free(dc.next_icount);
}
- if (tb->cflags & CF_LAST_IO) {
+ if (tb_cflags(tb) & CF_LAST_IO) {
gen_io_end();
}
--
2.13.6
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [Qemu-devel] [PULL 26/51] target/arm: check CF_PARALLEL instead of parallel_cpus
2017-10-25 9:34 [Qemu-devel] [PULL 00/51] tcg queued patches Richard Henderson
` (24 preceding siblings ...)
2017-10-25 9:35 ` [Qemu-devel] [PULL 25/51] tcg: convert tb->cflags reads to tb_cflags(tb) Richard Henderson
@ 2017-10-25 9:35 ` Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 27/51] target/hppa: " Richard Henderson
` (27 subsequent siblings)
53 siblings, 0 replies; 59+ messages in thread
From: Richard Henderson @ 2017-10-25 9:35 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Emilio G. Cota
From: "Emilio G. Cota" <cota@braap.org>
Thereby decoupling the resulting translated code from the current state
of the system.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper-a64.h | 4 ++++
target/arm/helper-a64.c | 38 ++++++++++++++++++++++++++++++++------
target/arm/op_helper.c | 7 -------
target/arm/translate-a64.c | 31 +++++++++++++++++++++++++------
target/arm/translate.c | 9 +++++++--
5 files changed, 68 insertions(+), 21 deletions(-)
diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
index 6f9eaba533..85d86741db 100644
--- a/target/arm/helper-a64.h
+++ b/target/arm/helper-a64.h
@@ -43,4 +43,8 @@ DEF_HELPER_FLAGS_2(fcvtx_f64_to_f32, TCG_CALL_NO_RWG, f32, f64, env)
DEF_HELPER_FLAGS_3(crc32_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32)
DEF_HELPER_FLAGS_3(crc32c_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32)
DEF_HELPER_FLAGS_4(paired_cmpxchg64_le, TCG_CALL_NO_WG, i64, env, i64, i64, i64)
+DEF_HELPER_FLAGS_4(paired_cmpxchg64_le_parallel, TCG_CALL_NO_WG,
+ i64, env, i64, i64, i64)
DEF_HELPER_FLAGS_4(paired_cmpxchg64_be, TCG_CALL_NO_WG, i64, env, i64, i64, i64)
+DEF_HELPER_FLAGS_4(paired_cmpxchg64_be_parallel, TCG_CALL_NO_WG,
+ i64, env, i64, i64, i64)
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index d9df82cff5..d0e435ca4b 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -430,8 +430,9 @@ uint64_t HELPER(crc32c_64)(uint64_t acc, uint64_t val, uint32_t bytes)
}
/* Returns 0 on success; 1 otherwise. */
-uint64_t HELPER(paired_cmpxchg64_le)(CPUARMState *env, uint64_t addr,
- uint64_t new_lo, uint64_t new_hi)
+static uint64_t do_paired_cmpxchg64_le(CPUARMState *env, uint64_t addr,
+ uint64_t new_lo, uint64_t new_hi,
+ bool parallel)
{
uintptr_t ra = GETPC();
Int128 oldv, cmpv, newv;
@@ -440,7 +441,7 @@ uint64_t HELPER(paired_cmpxchg64_le)(CPUARMState *env, uint64_t addr,
cmpv = int128_make128(env->exclusive_val, env->exclusive_high);
newv = int128_make128(new_lo, new_hi);
- if (parallel_cpus) {
+ if (parallel) {
#ifndef CONFIG_ATOMIC128
cpu_loop_exit_atomic(ENV_GET_CPU(env), ra);
#else
@@ -484,8 +485,21 @@ uint64_t HELPER(paired_cmpxchg64_le)(CPUARMState *env, uint64_t addr,
return !success;
}
-uint64_t HELPER(paired_cmpxchg64_be)(CPUARMState *env, uint64_t addr,
- uint64_t new_lo, uint64_t new_hi)
+uint64_t HELPER(paired_cmpxchg64_le)(CPUARMState *env, uint64_t addr,
+ uint64_t new_lo, uint64_t new_hi)
+{
+ return do_paired_cmpxchg64_le(env, addr, new_lo, new_hi, false);
+}
+
+uint64_t HELPER(paired_cmpxchg64_le_parallel)(CPUARMState *env, uint64_t addr,
+ uint64_t new_lo, uint64_t new_hi)
+{
+ return do_paired_cmpxchg64_le(env, addr, new_lo, new_hi, true);
+}
+
+static uint64_t do_paired_cmpxchg64_be(CPUARMState *env, uint64_t addr,
+ uint64_t new_lo, uint64_t new_hi,
+ bool parallel)
{
uintptr_t ra = GETPC();
Int128 oldv, cmpv, newv;
@@ -494,7 +508,7 @@ uint64_t HELPER(paired_cmpxchg64_be)(CPUARMState *env, uint64_t addr,
cmpv = int128_make128(env->exclusive_val, env->exclusive_high);
newv = int128_make128(new_lo, new_hi);
- if (parallel_cpus) {
+ if (parallel) {
#ifndef CONFIG_ATOMIC128
cpu_loop_exit_atomic(ENV_GET_CPU(env), ra);
#else
@@ -537,3 +551,15 @@ uint64_t HELPER(paired_cmpxchg64_be)(CPUARMState *env, uint64_t addr,
return !success;
}
+
+uint64_t HELPER(paired_cmpxchg64_be)(CPUARMState *env, uint64_t addr,
+ uint64_t new_lo, uint64_t new_hi)
+{
+ return do_paired_cmpxchg64_be(env, addr, new_lo, new_hi, false);
+}
+
+uint64_t HELPER(paired_cmpxchg64_be_parallel)(CPUARMState *env, uint64_t addr,
+ uint64_t new_lo, uint64_t new_hi)
+{
+ return do_paired_cmpxchg64_be(env, addr, new_lo, new_hi, true);
+}
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
index 3914145709..138d0df82f 100644
--- a/target/arm/op_helper.c
+++ b/target/arm/op_helper.c
@@ -502,13 +502,6 @@ void HELPER(yield)(CPUARMState *env)
ARMCPU *cpu = arm_env_get_cpu(env);
CPUState *cs = CPU(cpu);
- /* When running in MTTCG we don't generate jumps to the yield and
- * WFE helpers as it won't affect the scheduling of other vCPUs.
- * If we wanted to more completely model WFE/SEV so we don't busy
- * spin unnecessarily we would need to do something more involved.
- */
- g_assert(!parallel_cpus);
-
/* This is a non-trappable hint instruction that generally indicates
* that the guest is currently busy-looping. Yield control back to the
* top level loop so that a more deserving VCPU has a chance to run.
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index e9bee8c196..f6b364c04b 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -1336,13 +1336,18 @@ static void handle_hint(DisasContext *s, uint32_t insn,
case 3: /* WFI */
s->base.is_jmp = DISAS_WFI;
return;
+ /* When running in MTTCG we don't generate jumps to the yield and
+ * WFE helpers as it won't affect the scheduling of other vCPUs.
+ * If we wanted to more completely model WFE/SEV so we don't busy
+ * spin unnecessarily we would need to do something more involved.
+ */
case 1: /* YIELD */
- if (!parallel_cpus) {
+ if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) {
s->base.is_jmp = DISAS_YIELD;
}
return;
case 2: /* WFE */
- if (!parallel_cpus) {
+ if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) {
s->base.is_jmp = DISAS_WFE;
}
return;
@@ -1931,11 +1936,25 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
MO_64 | MO_ALIGN | s->be_data);
tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, cpu_exclusive_val);
} else if (s->be_data == MO_LE) {
- gen_helper_paired_cmpxchg64_le(tmp, cpu_env, cpu_exclusive_addr,
- cpu_reg(s, rt), cpu_reg(s, rt2));
+ if (tb_cflags(s->base.tb) & CF_PARALLEL) {
+ gen_helper_paired_cmpxchg64_le_parallel(tmp, cpu_env,
+ cpu_exclusive_addr,
+ cpu_reg(s, rt),
+ cpu_reg(s, rt2));
+ } else {
+ gen_helper_paired_cmpxchg64_le(tmp, cpu_env, cpu_exclusive_addr,
+ cpu_reg(s, rt), cpu_reg(s, rt2));
+ }
} else {
- gen_helper_paired_cmpxchg64_be(tmp, cpu_env, cpu_exclusive_addr,
- cpu_reg(s, rt), cpu_reg(s, rt2));
+ if (tb_cflags(s->base.tb) & CF_PARALLEL) {
+ gen_helper_paired_cmpxchg64_be_parallel(tmp, cpu_env,
+ cpu_exclusive_addr,
+ cpu_reg(s, rt),
+ cpu_reg(s, rt2));
+ } else {
+ gen_helper_paired_cmpxchg64_be(tmp, cpu_env, cpu_exclusive_addr,
+ cpu_reg(s, rt), cpu_reg(s, rt2));
+ }
}
} else {
tcg_gen_atomic_cmpxchg_i64(tmp, cpu_exclusive_addr, cpu_exclusive_val,
diff --git a/target/arm/translate.c b/target/arm/translate.c
index dfa547b1db..397cc7afea 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -4546,8 +4546,13 @@ static void gen_exception_return(DisasContext *s, TCGv_i32 pc)
static void gen_nop_hint(DisasContext *s, int val)
{
switch (val) {
+ /* When running in MTTCG we don't generate jumps to the yield and
+ * WFE helpers as it won't affect the scheduling of other vCPUs.
+ * If we wanted to more completely model WFE/SEV so we don't busy
+ * spin unnecessarily we would need to do something more involved.
+ */
case 1: /* yield */
- if (!parallel_cpus) {
+ if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) {
gen_set_pc_im(s, s->pc);
s->base.is_jmp = DISAS_YIELD;
}
@@ -4557,7 +4562,7 @@ static void gen_nop_hint(DisasContext *s, int val)
s->base.is_jmp = DISAS_WFI;
break;
case 2: /* wfe */
- if (!parallel_cpus) {
+ if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) {
gen_set_pc_im(s, s->pc);
s->base.is_jmp = DISAS_WFE;
}
--
2.13.6
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [Qemu-devel] [PULL 27/51] target/hppa: check CF_PARALLEL instead of parallel_cpus
2017-10-25 9:34 [Qemu-devel] [PULL 00/51] tcg queued patches Richard Henderson
` (25 preceding siblings ...)
2017-10-25 9:35 ` [Qemu-devel] [PULL 26/51] target/arm: check CF_PARALLEL instead of parallel_cpus Richard Henderson
@ 2017-10-25 9:35 ` Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 28/51] target/i386: " Richard Henderson
` (26 subsequent siblings)
53 siblings, 0 replies; 59+ messages in thread
From: Richard Henderson @ 2017-10-25 9:35 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Emilio G. Cota
From: "Emilio G. Cota" <cota@braap.org>
Thereby decoupling the resulting translated code from the current state
of the system.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/helper.h | 2 ++
target/hppa/op_helper.c | 32 ++++++++++++++++++++++++++++----
target/hppa/translate.c | 12 ++++++++++--
3 files changed, 40 insertions(+), 6 deletions(-)
diff --git a/target/hppa/helper.h b/target/hppa/helper.h
index 789f07fc0a..0a6b900555 100644
--- a/target/hppa/helper.h
+++ b/target/hppa/helper.h
@@ -3,7 +3,9 @@ DEF_HELPER_FLAGS_2(tsv, TCG_CALL_NO_WG, void, env, tl)
DEF_HELPER_FLAGS_2(tcond, TCG_CALL_NO_WG, void, env, tl)
DEF_HELPER_FLAGS_3(stby_b, TCG_CALL_NO_WG, void, env, tl, tl)
+DEF_HELPER_FLAGS_3(stby_b_parallel, TCG_CALL_NO_WG, void, env, tl, tl)
DEF_HELPER_FLAGS_3(stby_e, TCG_CALL_NO_WG, void, env, tl, tl)
+DEF_HELPER_FLAGS_3(stby_e_parallel, TCG_CALL_NO_WG, void, env, tl, tl)
DEF_HELPER_FLAGS_1(probe_r, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_1(probe_w, TCG_CALL_NO_RWG_SE, tl, tl)
diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c
index c05c0d5572..3104404e8d 100644
--- a/target/hppa/op_helper.c
+++ b/target/hppa/op_helper.c
@@ -76,7 +76,8 @@ static void atomic_store_3(CPUHPPAState *env, target_ulong addr, uint32_t val,
#endif
}
-void HELPER(stby_b)(CPUHPPAState *env, target_ulong addr, target_ulong val)
+static void do_stby_b(CPUHPPAState *env, target_ulong addr, target_ulong val,
+ bool parallel)
{
uintptr_t ra = GETPC();
@@ -89,7 +90,7 @@ void HELPER(stby_b)(CPUHPPAState *env, target_ulong addr, target_ulong val)
break;
case 1:
/* The 3 byte store must appear atomic. */
- if (parallel_cpus) {
+ if (parallel) {
atomic_store_3(env, addr, val, 0x00ffffffu, ra);
} else {
cpu_stb_data_ra(env, addr, val >> 16, ra);
@@ -102,14 +103,26 @@ void HELPER(stby_b)(CPUHPPAState *env, target_ulong addr, target_ulong val)
}
}
-void HELPER(stby_e)(CPUHPPAState *env, target_ulong addr, target_ulong val)
+void HELPER(stby_b)(CPUHPPAState *env, target_ulong addr, target_ulong val)
+{
+ do_stby_b(env, addr, val, false);
+}
+
+void HELPER(stby_b_parallel)(CPUHPPAState *env, target_ulong addr,
+ target_ulong val)
+{
+ do_stby_b(env, addr, val, true);
+}
+
+static void do_stby_e(CPUHPPAState *env, target_ulong addr, target_ulong val,
+ bool parallel)
{
uintptr_t ra = GETPC();
switch (addr & 3) {
case 3:
/* The 3 byte store must appear atomic. */
- if (parallel_cpus) {
+ if (parallel) {
atomic_store_3(env, addr - 3, val, 0xffffff00u, ra);
} else {
cpu_stw_data_ra(env, addr - 3, val >> 16, ra);
@@ -132,6 +145,17 @@ void HELPER(stby_e)(CPUHPPAState *env, target_ulong addr, target_ulong val)
}
}
+void HELPER(stby_e)(CPUHPPAState *env, target_ulong addr, target_ulong val)
+{
+ do_stby_e(env, addr, val, false);
+}
+
+void HELPER(stby_e_parallel)(CPUHPPAState *env, target_ulong addr,
+ target_ulong val)
+{
+ do_stby_e(env, addr, val, true);
+}
+
target_ulong HELPER(probe_r)(target_ulong addr)
{
return page_check_range(addr, 1, PAGE_READ);
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 460b4d3154..08b2c73291 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -2291,9 +2291,17 @@ static DisasJumpType trans_stby(DisasContext *ctx, uint32_t insn,
val = load_gpr(ctx, rt);
if (a) {
- gen_helper_stby_e(cpu_env, addr, val);
+ if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
+ gen_helper_stby_e_parallel(cpu_env, addr, val);
+ } else {
+ gen_helper_stby_e(cpu_env, addr, val);
+ }
} else {
- gen_helper_stby_b(cpu_env, addr, val);
+ if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
+ gen_helper_stby_b_parallel(cpu_env, addr, val);
+ } else {
+ gen_helper_stby_b(cpu_env, addr, val);
+ }
}
if (m) {
--
2.13.6
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [Qemu-devel] [PULL 28/51] target/i386: check CF_PARALLEL instead of parallel_cpus
2017-10-25 9:34 [Qemu-devel] [PULL 00/51] tcg queued patches Richard Henderson
` (26 preceding siblings ...)
2017-10-25 9:35 ` [Qemu-devel] [PULL 27/51] target/hppa: " Richard Henderson
@ 2017-10-25 9:35 ` Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 29/51] target/m68k: " Richard Henderson
` (25 subsequent siblings)
53 siblings, 0 replies; 59+ messages in thread
From: Richard Henderson @ 2017-10-25 9:35 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Emilio G. Cota
From: "Emilio G. Cota" <cota@braap.org>
Thereby decoupling the resulting translated code from the current state
of the system.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/i386/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/i386/translate.c b/target/i386/translate.c
index 2e2e0dbddc..70ba0b2d5a 100644
--- a/target/i386/translate.c
+++ b/target/i386/translate.c
@@ -5307,7 +5307,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
if (!(s->cpuid_ext_features & CPUID_EXT_CX16))
goto illegal_op;
gen_lea_modrm(env, s, modrm);
- if ((s->prefix & PREFIX_LOCK) && parallel_cpus) {
+ if ((s->prefix & PREFIX_LOCK) && (tb_cflags(s->base.tb) & CF_PARALLEL)) {
gen_helper_cmpxchg16b(cpu_env, cpu_A0);
} else {
gen_helper_cmpxchg16b_unlocked(cpu_env, cpu_A0);
@@ -5318,7 +5318,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
if (!(s->cpuid_features & CPUID_CX8))
goto illegal_op;
gen_lea_modrm(env, s, modrm);
- if ((s->prefix & PREFIX_LOCK) && parallel_cpus) {
+ if ((s->prefix & PREFIX_LOCK) && (tb_cflags(s->base.tb) & CF_PARALLEL)) {
gen_helper_cmpxchg8b(cpu_env, cpu_A0);
} else {
gen_helper_cmpxchg8b_unlocked(cpu_env, cpu_A0);
--
2.13.6
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [Qemu-devel] [PULL 29/51] target/m68k: check CF_PARALLEL instead of parallel_cpus
2017-10-25 9:34 [Qemu-devel] [PULL 00/51] tcg queued patches Richard Henderson
` (27 preceding siblings ...)
2017-10-25 9:35 ` [Qemu-devel] [PULL 28/51] target/i386: " Richard Henderson
@ 2017-10-25 9:35 ` Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 30/51] target/s390x: " Richard Henderson
` (24 subsequent siblings)
53 siblings, 0 replies; 59+ messages in thread
From: Richard Henderson @ 2017-10-25 9:35 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Emilio G. Cota
From: "Emilio G. Cota" <cota@braap.org>
Thereby decoupling the resulting translated code from the current state
of the system.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/m68k/helper.h | 1 +
target/m68k/op_helper.c | 33 ++++++++++++++++++++-------------
target/m68k/translate.c | 12 ++++++++++--
3 files changed, 31 insertions(+), 15 deletions(-)
diff --git a/target/m68k/helper.h b/target/m68k/helper.h
index 475a1f2186..eebe52dae5 100644
--- a/target/m68k/helper.h
+++ b/target/m68k/helper.h
@@ -11,6 +11,7 @@ DEF_HELPER_2(set_sr, void, env, i32)
DEF_HELPER_3(movec, void, env, i32, i32)
DEF_HELPER_4(cas2w, void, env, i32, i32, i32)
DEF_HELPER_4(cas2l, void, env, i32, i32, i32)
+DEF_HELPER_4(cas2l_parallel, void, env, i32, i32, i32)
#define dh_alias_fp ptr
#define dh_ctype_fp FPReg *
diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c
index 7b5126c88d..63089511cb 100644
--- a/target/m68k/op_helper.c
+++ b/target/m68k/op_helper.c
@@ -361,6 +361,7 @@ void HELPER(divsll)(CPUM68KState *env, int numr, int regr, int32_t den)
env->dregs[numr] = quot;
}
+/* We're executing in a serial context -- no need to be atomic. */
void HELPER(cas2w)(CPUM68KState *env, uint32_t regs, uint32_t a1, uint32_t a2)
{
uint32_t Dc1 = extract32(regs, 9, 3);
@@ -374,17 +375,11 @@ void HELPER(cas2w)(CPUM68KState *env, uint32_t regs, uint32_t a1, uint32_t a2)
int16_t l1, l2;
uintptr_t ra = GETPC();
- if (parallel_cpus) {
- /* Tell the main loop we need to serialize this insn. */
- cpu_loop_exit_atomic(ENV_GET_CPU(env), ra);
- } else {
- /* We're executing in a serial context -- no need to be atomic. */
- l1 = cpu_lduw_data_ra(env, a1, ra);
- l2 = cpu_lduw_data_ra(env, a2, ra);
- if (l1 == c1 && l2 == c2) {
- cpu_stw_data_ra(env, a1, u1, ra);
- cpu_stw_data_ra(env, a2, u2, ra);
- }
+ l1 = cpu_lduw_data_ra(env, a1, ra);
+ l2 = cpu_lduw_data_ra(env, a2, ra);
+ if (l1 == c1 && l2 == c2) {
+ cpu_stw_data_ra(env, a1, u1, ra);
+ cpu_stw_data_ra(env, a2, u2, ra);
}
if (c1 != l1) {
@@ -399,7 +394,8 @@ void HELPER(cas2w)(CPUM68KState *env, uint32_t regs, uint32_t a1, uint32_t a2)
env->dregs[Dc2] = deposit32(env->dregs[Dc2], 0, 16, l2);
}
-void HELPER(cas2l)(CPUM68KState *env, uint32_t regs, uint32_t a1, uint32_t a2)
+static void do_cas2l(CPUM68KState *env, uint32_t regs, uint32_t a1, uint32_t a2,
+ bool parallel)
{
uint32_t Dc1 = extract32(regs, 9, 3);
uint32_t Dc2 = extract32(regs, 6, 3);
@@ -416,7 +412,7 @@ void HELPER(cas2l)(CPUM68KState *env, uint32_t regs, uint32_t a1, uint32_t a2)
TCGMemOpIdx oi;
#endif
- if (parallel_cpus) {
+ if (parallel) {
/* We're executing in a parallel context -- must be atomic. */
#ifdef CONFIG_ATOMIC64
uint64_t c, u, l;
@@ -470,6 +466,17 @@ void HELPER(cas2l)(CPUM68KState *env, uint32_t regs, uint32_t a1, uint32_t a2)
env->dregs[Dc2] = l2;
}
+void HELPER(cas2l)(CPUM68KState *env, uint32_t regs, uint32_t a1, uint32_t a2)
+{
+ do_cas2l(env, regs, a1, a2, false);
+}
+
+void HELPER(cas2l_parallel)(CPUM68KState *env, uint32_t regs, uint32_t a1,
+ uint32_t a2)
+{
+ do_cas2l(env, regs, a1, a2, true);
+}
+
struct bf_data {
uint32_t addr;
uint32_t bofs;
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index fdc26268d0..d751faed7c 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -2312,7 +2312,11 @@ DISAS_INSN(cas2w)
(REG(ext1, 6) << 3) |
(REG(ext2, 0) << 6) |
(REG(ext1, 0) << 9));
- gen_helper_cas2w(cpu_env, regs, addr1, addr2);
+ if (tb_cflags(s->tb) & CF_PARALLEL) {
+ gen_helper_exit_atomic(cpu_env);
+ } else {
+ gen_helper_cas2w(cpu_env, regs, addr1, addr2);
+ }
tcg_temp_free(regs);
/* Note that cas2w also assigned to env->cc_op. */
@@ -2358,7 +2362,11 @@ DISAS_INSN(cas2l)
(REG(ext1, 6) << 3) |
(REG(ext2, 0) << 6) |
(REG(ext1, 0) << 9));
- gen_helper_cas2l(cpu_env, regs, addr1, addr2);
+ if (tb_cflags(s->tb) & CF_PARALLEL) {
+ gen_helper_cas2l_parallel(cpu_env, regs, addr1, addr2);
+ } else {
+ gen_helper_cas2l(cpu_env, regs, addr1, addr2);
+ }
tcg_temp_free(regs);
/* Note that cas2l also assigned to env->cc_op. */
--
2.13.6
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [Qemu-devel] [PULL 30/51] target/s390x: check CF_PARALLEL instead of parallel_cpus
2017-10-25 9:34 [Qemu-devel] [PULL 00/51] tcg queued patches Richard Henderson
` (28 preceding siblings ...)
2017-10-25 9:35 ` [Qemu-devel] [PULL 29/51] target/m68k: " Richard Henderson
@ 2017-10-25 9:35 ` Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 31/51] target/sh4: " Richard Henderson
` (23 subsequent siblings)
53 siblings, 0 replies; 59+ messages in thread
From: Richard Henderson @ 2017-10-25 9:35 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Emilio G. Cota
From: "Emilio G. Cota" <cota@braap.org>
Thereby decoupling the resulting translated code from the current state
of the system.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/s390x/helper.h | 4 +++
target/s390x/mem_helper.c | 80 +++++++++++++++++++++++++++++++++++++----------
target/s390x/translate.c | 26 ++++++++++++---
3 files changed, 88 insertions(+), 22 deletions(-)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index 81c5727168..9459b73c73 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -34,7 +34,9 @@ DEF_HELPER_3(celgb, i64, env, i64, i32)
DEF_HELPER_3(cdlgb, i64, env, i64, i32)
DEF_HELPER_3(cxlgb, i64, env, i64, i32)
DEF_HELPER_4(cdsg, void, env, i64, i32, i32)
+DEF_HELPER_4(cdsg_parallel, void, env, i64, i32, i32)
DEF_HELPER_4(csst, i32, env, i32, i64, i64)
+DEF_HELPER_4(csst_parallel, i32, env, i32, i64, i64)
DEF_HELPER_FLAGS_3(aeb, TCG_CALL_NO_WG, i64, env, i64, i64)
DEF_HELPER_FLAGS_3(adb, TCG_CALL_NO_WG, i64, env, i64, i64)
DEF_HELPER_FLAGS_5(axb, TCG_CALL_NO_WG, i64, env, i64, i64, i64, i64)
@@ -106,7 +108,9 @@ DEF_HELPER_FLAGS_2(sfas, TCG_CALL_NO_WG, void, env, i64)
DEF_HELPER_FLAGS_1(popcnt, TCG_CALL_NO_RWG_SE, i64, i64)
DEF_HELPER_2(stfle, i32, env, i64)
DEF_HELPER_FLAGS_2(lpq, TCG_CALL_NO_WG, i64, env, i64)
+DEF_HELPER_FLAGS_2(lpq_parallel, TCG_CALL_NO_WG, i64, env, i64)
DEF_HELPER_FLAGS_4(stpq, TCG_CALL_NO_WG, void, env, i64, i64, i64)
+DEF_HELPER_FLAGS_4(stpq_parallel, TCG_CALL_NO_WG, void, env, i64, i64, i64)
DEF_HELPER_4(mvcos, i32, env, i64, i64, i64)
DEF_HELPER_4(cu12, i32, env, i32, i32, i32)
DEF_HELPER_4(cu14, i32, env, i32, i32, i32)
diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c
index 69a16867d4..a1652d4849 100644
--- a/target/s390x/mem_helper.c
+++ b/target/s390x/mem_helper.c
@@ -1361,8 +1361,8 @@ uint32_t HELPER(trXX)(CPUS390XState *env, uint32_t r1, uint32_t r2,
return cc;
}
-void HELPER(cdsg)(CPUS390XState *env, uint64_t addr,
- uint32_t r1, uint32_t r3)
+static void do_cdsg(CPUS390XState *env, uint64_t addr,
+ uint32_t r1, uint32_t r3, bool parallel)
{
uintptr_t ra = GETPC();
Int128 cmpv = int128_make128(env->regs[r1 + 1], env->regs[r1]);
@@ -1370,7 +1370,7 @@ void HELPER(cdsg)(CPUS390XState *env, uint64_t addr,
Int128 oldv;
bool fail;
- if (parallel_cpus) {
+ if (parallel) {
#ifndef CONFIG_ATOMIC128
cpu_loop_exit_atomic(ENV_GET_CPU(env), ra);
#else
@@ -1402,7 +1402,20 @@ void HELPER(cdsg)(CPUS390XState *env, uint64_t addr,
env->regs[r1 + 1] = int128_getlo(oldv);
}
-uint32_t HELPER(csst)(CPUS390XState *env, uint32_t r3, uint64_t a1, uint64_t a2)
+void HELPER(cdsg)(CPUS390XState *env, uint64_t addr,
+ uint32_t r1, uint32_t r3)
+{
+ do_cdsg(env, addr, r1, r3, false);
+}
+
+void HELPER(cdsg_parallel)(CPUS390XState *env, uint64_t addr,
+ uint32_t r1, uint32_t r3)
+{
+ do_cdsg(env, addr, r1, r3, true);
+}
+
+static uint32_t do_csst(CPUS390XState *env, uint32_t r3, uint64_t a1,
+ uint64_t a2, bool parallel)
{
#if !defined(CONFIG_USER_ONLY) || defined(CONFIG_ATOMIC128)
uint32_t mem_idx = cpu_mmu_index(env, false);
@@ -1438,7 +1451,7 @@ uint32_t HELPER(csst)(CPUS390XState *env, uint32_t r3, uint64_t a1, uint64_t a2)
the complete operation is not. Therefore we do not need to assert serial
context in order to implement this. That said, restart early if we can't
support either operation that is supposed to be atomic. */
- if (parallel_cpus) {
+ if (parallel) {
int mask = 0;
#if !defined(CONFIG_ATOMIC64)
mask = -8;
@@ -1462,7 +1475,7 @@ uint32_t HELPER(csst)(CPUS390XState *env, uint32_t r3, uint64_t a1, uint64_t a2)
uint32_t cv = env->regs[r3];
uint32_t ov;
- if (parallel_cpus) {
+ if (parallel) {
#ifdef CONFIG_USER_ONLY
uint32_t *haddr = g2h(a1);
ov = atomic_cmpxchg__nocheck(haddr, cv, nv);
@@ -1485,7 +1498,7 @@ uint32_t HELPER(csst)(CPUS390XState *env, uint32_t r3, uint64_t a1, uint64_t a2)
uint64_t cv = env->regs[r3];
uint64_t ov;
- if (parallel_cpus) {
+ if (parallel) {
#ifdef CONFIG_ATOMIC64
# ifdef CONFIG_USER_ONLY
uint64_t *haddr = g2h(a1);
@@ -1495,7 +1508,7 @@ uint32_t HELPER(csst)(CPUS390XState *env, uint32_t r3, uint64_t a1, uint64_t a2)
ov = helper_atomic_cmpxchgq_be_mmu(env, a1, cv, nv, oi, ra);
# endif
#else
- /* Note that we asserted !parallel_cpus above. */
+ /* Note that we asserted !parallel above. */
g_assert_not_reached();
#endif
} else {
@@ -1515,13 +1528,13 @@ uint32_t HELPER(csst)(CPUS390XState *env, uint32_t r3, uint64_t a1, uint64_t a2)
Int128 cv = int128_make128(env->regs[r3 + 1], env->regs[r3]);
Int128 ov;
- if (parallel_cpus) {
+ if (parallel) {
#ifdef CONFIG_ATOMIC128
TCGMemOpIdx oi = make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx);
ov = helper_atomic_cmpxchgo_be_mmu(env, a1, cv, nv, oi, ra);
cc = !int128_eq(ov, cv);
#else
- /* Note that we asserted !parallel_cpus above. */
+ /* Note that we asserted !parallel above. */
g_assert_not_reached();
#endif
} else {
@@ -1565,13 +1578,13 @@ uint32_t HELPER(csst)(CPUS390XState *env, uint32_t r3, uint64_t a1, uint64_t a2)
cpu_stq_data_ra(env, a2, svh, ra);
break;
case 4:
- if (parallel_cpus) {
+ if (parallel) {
#ifdef CONFIG_ATOMIC128
TCGMemOpIdx oi = make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx);
Int128 sv = int128_make128(svl, svh);
helper_atomic_sto_be_mmu(env, a2, sv, oi, ra);
#else
- /* Note that we asserted !parallel_cpus above. */
+ /* Note that we asserted !parallel above. */
g_assert_not_reached();
#endif
} else {
@@ -1592,6 +1605,17 @@ uint32_t HELPER(csst)(CPUS390XState *env, uint32_t r3, uint64_t a1, uint64_t a2)
g_assert_not_reached();
}
+uint32_t HELPER(csst)(CPUS390XState *env, uint32_t r3, uint64_t a1, uint64_t a2)
+{
+ return do_csst(env, r3, a1, a2, false);
+}
+
+uint32_t HELPER(csst_parallel)(CPUS390XState *env, uint32_t r3, uint64_t a1,
+ uint64_t a2)
+{
+ return do_csst(env, r3, a1, a2, true);
+}
+
#if !defined(CONFIG_USER_ONLY)
void HELPER(lctlg)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3)
{
@@ -2011,12 +2035,12 @@ uint64_t HELPER(lra)(CPUS390XState *env, uint64_t addr)
#endif
/* load pair from quadword */
-uint64_t HELPER(lpq)(CPUS390XState *env, uint64_t addr)
+static uint64_t do_lpq(CPUS390XState *env, uint64_t addr, bool parallel)
{
uintptr_t ra = GETPC();
uint64_t hi, lo;
- if (parallel_cpus) {
+ if (parallel) {
#ifndef CONFIG_ATOMIC128
cpu_loop_exit_atomic(ENV_GET_CPU(env), ra);
#else
@@ -2037,13 +2061,23 @@ uint64_t HELPER(lpq)(CPUS390XState *env, uint64_t addr)
return hi;
}
+uint64_t HELPER(lpq)(CPUS390XState *env, uint64_t addr)
+{
+ return do_lpq(env, addr, false);
+}
+
+uint64_t HELPER(lpq_parallel)(CPUS390XState *env, uint64_t addr)
+{
+ return do_lpq(env, addr, true);
+}
+
/* store pair to quadword */
-void HELPER(stpq)(CPUS390XState *env, uint64_t addr,
- uint64_t low, uint64_t high)
+static void do_stpq(CPUS390XState *env, uint64_t addr,
+ uint64_t low, uint64_t high, bool parallel)
{
uintptr_t ra = GETPC();
- if (parallel_cpus) {
+ if (parallel) {
#ifndef CONFIG_ATOMIC128
cpu_loop_exit_atomic(ENV_GET_CPU(env), ra);
#else
@@ -2061,6 +2095,18 @@ void HELPER(stpq)(CPUS390XState *env, uint64_t addr,
}
}
+void HELPER(stpq)(CPUS390XState *env, uint64_t addr,
+ uint64_t low, uint64_t high)
+{
+ do_stpq(env, addr, low, high, false);
+}
+
+void HELPER(stpq_parallel)(CPUS390XState *env, uint64_t addr,
+ uint64_t low, uint64_t high)
+{
+ do_stpq(env, addr, low, high, true);
+}
+
/* Execute instruction. This instruction executes an insn modified with
the contents of r1. It does not change the executed instruction in memory;
it does not change the program counter.
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index d589fb2459..241b708502 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -1966,7 +1966,11 @@ static ExitStatus op_cdsg(DisasContext *s, DisasOps *o)
addr = get_address(s, 0, b2, d2);
t_r1 = tcg_const_i32(r1);
t_r3 = tcg_const_i32(r3);
- gen_helper_cdsg(cpu_env, addr, t_r1, t_r3);
+ if (tb_cflags(s->tb) & CF_PARALLEL) {
+ gen_helper_cdsg_parallel(cpu_env, addr, t_r1, t_r3);
+ } else {
+ gen_helper_cdsg(cpu_env, addr, t_r1, t_r3);
+ }
tcg_temp_free_i64(addr);
tcg_temp_free_i32(t_r1);
tcg_temp_free_i32(t_r3);
@@ -1980,7 +1984,11 @@ static ExitStatus op_csst(DisasContext *s, DisasOps *o)
int r3 = get_field(s->fields, r3);
TCGv_i32 t_r3 = tcg_const_i32(r3);
- gen_helper_csst(cc_op, cpu_env, t_r3, o->in1, o->in2);
+ if (tb_cflags(s->tb) & CF_PARALLEL) {
+ gen_helper_csst_parallel(cc_op, cpu_env, t_r3, o->in1, o->in2);
+ } else {
+ gen_helper_csst(cc_op, cpu_env, t_r3, o->in1, o->in2);
+ }
tcg_temp_free_i32(t_r3);
set_cc_static(s);
@@ -2939,7 +2947,7 @@ static ExitStatus op_lpd(DisasContext *s, DisasOps *o)
TCGMemOp mop = s->insn->data;
/* In a parallel context, stop the world and single step. */
- if (parallel_cpus) {
+ if (tb_cflags(s->tb) & CF_PARALLEL) {
potential_page_fault(s);
gen_exception(EXCP_ATOMIC);
return EXIT_NORETURN;
@@ -2960,7 +2968,11 @@ static ExitStatus op_lpd(DisasContext *s, DisasOps *o)
static ExitStatus op_lpq(DisasContext *s, DisasOps *o)
{
- gen_helper_lpq(o->out, cpu_env, o->in2);
+ if (tb_cflags(s->tb) & CF_PARALLEL) {
+ gen_helper_lpq_parallel(o->out, cpu_env, o->in2);
+ } else {
+ gen_helper_lpq(o->out, cpu_env, o->in2);
+ }
return_low128(o->out2);
return NO_EXIT;
}
@@ -4281,7 +4293,11 @@ static ExitStatus op_stmh(DisasContext *s, DisasOps *o)
static ExitStatus op_stpq(DisasContext *s, DisasOps *o)
{
- gen_helper_stpq(cpu_env, o->in2, o->out2, o->out);
+ if (tb_cflags(s->tb) & CF_PARALLEL) {
+ gen_helper_stpq_parallel(cpu_env, o->in2, o->out2, o->out);
+ } else {
+ gen_helper_stpq(cpu_env, o->in2, o->out2, o->out);
+ }
return NO_EXIT;
}
--
2.13.6
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [Qemu-devel] [PULL 31/51] target/sh4: check CF_PARALLEL instead of parallel_cpus
2017-10-25 9:34 [Qemu-devel] [PULL 00/51] tcg queued patches Richard Henderson
` (29 preceding siblings ...)
2017-10-25 9:35 ` [Qemu-devel] [PULL 30/51] target/s390x: " Richard Henderson
@ 2017-10-25 9:35 ` Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 32/51] target/sparc: " Richard Henderson
` (22 subsequent siblings)
53 siblings, 0 replies; 59+ messages in thread
From: Richard Henderson @ 2017-10-25 9:35 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Emilio G. Cota
From: "Emilio G. Cota" <cota@braap.org>
Thereby decoupling the resulting translated code from the current state
of the system.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sh4/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index 33176c9926..f918bae978 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -521,7 +521,7 @@ static void _decode_opc(DisasContext * ctx)
/* Detect the start of a gUSA region. If so, update envflags
and end the TB. This will allow us to see the end of the
region (stored in R0) in the next TB. */
- if (B11_8 == 15 && B7_0s < 0 && parallel_cpus) {
+ if (B11_8 == 15 && B7_0s < 0 && (tb_cflags(ctx->tb) & CF_PARALLEL)) {
ctx->envflags = deposit32(ctx->envflags, GUSA_SHIFT, 8, B7_0s);
ctx->bstate = BS_STOP;
}
--
2.13.6
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [Qemu-devel] [PULL 32/51] target/sparc: check CF_PARALLEL instead of parallel_cpus
2017-10-25 9:34 [Qemu-devel] [PULL 00/51] tcg queued patches Richard Henderson
` (30 preceding siblings ...)
2017-10-25 9:35 ` [Qemu-devel] [PULL 31/51] target/sh4: " Richard Henderson
@ 2017-10-25 9:35 ` Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 33/51] tcg: " Richard Henderson
` (21 subsequent siblings)
53 siblings, 0 replies; 59+ messages in thread
From: Richard Henderson @ 2017-10-25 9:35 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Emilio G. Cota
From: "Emilio G. Cota" <cota@braap.org>
Thereby decoupling the resulting translated code from the current state
of the system.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sparc/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index f2b5cdbf34..9dc41869a4 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -2437,7 +2437,7 @@ static void gen_ldstub_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn)
default:
/* ??? In theory, this should be raise DAE_invalid_asi.
But the SS-20 roms do ldstuba [%l0] #ASI_M_CTL, %o1. */
- if (parallel_cpus) {
+ if (tb_cflags(dc->tb) & CF_PARALLEL) {
gen_helper_exit_atomic(cpu_env);
} else {
TCGv_i32 r_asi = tcg_const_i32(da.asi);
--
2.13.6
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [Qemu-devel] [PULL 33/51] tcg: check CF_PARALLEL instead of parallel_cpus
2017-10-25 9:34 [Qemu-devel] [PULL 00/51] tcg queued patches Richard Henderson
` (31 preceding siblings ...)
2017-10-25 9:35 ` [Qemu-devel] [PULL 32/51] target/sparc: " Richard Henderson
@ 2017-10-25 9:35 ` Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 34/51] cpu-exec: lookup/generate TB outside exclusive region during step_atomic Richard Henderson
` (20 subsequent siblings)
53 siblings, 0 replies; 59+ messages in thread
From: Richard Henderson @ 2017-10-25 9:35 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Emilio G. Cota
From: "Emilio G. Cota" <cota@braap.org>
Thereby decoupling the resulting translated code from the current state
of the system.
The tb->cflags field is not passed to tcg generation functions. So
we add a field to TCGContext, storing there a copy of tb->cflags.
Most architectures have <= 32 registers, which results in a 4-byte hole
in TCGContext. Use this hole for the new field.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tcg.h | 1 +
accel/tcg/translate-all.c | 1 +
tcg/tcg-op.c | 10 +++++-----
3 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/tcg/tcg.h b/tcg/tcg.h
index 92d7468cec..7c39eac428 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -614,6 +614,7 @@ struct TCGContext {
uintptr_t *tb_jmp_target_addr; /* tb->jmp_target_arg if !direct_jump */
TCGRegSet reserved_regs;
+ uint32_t tb_cflags; /* cflags of the current TB */
intptr_t current_frame_offset;
intptr_t frame_start;
intptr_t frame_end;
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index 91fd6e444b..dcd47cd692 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -1296,6 +1296,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
tb->flags = flags;
tb->cflags = cflags;
tb->trace_vcpu_dstate = *cpu->trace_dstate;
+ tcg_ctx.tb_cflags = cflags;
#ifdef CONFIG_PROFILER
tcg_ctx.tb_count1++; /* includes aborted translations because of
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index 9561510d9c..8c7668de60 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -121,7 +121,7 @@ void tcg_gen_op6(TCGOpcode opc, TCGArg a1, TCGArg a2, TCGArg a3,
void tcg_gen_mb(TCGBar mb_type)
{
- if (parallel_cpus) {
+ if (tcg_ctx.tb_cflags & CF_PARALLEL) {
tcg_gen_op1(INDEX_op_mb, mb_type);
}
}
@@ -2780,7 +2780,7 @@ void tcg_gen_atomic_cmpxchg_i32(TCGv_i32 retv, TCGv addr, TCGv_i32 cmpv,
{
memop = tcg_canonicalize_memop(memop, 0, 0);
- if (!parallel_cpus) {
+ if (!(tcg_ctx.tb_cflags & CF_PARALLEL)) {
TCGv_i32 t1 = tcg_temp_new_i32();
TCGv_i32 t2 = tcg_temp_new_i32();
@@ -2824,7 +2824,7 @@ void tcg_gen_atomic_cmpxchg_i64(TCGv_i64 retv, TCGv addr, TCGv_i64 cmpv,
{
memop = tcg_canonicalize_memop(memop, 1, 0);
- if (!parallel_cpus) {
+ if (!(tcg_ctx.tb_cflags & CF_PARALLEL)) {
TCGv_i64 t1 = tcg_temp_new_i64();
TCGv_i64 t2 = tcg_temp_new_i64();
@@ -3001,7 +3001,7 @@ static void * const table_##NAME[16] = { \
void tcg_gen_atomic_##NAME##_i32 \
(TCGv_i32 ret, TCGv addr, TCGv_i32 val, TCGArg idx, TCGMemOp memop) \
{ \
- if (parallel_cpus) { \
+ if (tcg_ctx.tb_cflags & CF_PARALLEL) { \
do_atomic_op_i32(ret, addr, val, idx, memop, table_##NAME); \
} else { \
do_nonatomic_op_i32(ret, addr, val, idx, memop, NEW, \
@@ -3011,7 +3011,7 @@ void tcg_gen_atomic_##NAME##_i32 \
void tcg_gen_atomic_##NAME##_i64 \
(TCGv_i64 ret, TCGv addr, TCGv_i64 val, TCGArg idx, TCGMemOp memop) \
{ \
- if (parallel_cpus) { \
+ if (tcg_ctx.tb_cflags & CF_PARALLEL) { \
do_atomic_op_i64(ret, addr, val, idx, memop, table_##NAME); \
} else { \
do_nonatomic_op_i64(ret, addr, val, idx, memop, NEW, \
--
2.13.6
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [Qemu-devel] [PULL 34/51] cpu-exec: lookup/generate TB outside exclusive region during step_atomic
2017-10-25 9:34 [Qemu-devel] [PULL 00/51] tcg queued patches Richard Henderson
` (32 preceding siblings ...)
2017-10-25 9:35 ` [Qemu-devel] [PULL 33/51] tcg: " Richard Henderson
@ 2017-10-25 9:35 ` Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 35/51] tcg: Add CF_LAST_IO + CF_USE_ICOUNT to CF_HASH_MASK Richard Henderson
` (19 subsequent siblings)
53 siblings, 0 replies; 59+ messages in thread
From: Richard Henderson @ 2017-10-25 9:35 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Emilio G. Cota
From: "Emilio G. Cota" <cota@braap.org>
Now that all code generation has been converted to check CF_PARALLEL, we can
generate !CF_PARALLEL code without having yet set !parallel_cpus --
and therefore without having to be in the exclusive region during
cpu_exec_step_atomic.
While at it, merge cpu_exec_step into cpu_exec_step_atomic.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/cpu-exec.c | 30 ++++++++++++++----------------
1 file changed, 14 insertions(+), 16 deletions(-)
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 1c64977849..849b54d0b0 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -223,30 +223,40 @@ static void cpu_exec_nocache(CPUState *cpu, int max_cycles,
}
#endif
-static void cpu_exec_step(CPUState *cpu)
+void cpu_exec_step_atomic(CPUState *cpu)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
TranslationBlock *tb;
target_ulong cs_base, pc;
uint32_t flags;
uint32_t cflags = 1 | CF_IGNORE_ICOUNT;
+ uint32_t cf_mask = cflags & CF_HASH_MASK;
if (sigsetjmp(cpu->jmp_env, 0) == 0) {
- tb = tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags,
- cflags & CF_HASH_MASK);
+ tb = tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags, cf_mask);
if (tb == NULL) {
mmap_lock();
tb_lock();
- tb = tb_gen_code(cpu, pc, cs_base, flags, cflags);
+ tb = tb_htable_lookup(cpu, pc, cs_base, flags, cf_mask);
+ if (likely(tb == NULL)) {
+ tb = tb_gen_code(cpu, pc, cs_base, flags, cflags);
+ }
tb_unlock();
mmap_unlock();
}
+ start_exclusive();
+
+ /* Since we got here, we know that parallel_cpus must be true. */
+ parallel_cpus = false;
cc->cpu_exec_enter(cpu);
/* execute the generated code */
trace_exec_tb(tb, pc);
cpu_tb_exec(cpu, tb);
cc->cpu_exec_exit(cpu);
+ parallel_cpus = true;
+
+ end_exclusive();
} else {
/* We may have exited due to another problem here, so we need
* to reset any tb_locks we may have taken but didn't release.
@@ -260,18 +270,6 @@ static void cpu_exec_step(CPUState *cpu)
}
}
-void cpu_exec_step_atomic(CPUState *cpu)
-{
- start_exclusive();
-
- /* Since we got here, we know that parallel_cpus must be true. */
- parallel_cpus = false;
- cpu_exec_step(cpu);
- parallel_cpus = true;
-
- end_exclusive();
-}
-
struct tb_desc {
target_ulong pc;
target_ulong cs_base;
--
2.13.6
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [Qemu-devel] [PULL 35/51] tcg: Add CF_LAST_IO + CF_USE_ICOUNT to CF_HASH_MASK
2017-10-25 9:34 [Qemu-devel] [PULL 00/51] tcg queued patches Richard Henderson
` (33 preceding siblings ...)
2017-10-25 9:35 ` [Qemu-devel] [PULL 34/51] cpu-exec: lookup/generate TB outside exclusive region during step_atomic Richard Henderson
@ 2017-10-25 9:35 ` Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 36/51] tcg: Remove CF_IGNORE_ICOUNT Richard Henderson
` (18 subsequent siblings)
53 siblings, 0 replies; 59+ messages in thread
From: Richard Henderson @ 2017-10-25 9:35 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
These flags are used by target/*/translate.c,
and affect code generation.
Reviewed-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/exec-all.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 0fdb72bb22..a3bd3e7abd 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -327,7 +327,8 @@ struct TranslationBlock {
#define CF_INVALID 0x80000 /* TB is stale. Setters must acquire tb_lock */
#define CF_PARALLEL 0x100000 /* Generate code for a parallel context */
/* cflags' mask for hashing/comparison */
-#define CF_HASH_MASK (CF_COUNT_MASK | CF_PARALLEL)
+#define CF_HASH_MASK \
+ (CF_COUNT_MASK | CF_LAST_IO | CF_USE_ICOUNT | CF_PARALLEL)
/* Per-vCPU dynamic tracing state used to generate this TB */
uint32_t trace_vcpu_dstate;
--
2.13.6
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [Qemu-devel] [PULL 36/51] tcg: Remove CF_IGNORE_ICOUNT
2017-10-25 9:34 [Qemu-devel] [PULL 00/51] tcg queued patches Richard Henderson
` (34 preceding siblings ...)
2017-10-25 9:35 ` [Qemu-devel] [PULL 35/51] tcg: Add CF_LAST_IO + CF_USE_ICOUNT to CF_HASH_MASK Richard Henderson
@ 2017-10-25 9:35 ` Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 37/51] translate-all: use a binary search tree to track TBs in TBContext Richard Henderson
` (17 subsequent siblings)
53 siblings, 0 replies; 59+ messages in thread
From: Richard Henderson @ 2017-10-25 9:35 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
Now that we have curr_cflags, we can include CF_USE_ICOUNT
early and then remove it as necessary.
Reviewed-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/exec-all.h | 17 +++++++++--------
accel/tcg/cpu-exec.c | 16 +++++++++-------
accel/tcg/translate-all.c | 3 ---
3 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index a3bd3e7abd..f14c6a56eb 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -22,6 +22,7 @@
#include "qemu-common.h"
#include "exec/tb-context.h"
+#include "sysemu/cpus.h"
/* allow to see translation results - the slowdown should be negligible, so we leave it */
#define DEBUG_DISAS
@@ -319,13 +320,12 @@ struct TranslationBlock {
size <= TARGET_PAGE_SIZE) */
uint16_t icount;
uint32_t cflags; /* compile flags */
-#define CF_COUNT_MASK 0x7fff
-#define CF_LAST_IO 0x8000 /* Last insn may be an IO access. */
-#define CF_NOCACHE 0x10000 /* To be freed after execution */
-#define CF_USE_ICOUNT 0x20000
-#define CF_IGNORE_ICOUNT 0x40000 /* Do not generate icount code */
-#define CF_INVALID 0x80000 /* TB is stale. Setters must acquire tb_lock */
-#define CF_PARALLEL 0x100000 /* Generate code for a parallel context */
+#define CF_COUNT_MASK 0x00007fff
+#define CF_LAST_IO 0x00008000 /* Last insn may be an IO access. */
+#define CF_NOCACHE 0x00010000 /* To be freed after execution */
+#define CF_USE_ICOUNT 0x00020000
+#define CF_INVALID 0x00040000 /* TB is stale. Setters need tb_lock */
+#define CF_PARALLEL 0x00080000 /* Generate code for a parallel context */
/* cflags' mask for hashing/comparison */
#define CF_HASH_MASK \
(CF_COUNT_MASK | CF_LAST_IO | CF_USE_ICOUNT | CF_PARALLEL)
@@ -380,7 +380,8 @@ static inline uint32_t tb_cflags(const TranslationBlock *tb)
/* current cflags for hashing/comparison */
static inline uint32_t curr_cflags(void)
{
- return parallel_cpus ? CF_PARALLEL : 0;
+ return (parallel_cpus ? CF_PARALLEL : 0)
+ | (use_icount ? CF_USE_ICOUNT : 0);
}
void tb_free(TranslationBlock *tb);
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 849b54d0b0..b44c7941aa 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -198,17 +198,19 @@ static void cpu_exec_nocache(CPUState *cpu, int max_cycles,
TranslationBlock *orig_tb, bool ignore_icount)
{
TranslationBlock *tb;
+ uint32_t cflags = curr_cflags() | CF_NOCACHE;
+
+ if (ignore_icount) {
+ cflags &= ~CF_USE_ICOUNT;
+ }
/* Should never happen.
We only end up here when an existing TB is too long. */
- if (max_cycles > CF_COUNT_MASK)
- max_cycles = CF_COUNT_MASK;
+ cflags |= MIN(max_cycles, CF_COUNT_MASK);
tb_lock();
- tb = tb_gen_code(cpu, orig_tb->pc, orig_tb->cs_base, orig_tb->flags,
- max_cycles | CF_NOCACHE
- | (ignore_icount ? CF_IGNORE_ICOUNT : 0)
- | curr_cflags());
+ tb = tb_gen_code(cpu, orig_tb->pc, orig_tb->cs_base,
+ orig_tb->flags, cflags);
tb->orig_tb = orig_tb;
tb_unlock();
@@ -229,7 +231,7 @@ void cpu_exec_step_atomic(CPUState *cpu)
TranslationBlock *tb;
target_ulong cs_base, pc;
uint32_t flags;
- uint32_t cflags = 1 | CF_IGNORE_ICOUNT;
+ uint32_t cflags = 1;
uint32_t cf_mask = cflags & CF_HASH_MASK;
if (sigsetjmp(cpu->jmp_env, 0) == 0) {
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index dcd47cd692..9fa94340dd 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -1274,9 +1274,6 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
assert_memory_lock();
phys_pc = get_page_addr_code(env, pc);
- if (use_icount && !(cflags & CF_IGNORE_ICOUNT)) {
- cflags |= CF_USE_ICOUNT;
- }
tb = tb_alloc(pc);
if (unlikely(!tb)) {
--
2.13.6
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [Qemu-devel] [PULL 37/51] translate-all: use a binary search tree to track TBs in TBContext
2017-10-25 9:34 [Qemu-devel] [PULL 00/51] tcg queued patches Richard Henderson
` (35 preceding siblings ...)
2017-10-25 9:35 ` [Qemu-devel] [PULL 36/51] tcg: Remove CF_IGNORE_ICOUNT Richard Henderson
@ 2017-10-25 9:35 ` Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 38/51] exec-all: rename tb_free to tb_remove Richard Henderson
` (16 subsequent siblings)
53 siblings, 0 replies; 59+ messages in thread
From: Richard Henderson @ 2017-10-25 9:35 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Emilio G. Cota
From: "Emilio G. Cota" <cota@braap.org>
This is a prerequisite for supporting multiple TCG contexts, since
we will have threads generating code in separate regions of
code_gen_buffer.
For this we need a new field (.size) in struct tb_tc to keep
track of the size of the translated code. This field uses a size_t
to avoid adding a hole to the struct, although really an unsigned
int would have been enough.
The comparison function we use is optimized for the common case:
insertions. Profiling shows that upon booting debian-arm, 98%
of comparisons are between existing tb's (i.e. a->size and b->size
are both !0), which happens during insertions (and removals, but
those are rare). The remaining cases are lookups. From reading the glib
sources we see that the first key is always the lookup key. However,
the code does not assume this to always be the case because this
behaviour is not guaranteed in the glib docs. However, we embed
this knowledge in the code as a branch hint for the compiler.
Note that tb_free does not free space in the code_gen_buffer anymore,
since we cannot easily know whether the tb is the last one inserted
in code_gen_buffer. The next patch in this series renames tb_free
to tb_remove to reflect this.
Performance-wise, lookups in tb_find_pc are the same as before:
O(log n). However, insertions are O(log n) instead of O(1), which
results in a small slowdown when booting debian-arm:
Performance counter stats for 'build/arm-softmmu/qemu-system-arm \
-machine type=virt -nographic -smp 1 -m 4096 \
-netdev user,id=unet,hostfwd=tcp::2222-:22 \
-device virtio-net-device,netdev=unet \
-drive file=img/arm/jessie-arm32.qcow2,id=myblock,index=0,if=none \
-device virtio-blk-device,drive=myblock \
-kernel img/arm/aarch32-current-linux-kernel-only.img \
-append console=ttyAMA0 root=/dev/vda1 \
-name arm,debug-threads=on -smp 1' (10 runs):
- Before:
8048.598422 task-clock (msec) # 0.931 CPUs utilized ( +- 0.28% )
16,974 context-switches # 0.002 M/sec ( +- 0.12% )
0 cpu-migrations # 0.000 K/sec
10,125 page-faults # 0.001 M/sec ( +- 1.23% )
35,144,901,879 cycles # 4.367 GHz ( +- 0.14% )
<not supported> stalled-cycles-frontend
<not supported> stalled-cycles-backend
65,758,252,643 instructions # 1.87 insns per cycle ( +- 0.33% )
10,871,298,668 branches # 1350.707 M/sec ( +- 0.41% )
192,322,212 branch-misses # 1.77% of all branches ( +- 0.32% )
8.640869419 seconds time elapsed ( +- 0.57% )
- After:
8146.242027 task-clock (msec) # 0.923 CPUs utilized ( +- 1.23% )
17,016 context-switches # 0.002 M/sec ( +- 0.40% )
0 cpu-migrations # 0.000 K/sec
18,769 page-faults # 0.002 M/sec ( +- 0.45% )
35,660,956,120 cycles # 4.378 GHz ( +- 1.22% )
<not supported> stalled-cycles-frontend
<not supported> stalled-cycles-backend
65,095,366,607 instructions # 1.83 insns per cycle ( +- 1.73% )
10,803,480,261 branches # 1326.192 M/sec ( +- 1.95% )
195,601,289 branch-misses # 1.81% of all branches ( +- 0.39% )
8.828660235 seconds time elapsed ( +- 0.38% )
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/exec-all.h | 6 +-
include/exec/tb-context.h | 4 +-
accel/tcg/translate-all.c | 221 ++++++++++++++++++++++++----------------------
3 files changed, 119 insertions(+), 112 deletions(-)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index f14c6a56eb..e2d598082e 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -306,10 +306,14 @@ static inline void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr)
/*
* Translation Cache-related fields of a TB.
+ * This struct exists just for convenience; we keep track of TB's in a binary
+ * search tree, and the only fields needed to compare TB's in the tree are
+ * @ptr and @size.
+ * Note: the address of search data can be obtained by adding @size to @ptr.
*/
struct tb_tc {
void *ptr; /* pointer to the translated code */
- uint8_t *search; /* pointer to search data */
+ size_t size;
};
struct TranslationBlock {
diff --git a/include/exec/tb-context.h b/include/exec/tb-context.h
index 25c2afe753..1fa8dcc737 100644
--- a/include/exec/tb-context.h
+++ b/include/exec/tb-context.h
@@ -31,10 +31,8 @@ typedef struct TBContext TBContext;
struct TBContext {
- TranslationBlock **tbs;
+ GTree *tb_tree;
struct qht htable;
- size_t tbs_size;
- int nb_tbs;
/* any access to the tbs or the page table must use this lock */
QemuMutex tb_lock;
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index 9fa94340dd..678e5ab61e 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -270,8 +270,6 @@ static int encode_search(TranslationBlock *tb, uint8_t *block)
uint8_t *p = block;
int i, j, n;
- tb->tc.search = block;
-
for (i = 0, n = tb->icount; i < n; ++i) {
target_ulong prev;
@@ -307,7 +305,7 @@ static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
target_ulong data[TARGET_INSN_START_WORDS] = { tb->pc };
uintptr_t host_pc = (uintptr_t)tb->tc.ptr;
CPUArchState *env = cpu->env_ptr;
- uint8_t *p = tb->tc.search;
+ uint8_t *p = tb->tc.ptr + tb->tc.size;
int i, j, num_insns = tb->icount;
#ifdef CONFIG_PROFILER
int64_t ti = profile_getclock();
@@ -776,6 +774,48 @@ static inline void *alloc_code_gen_buffer(void)
}
#endif /* USE_STATIC_CODE_GEN_BUFFER, WIN32, POSIX */
+/* compare a pointer @ptr and a tb_tc @s */
+static int ptr_cmp_tb_tc(const void *ptr, const struct tb_tc *s)
+{
+ if (ptr >= s->ptr + s->size) {
+ return 1;
+ } else if (ptr < s->ptr) {
+ return -1;
+ }
+ return 0;
+}
+
+static gint tb_tc_cmp(gconstpointer ap, gconstpointer bp)
+{
+ const struct tb_tc *a = ap;
+ const struct tb_tc *b = bp;
+
+ /*
+ * When both sizes are set, we know this isn't a lookup.
+ * This is the most likely case: every TB must be inserted; lookups
+ * are a lot less frequent.
+ */
+ if (likely(a->size && b->size)) {
+ if (a->ptr > b->ptr) {
+ return 1;
+ } else if (a->ptr < b->ptr) {
+ return -1;
+ }
+ /* a->ptr == b->ptr should happen only on deletions */
+ g_assert(a->size == b->size);
+ return 0;
+ }
+ /*
+ * All lookups have either .size field set to 0.
+ * From the glib sources we see that @ap is always the lookup key. However
+ * the docs provide no guarantee, so we just mark this case as likely.
+ */
+ if (likely(a->size == 0)) {
+ return ptr_cmp_tb_tc(a->ptr, b);
+ }
+ return ptr_cmp_tb_tc(b->ptr, a);
+}
+
static inline void code_gen_alloc(size_t tb_size)
{
tcg_ctx.code_gen_buffer_size = size_code_gen_buffer(tb_size);
@@ -784,15 +824,7 @@ static inline void code_gen_alloc(size_t tb_size)
fprintf(stderr, "Could not allocate dynamic translator buffer\n");
exit(1);
}
-
- /* size this conservatively -- realloc later if needed */
- tcg_ctx.tb_ctx.tbs_size =
- tcg_ctx.code_gen_buffer_size / CODE_GEN_AVG_BLOCK_SIZE / 8;
- if (unlikely(!tcg_ctx.tb_ctx.tbs_size)) {
- tcg_ctx.tb_ctx.tbs_size = 64 * 1024;
- }
- tcg_ctx.tb_ctx.tbs = g_new(TranslationBlock *, tcg_ctx.tb_ctx.tbs_size);
-
+ tcg_ctx.tb_ctx.tb_tree = g_tree_new(tb_tc_cmp);
qemu_mutex_init(&tcg_ctx.tb_ctx.tb_lock);
}
@@ -829,7 +861,6 @@ void tcg_exec_init(unsigned long tb_size)
static TranslationBlock *tb_alloc(target_ulong pc)
{
TranslationBlock *tb;
- TBContext *ctx;
assert_tb_locked();
@@ -837,12 +868,6 @@ static TranslationBlock *tb_alloc(target_ulong pc)
if (unlikely(tb == NULL)) {
return NULL;
}
- ctx = &tcg_ctx.tb_ctx;
- if (unlikely(ctx->nb_tbs == ctx->tbs_size)) {
- ctx->tbs_size *= 2;
- ctx->tbs = g_renew(TranslationBlock *, ctx->tbs, ctx->tbs_size);
- }
- ctx->tbs[ctx->nb_tbs++] = tb;
return tb;
}
@@ -851,16 +876,7 @@ void tb_free(TranslationBlock *tb)
{
assert_tb_locked();
- /* In practice this is mostly used for single use temporary TB
- Ignore the hard cases and just back up if this TB happens to
- be the last one generated. */
- if (tcg_ctx.tb_ctx.nb_tbs > 0 &&
- tb == tcg_ctx.tb_ctx.tbs[tcg_ctx.tb_ctx.nb_tbs - 1]) {
- size_t struct_size = ROUND_UP(sizeof(*tb), qemu_icache_linesize);
-
- tcg_ctx.code_gen_ptr = tb->tc.ptr - struct_size;
- tcg_ctx.tb_ctx.nb_tbs--;
- }
+ g_tree_remove(tcg_ctx.tb_ctx.tb_tree, &tb->tc);
}
static inline void invalidate_page_bitmap(PageDesc *p)
@@ -918,11 +934,12 @@ static void do_tb_flush(CPUState *cpu, run_on_cpu_data tb_flush_count)
}
if (DEBUG_TB_FLUSH_GATE) {
- printf("qemu: flush code_size=%td nb_tbs=%d avg_tb_size=%td\n",
- tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer,
- tcg_ctx.tb_ctx.nb_tbs, tcg_ctx.tb_ctx.nb_tbs > 0 ?
- (tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer) /
- tcg_ctx.tb_ctx.nb_tbs : 0);
+ size_t nb_tbs = g_tree_nnodes(tcg_ctx.tb_ctx.tb_tree);
+
+ printf("qemu: flush code_size=%td nb_tbs=%zu avg_tb_size=%td\n",
+ tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer, nb_tbs,
+ nb_tbs > 0 ?
+ (tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer) / nb_tbs : 0);
}
if ((unsigned long)(tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer)
> tcg_ctx.code_gen_buffer_size) {
@@ -933,7 +950,10 @@ static void do_tb_flush(CPUState *cpu, run_on_cpu_data tb_flush_count)
cpu_tb_jmp_cache_clear(cpu);
}
- tcg_ctx.tb_ctx.nb_tbs = 0;
+ /* Increment the refcount first so that destroy acts as a reset */
+ g_tree_ref(tcg_ctx.tb_ctx.tb_tree);
+ g_tree_destroy(tcg_ctx.tb_ctx.tb_tree);
+
qht_reset_size(&tcg_ctx.tb_ctx.htable, CODE_GEN_HTABLE_SIZE);
page_flush_tb();
@@ -1340,6 +1360,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
if (unlikely(search_size < 0)) {
goto buffer_overflow;
}
+ tb->tc.size = gen_code_size;
#ifdef CONFIG_PROFILER
tcg_ctx.code_time += profile_getclock() - ti;
@@ -1410,6 +1431,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
* through the physical hash table and physical page list.
*/
tb_link_page(tb, phys_pc, phys_page2);
+ g_tree_insert(tcg_ctx.tb_ctx.tb_tree, &tb->tc, tb);
return tb;
}
@@ -1672,37 +1694,16 @@ static bool tb_invalidate_phys_page(tb_page_addr_t addr, uintptr_t pc)
}
#endif
-/* find the TB 'tb' such that tb[0].tc_ptr <= tc_ptr <
- tb[1].tc_ptr. Return NULL if not found */
+/*
+ * Find the TB 'tb' such that
+ * tb->tc.ptr <= tc_ptr < tb->tc.ptr + tb->tc.size
+ * Return NULL if not found.
+ */
static TranslationBlock *tb_find_pc(uintptr_t tc_ptr)
{
- int m_min, m_max, m;
- uintptr_t v;
- TranslationBlock *tb;
+ struct tb_tc s = { .ptr = (void *)tc_ptr };
- if (tcg_ctx.tb_ctx.nb_tbs <= 0) {
- return NULL;
- }
- if (tc_ptr < (uintptr_t)tcg_ctx.code_gen_buffer ||
- tc_ptr >= (uintptr_t)tcg_ctx.code_gen_ptr) {
- return NULL;
- }
- /* binary search (cf Knuth) */
- m_min = 0;
- m_max = tcg_ctx.tb_ctx.nb_tbs - 1;
- while (m_min <= m_max) {
- m = (m_min + m_max) >> 1;
- tb = tcg_ctx.tb_ctx.tbs[m];
- v = (uintptr_t)tb->tc.ptr;
- if (v == tc_ptr) {
- return tb;
- } else if (tc_ptr < v) {
- m_max = m - 1;
- } else {
- m_min = m + 1;
- }
- }
- return tcg_ctx.tb_ctx.tbs[m_max];
+ return g_tree_lookup(tcg_ctx.tb_ctx.tb_tree, &s);
}
#if !defined(CONFIG_USER_ONLY)
@@ -1880,63 +1881,67 @@ static void print_qht_statistics(FILE *f, fprintf_function cpu_fprintf,
g_free(hgram);
}
+struct tb_tree_stats {
+ size_t target_size;
+ size_t max_target_size;
+ size_t direct_jmp_count;
+ size_t direct_jmp2_count;
+ size_t cross_page;
+};
+
+static gboolean tb_tree_stats_iter(gpointer key, gpointer value, gpointer data)
+{
+ const TranslationBlock *tb = value;
+ struct tb_tree_stats *tst = data;
+
+ tst->target_size += tb->size;
+ if (tb->size > tst->max_target_size) {
+ tst->max_target_size = tb->size;
+ }
+ if (tb->page_addr[1] != -1) {
+ tst->cross_page++;
+ }
+ if (tb->jmp_reset_offset[0] != TB_JMP_RESET_OFFSET_INVALID) {
+ tst->direct_jmp_count++;
+ if (tb->jmp_reset_offset[1] != TB_JMP_RESET_OFFSET_INVALID) {
+ tst->direct_jmp2_count++;
+ }
+ }
+ return false;
+}
+
void dump_exec_info(FILE *f, fprintf_function cpu_fprintf)
{
- int i, target_code_size, max_target_code_size;
- int direct_jmp_count, direct_jmp2_count, cross_page;
- TranslationBlock *tb;
+ struct tb_tree_stats tst = {};
struct qht_stats hst;
+ size_t nb_tbs;
tb_lock();
- target_code_size = 0;
- max_target_code_size = 0;
- cross_page = 0;
- direct_jmp_count = 0;
- direct_jmp2_count = 0;
- for (i = 0; i < tcg_ctx.tb_ctx.nb_tbs; i++) {
- tb = tcg_ctx.tb_ctx.tbs[i];
- target_code_size += tb->size;
- if (tb->size > max_target_code_size) {
- max_target_code_size = tb->size;
- }
- if (tb->page_addr[1] != -1) {
- cross_page++;
- }
- if (tb->jmp_reset_offset[0] != TB_JMP_RESET_OFFSET_INVALID) {
- direct_jmp_count++;
- if (tb->jmp_reset_offset[1] != TB_JMP_RESET_OFFSET_INVALID) {
- direct_jmp2_count++;
- }
- }
- }
+ nb_tbs = g_tree_nnodes(tcg_ctx.tb_ctx.tb_tree);
+ g_tree_foreach(tcg_ctx.tb_ctx.tb_tree, tb_tree_stats_iter, &tst);
/* XXX: avoid using doubles ? */
cpu_fprintf(f, "Translation buffer state:\n");
cpu_fprintf(f, "gen code size %td/%zd\n",
tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer,
tcg_ctx.code_gen_highwater - tcg_ctx.code_gen_buffer);
- cpu_fprintf(f, "TB count %d\n", tcg_ctx.tb_ctx.nb_tbs);
- cpu_fprintf(f, "TB avg target size %d max=%d bytes\n",
- tcg_ctx.tb_ctx.nb_tbs ? target_code_size /
- tcg_ctx.tb_ctx.nb_tbs : 0,
- max_target_code_size);
+ cpu_fprintf(f, "TB count %zu\n", nb_tbs);
+ cpu_fprintf(f, "TB avg target size %zu max=%zu bytes\n",
+ nb_tbs ? tst.target_size / nb_tbs : 0,
+ tst.max_target_size);
cpu_fprintf(f, "TB avg host size %td bytes (expansion ratio: %0.1f)\n",
- tcg_ctx.tb_ctx.nb_tbs ? (tcg_ctx.code_gen_ptr -
- tcg_ctx.code_gen_buffer) /
- tcg_ctx.tb_ctx.nb_tbs : 0,
- target_code_size ? (double) (tcg_ctx.code_gen_ptr -
- tcg_ctx.code_gen_buffer) /
- target_code_size : 0);
- cpu_fprintf(f, "cross page TB count %d (%d%%)\n", cross_page,
- tcg_ctx.tb_ctx.nb_tbs ? (cross_page * 100) /
- tcg_ctx.tb_ctx.nb_tbs : 0);
- cpu_fprintf(f, "direct jump count %d (%d%%) (2 jumps=%d %d%%)\n",
- direct_jmp_count,
- tcg_ctx.tb_ctx.nb_tbs ? (direct_jmp_count * 100) /
- tcg_ctx.tb_ctx.nb_tbs : 0,
- direct_jmp2_count,
- tcg_ctx.tb_ctx.nb_tbs ? (direct_jmp2_count * 100) /
- tcg_ctx.tb_ctx.nb_tbs : 0);
+ nb_tbs ? (tcg_ctx.code_gen_ptr -
+ tcg_ctx.code_gen_buffer) / nb_tbs : 0,
+ tst.target_size ? (double) (tcg_ctx.code_gen_ptr -
+ tcg_ctx.code_gen_buffer) /
+ tst.target_size : 0);
+ cpu_fprintf(f, "cross page TB count %zu (%zu%%)\n", tst.cross_page,
+ nb_tbs ? (tst.cross_page * 100) / nb_tbs : 0);
+ cpu_fprintf(f, "direct jump count %zu (%zu%%) (2 jumps=%zu %zu%%)\n",
+ tst.direct_jmp_count,
+ nb_tbs ? (tst.direct_jmp_count * 100) / nb_tbs : 0,
+ tst.direct_jmp2_count,
+ nb_tbs ? (tst.direct_jmp2_count * 100) / nb_tbs : 0);
qht_statistics_init(&tcg_ctx.tb_ctx.htable, &hst);
print_qht_statistics(f, cpu_fprintf, hst);
--
2.13.6
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [Qemu-devel] [PULL 38/51] exec-all: rename tb_free to tb_remove
2017-10-25 9:34 [Qemu-devel] [PULL 00/51] tcg queued patches Richard Henderson
` (36 preceding siblings ...)
2017-10-25 9:35 ` [Qemu-devel] [PULL 37/51] translate-all: use a binary search tree to track TBs in TBContext Richard Henderson
@ 2017-10-25 9:35 ` Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 39/51] translate-all: report correct avg host TB size Richard Henderson
` (15 subsequent siblings)
53 siblings, 0 replies; 59+ messages in thread
From: Richard Henderson @ 2017-10-25 9:35 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Emilio G. Cota
From: "Emilio G. Cota" <cota@braap.org>
We don't really free anything in this function anymore; we just remove
the TB from the binary search tree.
Suggested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/exec-all.h | 2 +-
accel/tcg/cpu-exec.c | 2 +-
accel/tcg/translate-all.c | 6 +++---
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index e2d598082e..923ece3e9b 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -388,7 +388,7 @@ static inline uint32_t curr_cflags(void)
| (use_icount ? CF_USE_ICOUNT : 0);
}
-void tb_free(TranslationBlock *tb);
+void tb_remove(TranslationBlock *tb);
void tb_flush(CPUState *cpu);
void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr);
TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc,
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index b44c7941aa..9b58cdee28 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -220,7 +220,7 @@ static void cpu_exec_nocache(CPUState *cpu, int max_cycles,
tb_lock();
tb_phys_invalidate(tb, -1);
- tb_free(tb);
+ tb_remove(tb);
tb_unlock();
}
#endif
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index 678e5ab61e..e929ccb30b 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -373,7 +373,7 @@ bool cpu_restore_state(CPUState *cpu, uintptr_t retaddr)
if (tb->cflags & CF_NOCACHE) {
/* one-shot translation, invalidate it immediately */
tb_phys_invalidate(tb, -1);
- tb_free(tb);
+ tb_remove(tb);
}
r = true;
}
@@ -872,7 +872,7 @@ static TranslationBlock *tb_alloc(target_ulong pc)
}
/* Called with tb_lock held. */
-void tb_free(TranslationBlock *tb)
+void tb_remove(TranslationBlock *tb)
{
assert_tb_locked();
@@ -1811,7 +1811,7 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr)
* cpu_exec_nocache() */
tb_phys_invalidate(tb->orig_tb, -1);
}
- tb_free(tb);
+ tb_remove(tb);
}
/* TODO: If env->pc != tb->pc (i.e. the faulting instruction was not
--
2.13.6
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [Qemu-devel] [PULL 39/51] translate-all: report correct avg host TB size
2017-10-25 9:34 [Qemu-devel] [PULL 00/51] tcg queued patches Richard Henderson
` (37 preceding siblings ...)
2017-10-25 9:35 ` [Qemu-devel] [PULL 38/51] exec-all: rename tb_free to tb_remove Richard Henderson
@ 2017-10-25 9:35 ` Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 40/51] tcg: take tb_ctx out of TCGContext Richard Henderson
` (14 subsequent siblings)
53 siblings, 0 replies; 59+ messages in thread
From: Richard Henderson @ 2017-10-25 9:35 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Emilio G. Cota
From: "Emilio G. Cota" <cota@braap.org>
Since commit 6e3b2bfd6 ("tcg: allocate TB structs before the
corresponding translated code") we are not fully utilizing
code_gen_buffer for translated code, and therefore are
incorrectly reporting the amount of translated code as well as
the average host TB size. Address this by:
- Making the conscious choice of misreporting the total translated code;
doing otherwise would mislead users into thinking "-tb-size" is not
honoured.
- Expanding tb_tree_stats to accurately count the bytes of translated code on
the host, and using this for reporting the average tb host size,
as well as the expansion ratio.
In the future we might want to consider reporting the accurate numbers for
the total translated code, together with a "bookkeeping/overhead" field to
account for the TB structs.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/translate-all.c | 32 +++++++++++++++++++++++---------
1 file changed, 23 insertions(+), 9 deletions(-)
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index e929ccb30b..7e2c0cdb98 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -921,6 +921,15 @@ static void page_flush_tb(void)
}
}
+static gboolean tb_host_size_iter(gpointer key, gpointer value, gpointer data)
+{
+ const TranslationBlock *tb = value;
+ size_t *size = data;
+
+ *size += tb->tc.size;
+ return false;
+}
+
/* flush all the translation blocks */
static void do_tb_flush(CPUState *cpu, run_on_cpu_data tb_flush_count)
{
@@ -935,11 +944,12 @@ static void do_tb_flush(CPUState *cpu, run_on_cpu_data tb_flush_count)
if (DEBUG_TB_FLUSH_GATE) {
size_t nb_tbs = g_tree_nnodes(tcg_ctx.tb_ctx.tb_tree);
+ size_t host_size = 0;
- printf("qemu: flush code_size=%td nb_tbs=%zu avg_tb_size=%td\n",
+ g_tree_foreach(tcg_ctx.tb_ctx.tb_tree, tb_host_size_iter, &host_size);
+ printf("qemu: flush code_size=%td nb_tbs=%zu avg_tb_size=%zu\n",
tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer, nb_tbs,
- nb_tbs > 0 ?
- (tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer) / nb_tbs : 0);
+ nb_tbs > 0 ? host_size / nb_tbs : 0);
}
if ((unsigned long)(tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer)
> tcg_ctx.code_gen_buffer_size) {
@@ -1882,6 +1892,7 @@ static void print_qht_statistics(FILE *f, fprintf_function cpu_fprintf,
}
struct tb_tree_stats {
+ size_t host_size;
size_t target_size;
size_t max_target_size;
size_t direct_jmp_count;
@@ -1894,6 +1905,7 @@ static gboolean tb_tree_stats_iter(gpointer key, gpointer value, gpointer data)
const TranslationBlock *tb = value;
struct tb_tree_stats *tst = data;
+ tst->host_size += tb->tc.size;
tst->target_size += tb->size;
if (tb->size > tst->max_target_size) {
tst->max_target_size = tb->size;
@@ -1922,6 +1934,11 @@ void dump_exec_info(FILE *f, fprintf_function cpu_fprintf)
g_tree_foreach(tcg_ctx.tb_ctx.tb_tree, tb_tree_stats_iter, &tst);
/* XXX: avoid using doubles ? */
cpu_fprintf(f, "Translation buffer state:\n");
+ /*
+ * Report total code size including the padding and TB structs;
+ * otherwise users might think "-tb-size" is not honoured.
+ * For avg host size we use the precise numbers from tb_tree_stats though.
+ */
cpu_fprintf(f, "gen code size %td/%zd\n",
tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer,
tcg_ctx.code_gen_highwater - tcg_ctx.code_gen_buffer);
@@ -1929,12 +1946,9 @@ void dump_exec_info(FILE *f, fprintf_function cpu_fprintf)
cpu_fprintf(f, "TB avg target size %zu max=%zu bytes\n",
nb_tbs ? tst.target_size / nb_tbs : 0,
tst.max_target_size);
- cpu_fprintf(f, "TB avg host size %td bytes (expansion ratio: %0.1f)\n",
- nb_tbs ? (tcg_ctx.code_gen_ptr -
- tcg_ctx.code_gen_buffer) / nb_tbs : 0,
- tst.target_size ? (double) (tcg_ctx.code_gen_ptr -
- tcg_ctx.code_gen_buffer) /
- tst.target_size : 0);
+ cpu_fprintf(f, "TB avg host size %zu bytes (expansion ratio: %0.1f)\n",
+ nb_tbs ? tst.host_size / nb_tbs : 0,
+ tst.target_size ? (double)tst.host_size / tst.target_size : 0);
cpu_fprintf(f, "cross page TB count %zu (%zu%%)\n", tst.cross_page,
nb_tbs ? (tst.cross_page * 100) / nb_tbs : 0);
cpu_fprintf(f, "direct jump count %zu (%zu%%) (2 jumps=%zu %zu%%)\n",
--
2.13.6
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [Qemu-devel] [PULL 40/51] tcg: take tb_ctx out of TCGContext
2017-10-25 9:34 [Qemu-devel] [PULL 00/51] tcg queued patches Richard Henderson
` (38 preceding siblings ...)
2017-10-25 9:35 ` [Qemu-devel] [PULL 39/51] translate-all: report correct avg host TB size Richard Henderson
@ 2017-10-25 9:35 ` Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 41/51] tcg: define tcg_init_ctx and make tcg_ctx a pointer Richard Henderson
` (13 subsequent siblings)
53 siblings, 0 replies; 59+ messages in thread
From: Richard Henderson @ 2017-10-25 9:35 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Emilio G. Cota
From: "Emilio G. Cota" <cota@braap.org>
Groundwork for supporting multiple TCG contexts.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/tb-context.h | 2 ++
tcg/tcg.h | 2 --
accel/tcg/cpu-exec.c | 2 +-
accel/tcg/translate-all.c | 57 +++++++++++++++++++++++------------------------
linux-user/main.c | 6 ++---
5 files changed, 34 insertions(+), 35 deletions(-)
diff --git a/include/exec/tb-context.h b/include/exec/tb-context.h
index 1fa8dcc737..1d41202485 100644
--- a/include/exec/tb-context.h
+++ b/include/exec/tb-context.h
@@ -41,4 +41,6 @@ struct TBContext {
int tb_phys_invalidate_count;
};
+extern TBContext tb_ctx;
+
#endif
diff --git a/tcg/tcg.h b/tcg/tcg.h
index 7c39eac428..76324c9ad6 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -663,8 +663,6 @@ struct TCGContext {
/* Threshold to flush the translated code buffer. */
void *code_gen_highwater;
- TBContext tb_ctx;
-
/* Track which vCPU triggers events */
CPUState *cpu; /* *_trans */
TCGv_env tcg_env; /* *_exec */
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 9b58cdee28..4318441e4c 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -327,7 +327,7 @@ TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc,
phys_pc = get_page_addr_code(desc.env, pc);
desc.phys_page1 = phys_pc & TARGET_PAGE_MASK;
h = tb_hash_func(phys_pc, pc, flags, cf_mask, *cpu->trace_dstate);
- return qht_lookup(&tcg_ctx.tb_ctx.htable, tb_cmp, &desc, h);
+ return qht_lookup(&tb_ctx.htable, tb_cmp, &desc, h);
}
void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr)
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index 7e2c0cdb98..b238b724a8 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -154,6 +154,7 @@ static void *l1_map[V_L1_MAX_SIZE];
/* code generation context */
TCGContext tcg_ctx;
+TBContext tb_ctx;
bool parallel_cpus;
/* translation block context */
@@ -185,7 +186,7 @@ static void page_table_config_init(void)
void tb_lock(void)
{
assert_tb_unlocked();
- qemu_mutex_lock(&tcg_ctx.tb_ctx.tb_lock);
+ qemu_mutex_lock(&tb_ctx.tb_lock);
have_tb_lock++;
}
@@ -193,13 +194,13 @@ void tb_unlock(void)
{
assert_tb_locked();
have_tb_lock--;
- qemu_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock);
+ qemu_mutex_unlock(&tb_ctx.tb_lock);
}
void tb_lock_reset(void)
{
if (have_tb_lock) {
- qemu_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock);
+ qemu_mutex_unlock(&tb_ctx.tb_lock);
have_tb_lock = 0;
}
}
@@ -824,15 +825,15 @@ static inline void code_gen_alloc(size_t tb_size)
fprintf(stderr, "Could not allocate dynamic translator buffer\n");
exit(1);
}
- tcg_ctx.tb_ctx.tb_tree = g_tree_new(tb_tc_cmp);
- qemu_mutex_init(&tcg_ctx.tb_ctx.tb_lock);
+ tb_ctx.tb_tree = g_tree_new(tb_tc_cmp);
+ qemu_mutex_init(&tb_ctx.tb_lock);
}
static void tb_htable_init(void)
{
unsigned int mode = QHT_MODE_AUTO_RESIZE;
- qht_init(&tcg_ctx.tb_ctx.htable, CODE_GEN_HTABLE_SIZE, mode);
+ qht_init(&tb_ctx.htable, CODE_GEN_HTABLE_SIZE, mode);
}
/* Must be called before using the QEMU cpus. 'tb_size' is the size
@@ -876,7 +877,7 @@ void tb_remove(TranslationBlock *tb)
{
assert_tb_locked();
- g_tree_remove(tcg_ctx.tb_ctx.tb_tree, &tb->tc);
+ g_tree_remove(tb_ctx.tb_tree, &tb->tc);
}
static inline void invalidate_page_bitmap(PageDesc *p)
@@ -938,15 +939,15 @@ static void do_tb_flush(CPUState *cpu, run_on_cpu_data tb_flush_count)
/* If it is already been done on request of another CPU,
* just retry.
*/
- if (tcg_ctx.tb_ctx.tb_flush_count != tb_flush_count.host_int) {
+ if (tb_ctx.tb_flush_count != tb_flush_count.host_int) {
goto done;
}
if (DEBUG_TB_FLUSH_GATE) {
- size_t nb_tbs = g_tree_nnodes(tcg_ctx.tb_ctx.tb_tree);
+ size_t nb_tbs = g_tree_nnodes(tb_ctx.tb_tree);
size_t host_size = 0;
- g_tree_foreach(tcg_ctx.tb_ctx.tb_tree, tb_host_size_iter, &host_size);
+ g_tree_foreach(tb_ctx.tb_tree, tb_host_size_iter, &host_size);
printf("qemu: flush code_size=%td nb_tbs=%zu avg_tb_size=%zu\n",
tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer, nb_tbs,
nb_tbs > 0 ? host_size / nb_tbs : 0);
@@ -961,17 +962,16 @@ static void do_tb_flush(CPUState *cpu, run_on_cpu_data tb_flush_count)
}
/* Increment the refcount first so that destroy acts as a reset */
- g_tree_ref(tcg_ctx.tb_ctx.tb_tree);
- g_tree_destroy(tcg_ctx.tb_ctx.tb_tree);
+ g_tree_ref(tb_ctx.tb_tree);
+ g_tree_destroy(tb_ctx.tb_tree);
- qht_reset_size(&tcg_ctx.tb_ctx.htable, CODE_GEN_HTABLE_SIZE);
+ qht_reset_size(&tb_ctx.htable, CODE_GEN_HTABLE_SIZE);
page_flush_tb();
tcg_ctx.code_gen_ptr = tcg_ctx.code_gen_buffer;
/* XXX: flush processor icache at this point if cache flush is
expensive */
- atomic_mb_set(&tcg_ctx.tb_ctx.tb_flush_count,
- tcg_ctx.tb_ctx.tb_flush_count + 1);
+ atomic_mb_set(&tb_ctx.tb_flush_count, tb_ctx.tb_flush_count + 1);
done:
tb_unlock();
@@ -980,7 +980,7 @@ done:
void tb_flush(CPUState *cpu)
{
if (tcg_enabled()) {
- unsigned tb_flush_count = atomic_mb_read(&tcg_ctx.tb_ctx.tb_flush_count);
+ unsigned tb_flush_count = atomic_mb_read(&tb_ctx.tb_flush_count);
async_safe_run_on_cpu(cpu, do_tb_flush,
RUN_ON_CPU_HOST_INT(tb_flush_count));
}
@@ -1013,7 +1013,7 @@ do_tb_invalidate_check(struct qht *ht, void *p, uint32_t hash, void *userp)
static void tb_invalidate_check(target_ulong address)
{
address &= TARGET_PAGE_MASK;
- qht_iter(&tcg_ctx.tb_ctx.htable, do_tb_invalidate_check, &address);
+ qht_iter(&tb_ctx.htable, do_tb_invalidate_check, &address);
}
static void
@@ -1033,7 +1033,7 @@ do_tb_page_check(struct qht *ht, void *p, uint32_t hash, void *userp)
/* verify that all the pages have correct rights for code */
static void tb_page_check(void)
{
- qht_iter(&tcg_ctx.tb_ctx.htable, do_tb_page_check, NULL);
+ qht_iter(&tb_ctx.htable, do_tb_page_check, NULL);
}
#endif /* CONFIG_USER_ONLY */
@@ -1133,7 +1133,7 @@ void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr)
phys_pc = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK);
h = tb_hash_func(phys_pc, tb->pc, tb->flags, tb->cflags & CF_HASH_MASK,
tb->trace_vcpu_dstate);
- qht_remove(&tcg_ctx.tb_ctx.htable, tb, h);
+ qht_remove(&tb_ctx.htable, tb, h);
/* remove the TB from the page list */
if (tb->page_addr[0] != page_addr) {
@@ -1162,7 +1162,7 @@ void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr)
/* suppress any remaining jumps to this TB */
tb_jmp_unlink(tb);
- tcg_ctx.tb_ctx.tb_phys_invalidate_count++;
+ tb_ctx.tb_phys_invalidate_count++;
}
#ifdef CONFIG_SOFTMMU
@@ -1278,7 +1278,7 @@ static void tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc,
/* add in the hash table */
h = tb_hash_func(phys_pc, tb->pc, tb->flags, tb->cflags & CF_HASH_MASK,
tb->trace_vcpu_dstate);
- qht_insert(&tcg_ctx.tb_ctx.htable, tb, h);
+ qht_insert(&tb_ctx.htable, tb, h);
#ifdef CONFIG_USER_ONLY
if (DEBUG_TB_CHECK_GATE) {
@@ -1441,7 +1441,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
* through the physical hash table and physical page list.
*/
tb_link_page(tb, phys_pc, phys_page2);
- g_tree_insert(tcg_ctx.tb_ctx.tb_tree, &tb->tc, tb);
+ g_tree_insert(tb_ctx.tb_tree, &tb->tc, tb);
return tb;
}
@@ -1713,7 +1713,7 @@ static TranslationBlock *tb_find_pc(uintptr_t tc_ptr)
{
struct tb_tc s = { .ptr = (void *)tc_ptr };
- return g_tree_lookup(tcg_ctx.tb_ctx.tb_tree, &s);
+ return g_tree_lookup(tb_ctx.tb_tree, &s);
}
#if !defined(CONFIG_USER_ONLY)
@@ -1930,8 +1930,8 @@ void dump_exec_info(FILE *f, fprintf_function cpu_fprintf)
tb_lock();
- nb_tbs = g_tree_nnodes(tcg_ctx.tb_ctx.tb_tree);
- g_tree_foreach(tcg_ctx.tb_ctx.tb_tree, tb_tree_stats_iter, &tst);
+ nb_tbs = g_tree_nnodes(tb_ctx.tb_tree);
+ g_tree_foreach(tb_ctx.tb_tree, tb_tree_stats_iter, &tst);
/* XXX: avoid using doubles ? */
cpu_fprintf(f, "Translation buffer state:\n");
/*
@@ -1957,15 +1957,14 @@ void dump_exec_info(FILE *f, fprintf_function cpu_fprintf)
tst.direct_jmp2_count,
nb_tbs ? (tst.direct_jmp2_count * 100) / nb_tbs : 0);
- qht_statistics_init(&tcg_ctx.tb_ctx.htable, &hst);
+ qht_statistics_init(&tb_ctx.htable, &hst);
print_qht_statistics(f, cpu_fprintf, hst);
qht_statistics_destroy(&hst);
cpu_fprintf(f, "\nStatistics:\n");
cpu_fprintf(f, "TB flush count %u\n",
- atomic_read(&tcg_ctx.tb_ctx.tb_flush_count));
- cpu_fprintf(f, "TB invalidate count %d\n",
- tcg_ctx.tb_ctx.tb_phys_invalidate_count);
+ atomic_read(&tb_ctx.tb_flush_count));
+ cpu_fprintf(f, "TB invalidate count %d\n", tb_ctx.tb_phys_invalidate_count);
cpu_fprintf(f, "TLB flush count %zu\n", tlb_flush_count());
tcg_dump_info(f, cpu_fprintf);
diff --git a/linux-user/main.c b/linux-user/main.c
index dde04c769a..0a2a0d75b3 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -129,7 +129,7 @@ int cpu_get_pic_interrupt(CPUX86State *env)
void fork_start(void)
{
cpu_list_lock();
- qemu_mutex_lock(&tcg_ctx.tb_ctx.tb_lock);
+ qemu_mutex_lock(&tb_ctx.tb_lock);
mmap_fork_start();
}
@@ -145,11 +145,11 @@ void fork_end(int child)
QTAILQ_REMOVE(&cpus, cpu, node);
}
}
- qemu_mutex_init(&tcg_ctx.tb_ctx.tb_lock);
+ qemu_mutex_init(&tb_ctx.tb_lock);
qemu_init_cpu_list();
gdbserver_fork(thread_cpu);
} else {
- qemu_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock);
+ qemu_mutex_unlock(&tb_ctx.tb_lock);
cpu_list_unlock();
}
}
--
2.13.6
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [Qemu-devel] [PULL 41/51] tcg: define tcg_init_ctx and make tcg_ctx a pointer
2017-10-25 9:34 [Qemu-devel] [PULL 00/51] tcg queued patches Richard Henderson
` (39 preceding siblings ...)
2017-10-25 9:35 ` [Qemu-devel] [PULL 40/51] tcg: take tb_ctx out of TCGContext Richard Henderson
@ 2017-10-25 9:35 ` Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 42/51] gen-icount: fold exitreq_label into TCGContext Richard Henderson
` (12 subsequent siblings)
53 siblings, 0 replies; 59+ messages in thread
From: Richard Henderson @ 2017-10-25 9:35 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Emilio G. Cota
From: "Emilio G. Cota" <cota@braap.org>
Groundwork for supporting multiple TCG contexts.
The core of this patch is this change to tcg/tcg.h:
> -extern TCGContext tcg_ctx;
> +extern TCGContext tcg_init_ctx;
> +extern TCGContext *tcg_ctx;
Note that for now we set *tcg_ctx to whatever TCGContext is passed
to tcg_context_init -- in this case &tcg_init_ctx.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/gen-icount.h | 10 ++--
tcg/tcg.h | 21 ++++----
accel/tcg/tcg-runtime.c | 2 +-
accel/tcg/translate-all.c | 109 +++++++++++++++++++++---------------------
bsd-user/main.c | 2 +-
linux-user/main.c | 2 +-
target/alpha/translate.c | 2 +-
target/arm/translate.c | 2 +-
target/cris/translate.c | 2 +-
target/cris/translate_v10.c | 2 +-
target/hppa/translate.c | 2 +-
target/i386/translate.c | 2 +-
target/lm32/translate.c | 2 +-
target/m68k/translate.c | 2 +-
target/microblaze/translate.c | 2 +-
target/mips/translate.c | 2 +-
target/moxie/translate.c | 2 +-
target/nios2/translate.c | 2 +-
target/openrisc/translate.c | 2 +-
target/ppc/translate.c | 2 +-
target/s390x/translate.c | 2 +-
target/sh4/translate.c | 2 +-
target/sparc/translate.c | 2 +-
target/tilegx/translate.c | 2 +-
target/tricore/translate.c | 2 +-
target/unicore32/translate.c | 2 +-
target/xtensa/translate.c | 2 +-
tcg/tcg-op.c | 46 +++++++++---------
tcg/tcg.c | 22 +++++----
29 files changed, 130 insertions(+), 126 deletions(-)
diff --git a/include/exec/gen-icount.h b/include/exec/gen-icount.h
index 48b566c1c9..c58b0b2585 100644
--- a/include/exec/gen-icount.h
+++ b/include/exec/gen-icount.h
@@ -19,7 +19,7 @@ static inline void gen_tb_start(TranslationBlock *tb)
count = tcg_temp_new_i32();
}
- tcg_gen_ld_i32(count, tcg_ctx.tcg_env,
+ tcg_gen_ld_i32(count, tcg_ctx->tcg_env,
-ENV_OFFSET + offsetof(CPUState, icount_decr.u32));
if (tb_cflags(tb) & CF_USE_ICOUNT) {
@@ -37,7 +37,7 @@ static inline void gen_tb_start(TranslationBlock *tb)
tcg_gen_brcondi_i32(TCG_COND_LT, count, 0, exitreq_label);
if (tb_cflags(tb) & CF_USE_ICOUNT) {
- tcg_gen_st16_i32(count, tcg_ctx.tcg_env,
+ tcg_gen_st16_i32(count, tcg_ctx->tcg_env,
-ENV_OFFSET + offsetof(CPUState, icount_decr.u16.low));
}
@@ -56,13 +56,13 @@ static inline void gen_tb_end(TranslationBlock *tb, int num_insns)
tcg_gen_exit_tb((uintptr_t)tb + TB_EXIT_REQUESTED);
/* Terminate the linked list. */
- tcg_ctx.gen_op_buf[tcg_ctx.gen_op_buf[0].prev].next = 0;
+ tcg_ctx->gen_op_buf[tcg_ctx->gen_op_buf[0].prev].next = 0;
}
static inline void gen_io_start(void)
{
TCGv_i32 tmp = tcg_const_i32(1);
- tcg_gen_st_i32(tmp, tcg_ctx.tcg_env,
+ tcg_gen_st_i32(tmp, tcg_ctx->tcg_env,
-ENV_OFFSET + offsetof(CPUState, can_do_io));
tcg_temp_free_i32(tmp);
}
@@ -70,7 +70,7 @@ static inline void gen_io_start(void)
static inline void gen_io_end(void)
{
TCGv_i32 tmp = tcg_const_i32(0);
- tcg_gen_st_i32(tmp, tcg_ctx.tcg_env,
+ tcg_gen_st_i32(tmp, tcg_ctx->tcg_env,
-ENV_OFFSET + offsetof(CPUState, can_do_io));
tcg_temp_free_i32(tmp);
}
diff --git a/tcg/tcg.h b/tcg/tcg.h
index 76324c9ad6..17fd146557 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -688,12 +688,13 @@ struct TCGContext {
target_ulong gen_insn_data[TCG_MAX_INSNS][TARGET_INSN_START_WORDS];
};
-extern TCGContext tcg_ctx;
+extern TCGContext tcg_init_ctx;
+extern TCGContext *tcg_ctx;
static inline size_t temp_idx(TCGTemp *ts)
{
- ptrdiff_t n = ts - tcg_ctx.temps;
- tcg_debug_assert(n >= 0 && n < tcg_ctx.nb_temps);
+ ptrdiff_t n = ts - tcg_ctx->temps;
+ tcg_debug_assert(n >= 0 && n < tcg_ctx->nb_temps);
return n;
}
@@ -713,7 +714,7 @@ static inline TCGTemp *arg_temp(TCGArg a)
static inline TCGTemp *tcgv_i32_temp(TCGv_i32 v)
{
uintptr_t o = (uintptr_t)v;
- TCGTemp *t = (void *)&tcg_ctx + o;
+ TCGTemp *t = (void *)tcg_ctx + o;
tcg_debug_assert(offsetof(TCGContext, temps[temp_idx(t)]) == o);
return t;
}
@@ -746,7 +747,7 @@ static inline TCGArg tcgv_ptr_arg(TCGv_ptr v)
static inline TCGv_i32 temp_tcgv_i32(TCGTemp *t)
{
(void)temp_idx(t); /* trigger embedded assert */
- return (TCGv_i32)((void *)t - (void *)&tcg_ctx);
+ return (TCGv_i32)((void *)t - (void *)tcg_ctx);
}
static inline TCGv_i64 temp_tcgv_i64(TCGTemp *t)
@@ -773,13 +774,13 @@ static inline TCGv_i32 TCGV_HIGH(TCGv_i64 t)
static inline void tcg_set_insn_param(int op_idx, int arg, TCGArg v)
{
- tcg_ctx.gen_op_buf[op_idx].args[arg] = v;
+ tcg_ctx->gen_op_buf[op_idx].args[arg] = v;
}
/* The number of opcodes emitted so far. */
static inline int tcg_op_buf_count(void)
{
- return tcg_ctx.gen_next_op_idx;
+ return tcg_ctx->gen_next_op_idx;
}
/* Test for whether to terminate the TB for using too many opcodes. */
@@ -798,7 +799,7 @@ TranslationBlock *tcg_tb_alloc(TCGContext *s);
/* Called with tb_lock held. */
static inline void *tcg_malloc(int size)
{
- TCGContext *s = &tcg_ctx;
+ TCGContext *s = tcg_ctx;
uint8_t *ptr, *ptr_end;
/* ??? This is a weak placeholder for minimum malloc alignment. */
@@ -807,7 +808,7 @@ static inline void *tcg_malloc(int size)
ptr = s->pool_cur;
ptr_end = ptr + size;
if (unlikely(ptr_end > s->pool_end)) {
- return tcg_malloc_internal(&tcg_ctx, size);
+ return tcg_malloc_internal(tcg_ctx, size);
} else {
s->pool_cur = ptr_end;
return ptr;
@@ -1147,7 +1148,7 @@ static inline unsigned get_mmuidx(TCGMemOpIdx oi)
uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr);
#else
# define tcg_qemu_tb_exec(env, tb_ptr) \
- ((uintptr_t (*)(void *, void *))tcg_ctx.code_gen_prologue)(env, tb_ptr)
+ ((uintptr_t (*)(void *, void *))tcg_ctx->code_gen_prologue)(env, tb_ptr)
#endif
void tcg_register_jit(void *buf, size_t buf_size);
diff --git a/accel/tcg/tcg-runtime.c b/accel/tcg/tcg-runtime.c
index 25f0cabfed..4172ffda82 100644
--- a/accel/tcg/tcg-runtime.c
+++ b/accel/tcg/tcg-runtime.c
@@ -153,7 +153,7 @@ void *HELPER(lookup_tb_ptr)(CPUArchState *env)
tb = tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags, curr_cflags());
if (tb == NULL) {
- return tcg_ctx.code_gen_epilogue;
+ return tcg_ctx->code_gen_epilogue;
}
qemu_log_mask_and_addr(CPU_LOG_EXEC, pc,
"Chain %p [%d: " TARGET_FMT_lx "] %s\n",
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index b238b724a8..7cd9ad5f9c 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -153,7 +153,8 @@ static int v_l2_levels;
static void *l1_map[V_L1_MAX_SIZE];
/* code generation context */
-TCGContext tcg_ctx;
+TCGContext tcg_init_ctx;
+TCGContext *tcg_ctx;
TBContext tb_ctx;
bool parallel_cpus;
@@ -209,7 +210,7 @@ static TranslationBlock *tb_find_pc(uintptr_t tc_ptr);
void cpu_gen_init(void)
{
- tcg_context_init(&tcg_ctx);
+ tcg_context_init(&tcg_init_ctx);
}
/* Encode VAL as a signed leb128 sequence at P.
@@ -267,7 +268,7 @@ static target_long decode_sleb128(uint8_t **pp)
static int encode_search(TranslationBlock *tb, uint8_t *block)
{
- uint8_t *highwater = tcg_ctx.code_gen_highwater;
+ uint8_t *highwater = tcg_ctx->code_gen_highwater;
uint8_t *p = block;
int i, j, n;
@@ -278,12 +279,12 @@ static int encode_search(TranslationBlock *tb, uint8_t *block)
if (i == 0) {
prev = (j == 0 ? tb->pc : 0);
} else {
- prev = tcg_ctx.gen_insn_data[i - 1][j];
+ prev = tcg_ctx->gen_insn_data[i - 1][j];
}
- p = encode_sleb128(p, tcg_ctx.gen_insn_data[i][j] - prev);
+ p = encode_sleb128(p, tcg_ctx->gen_insn_data[i][j] - prev);
}
- prev = (i == 0 ? 0 : tcg_ctx.gen_insn_end_off[i - 1]);
- p = encode_sleb128(p, tcg_ctx.gen_insn_end_off[i] - prev);
+ prev = (i == 0 ? 0 : tcg_ctx->gen_insn_end_off[i - 1]);
+ p = encode_sleb128(p, tcg_ctx->gen_insn_end_off[i] - prev);
/* Test for (pending) buffer overflow. The assumption is that any
one row beginning below the high water mark cannot overrun
@@ -343,8 +344,8 @@ static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
restore_state_to_opc(env, tb, data);
#ifdef CONFIG_PROFILER
- tcg_ctx.restore_time += profile_getclock() - ti;
- tcg_ctx.restore_count++;
+ tcg_ctx->restore_time += profile_getclock() - ti;
+ tcg_ctx->restore_count++;
#endif
return 0;
}
@@ -590,7 +591,7 @@ static inline void *split_cross_256mb(void *buf1, size_t size1)
buf1 = buf2;
}
- tcg_ctx.code_gen_buffer_size = size1;
+ tcg_ctx->code_gen_buffer_size = size1;
return buf1;
}
#endif
@@ -653,16 +654,16 @@ static inline void *alloc_code_gen_buffer(void)
size = full_size - qemu_real_host_page_size;
/* Honor a command-line option limiting the size of the buffer. */
- if (size > tcg_ctx.code_gen_buffer_size) {
- size = (((uintptr_t)buf + tcg_ctx.code_gen_buffer_size)
+ if (size > tcg_ctx->code_gen_buffer_size) {
+ size = (((uintptr_t)buf + tcg_ctx->code_gen_buffer_size)
& qemu_real_host_page_mask) - (uintptr_t)buf;
}
- tcg_ctx.code_gen_buffer_size = size;
+ tcg_ctx->code_gen_buffer_size = size;
#ifdef __mips__
if (cross_256mb(buf, size)) {
buf = split_cross_256mb(buf, size);
- size = tcg_ctx.code_gen_buffer_size;
+ size = tcg_ctx->code_gen_buffer_size;
}
#endif
@@ -675,7 +676,7 @@ static inline void *alloc_code_gen_buffer(void)
#elif defined(_WIN32)
static inline void *alloc_code_gen_buffer(void)
{
- size_t size = tcg_ctx.code_gen_buffer_size;
+ size_t size = tcg_ctx->code_gen_buffer_size;
void *buf1, *buf2;
/* Perform the allocation in two steps, so that the guard page
@@ -694,7 +695,7 @@ static inline void *alloc_code_gen_buffer(void)
{
int flags = MAP_PRIVATE | MAP_ANONYMOUS;
uintptr_t start = 0;
- size_t size = tcg_ctx.code_gen_buffer_size;
+ size_t size = tcg_ctx->code_gen_buffer_size;
void *buf;
/* Constrain the position of the buffer based on the host cpu.
@@ -711,7 +712,7 @@ static inline void *alloc_code_gen_buffer(void)
flags |= MAP_32BIT;
/* Cannot expect to map more than 800MB in low memory. */
if (size > 800u * 1024 * 1024) {
- tcg_ctx.code_gen_buffer_size = size = 800u * 1024 * 1024;
+ tcg_ctx->code_gen_buffer_size = size = 800u * 1024 * 1024;
}
# elif defined(__sparc__)
start = 0x40000000ul;
@@ -751,7 +752,7 @@ static inline void *alloc_code_gen_buffer(void)
default:
/* Split the original buffer. Free the smaller half. */
buf2 = split_cross_256mb(buf, size);
- size2 = tcg_ctx.code_gen_buffer_size;
+ size2 = tcg_ctx->code_gen_buffer_size;
if (buf == buf2) {
munmap(buf + size2 + qemu_real_host_page_size, size - size2);
} else {
@@ -819,9 +820,9 @@ static gint tb_tc_cmp(gconstpointer ap, gconstpointer bp)
static inline void code_gen_alloc(size_t tb_size)
{
- tcg_ctx.code_gen_buffer_size = size_code_gen_buffer(tb_size);
- tcg_ctx.code_gen_buffer = alloc_code_gen_buffer();
- if (tcg_ctx.code_gen_buffer == NULL) {
+ tcg_ctx->code_gen_buffer_size = size_code_gen_buffer(tb_size);
+ tcg_ctx->code_gen_buffer = alloc_code_gen_buffer();
+ if (tcg_ctx->code_gen_buffer == NULL) {
fprintf(stderr, "Could not allocate dynamic translator buffer\n");
exit(1);
}
@@ -849,7 +850,7 @@ void tcg_exec_init(unsigned long tb_size)
#if defined(CONFIG_SOFTMMU)
/* There's no guest base to take into account, so go ahead and
initialize the prologue now. */
- tcg_prologue_init(&tcg_ctx);
+ tcg_prologue_init(tcg_ctx);
#endif
}
@@ -865,7 +866,7 @@ static TranslationBlock *tb_alloc(target_ulong pc)
assert_tb_locked();
- tb = tcg_tb_alloc(&tcg_ctx);
+ tb = tcg_tb_alloc(tcg_ctx);
if (unlikely(tb == NULL)) {
return NULL;
}
@@ -949,11 +950,11 @@ static void do_tb_flush(CPUState *cpu, run_on_cpu_data tb_flush_count)
g_tree_foreach(tb_ctx.tb_tree, tb_host_size_iter, &host_size);
printf("qemu: flush code_size=%td nb_tbs=%zu avg_tb_size=%zu\n",
- tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer, nb_tbs,
+ tcg_ctx->code_gen_ptr - tcg_ctx->code_gen_buffer, nb_tbs,
nb_tbs > 0 ? host_size / nb_tbs : 0);
}
- if ((unsigned long)(tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer)
- > tcg_ctx.code_gen_buffer_size) {
+ if ((unsigned long)(tcg_ctx->code_gen_ptr - tcg_ctx->code_gen_buffer)
+ > tcg_ctx->code_gen_buffer_size) {
cpu_abort(cpu, "Internal error: code buffer overflow\n");
}
@@ -968,7 +969,7 @@ static void do_tb_flush(CPUState *cpu, run_on_cpu_data tb_flush_count)
qht_reset_size(&tb_ctx.htable, CODE_GEN_HTABLE_SIZE);
page_flush_tb();
- tcg_ctx.code_gen_ptr = tcg_ctx.code_gen_buffer;
+ tcg_ctx->code_gen_ptr = tcg_ctx->code_gen_buffer;
/* XXX: flush processor icache at this point if cache flush is
expensive */
atomic_mb_set(&tb_ctx.tb_flush_count, tb_ctx.tb_flush_count + 1);
@@ -1316,44 +1317,44 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
cpu_loop_exit(cpu);
}
- gen_code_buf = tcg_ctx.code_gen_ptr;
+ gen_code_buf = tcg_ctx->code_gen_ptr;
tb->tc.ptr = gen_code_buf;
tb->pc = pc;
tb->cs_base = cs_base;
tb->flags = flags;
tb->cflags = cflags;
tb->trace_vcpu_dstate = *cpu->trace_dstate;
- tcg_ctx.tb_cflags = cflags;
+ tcg_ctx->tb_cflags = cflags;
#ifdef CONFIG_PROFILER
- tcg_ctx.tb_count1++; /* includes aborted translations because of
+ tcg_ctx->tb_count1++; /* includes aborted translations because of
exceptions */
ti = profile_getclock();
#endif
- tcg_func_start(&tcg_ctx);
+ tcg_func_start(tcg_ctx);
- tcg_ctx.cpu = ENV_GET_CPU(env);
+ tcg_ctx->cpu = ENV_GET_CPU(env);
gen_intermediate_code(cpu, tb);
- tcg_ctx.cpu = NULL;
+ tcg_ctx->cpu = NULL;
trace_translate_block(tb, tb->pc, tb->tc.ptr);
/* generate machine code */
tb->jmp_reset_offset[0] = TB_JMP_RESET_OFFSET_INVALID;
tb->jmp_reset_offset[1] = TB_JMP_RESET_OFFSET_INVALID;
- tcg_ctx.tb_jmp_reset_offset = tb->jmp_reset_offset;
+ tcg_ctx->tb_jmp_reset_offset = tb->jmp_reset_offset;
if (TCG_TARGET_HAS_direct_jump) {
- tcg_ctx.tb_jmp_insn_offset = tb->jmp_target_arg;
- tcg_ctx.tb_jmp_target_addr = NULL;
+ tcg_ctx->tb_jmp_insn_offset = tb->jmp_target_arg;
+ tcg_ctx->tb_jmp_target_addr = NULL;
} else {
- tcg_ctx.tb_jmp_insn_offset = NULL;
- tcg_ctx.tb_jmp_target_addr = tb->jmp_target_arg;
+ tcg_ctx->tb_jmp_insn_offset = NULL;
+ tcg_ctx->tb_jmp_target_addr = tb->jmp_target_arg;
}
#ifdef CONFIG_PROFILER
- tcg_ctx.tb_count++;
- tcg_ctx.interm_time += profile_getclock() - ti;
+ tcg_ctx->tb_count++;
+ tcg_ctx->interm_time += profile_getclock() - ti;
ti = profile_getclock();
#endif
@@ -1362,7 +1363,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
the tcg optimization currently hidden inside tcg_gen_code. All
that should be required is to flush the TBs, allocate a new TB,
re-initialize it per above, and re-do the actual code generation. */
- gen_code_size = tcg_gen_code(&tcg_ctx, tb);
+ gen_code_size = tcg_gen_code(tcg_ctx, tb);
if (unlikely(gen_code_size < 0)) {
goto buffer_overflow;
}
@@ -1373,10 +1374,10 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
tb->tc.size = gen_code_size;
#ifdef CONFIG_PROFILER
- tcg_ctx.code_time += profile_getclock() - ti;
- tcg_ctx.code_in_len += tb->size;
- tcg_ctx.code_out_len += gen_code_size;
- tcg_ctx.search_out_len += search_size;
+ tcg_ctx->code_time += profile_getclock() - ti;
+ tcg_ctx->code_in_len += tb->size;
+ tcg_ctx->code_out_len += gen_code_size;
+ tcg_ctx->search_out_len += search_size;
#endif
#ifdef DEBUG_DISAS
@@ -1384,8 +1385,8 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
qemu_log_in_addr_range(tb->pc)) {
qemu_log_lock();
qemu_log("OUT: [size=%d]\n", gen_code_size);
- if (tcg_ctx.data_gen_ptr) {
- size_t code_size = tcg_ctx.data_gen_ptr - tb->tc.ptr;
+ if (tcg_ctx->data_gen_ptr) {
+ size_t code_size = tcg_ctx->data_gen_ptr - tb->tc.ptr;
size_t data_size = gen_code_size - code_size;
size_t i;
@@ -1394,12 +1395,12 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
for (i = 0; i < data_size; i += sizeof(tcg_target_ulong)) {
if (sizeof(tcg_target_ulong) == 8) {
qemu_log("0x%08" PRIxPTR ": .quad 0x%016" PRIx64 "\n",
- (uintptr_t)tcg_ctx.data_gen_ptr + i,
- *(uint64_t *)(tcg_ctx.data_gen_ptr + i));
+ (uintptr_t)tcg_ctx->data_gen_ptr + i,
+ *(uint64_t *)(tcg_ctx->data_gen_ptr + i));
} else {
qemu_log("0x%08" PRIxPTR ": .long 0x%08x\n",
- (uintptr_t)tcg_ctx.data_gen_ptr + i,
- *(uint32_t *)(tcg_ctx.data_gen_ptr + i));
+ (uintptr_t)tcg_ctx->data_gen_ptr + i,
+ *(uint32_t *)(tcg_ctx->data_gen_ptr + i));
}
}
} else {
@@ -1411,7 +1412,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
}
#endif
- tcg_ctx.code_gen_ptr = (void *)
+ tcg_ctx->code_gen_ptr = (void *)
ROUND_UP((uintptr_t)gen_code_buf + gen_code_size + search_size,
CODE_GEN_ALIGN);
@@ -1940,8 +1941,8 @@ void dump_exec_info(FILE *f, fprintf_function cpu_fprintf)
* For avg host size we use the precise numbers from tb_tree_stats though.
*/
cpu_fprintf(f, "gen code size %td/%zd\n",
- tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer,
- tcg_ctx.code_gen_highwater - tcg_ctx.code_gen_buffer);
+ tcg_ctx->code_gen_ptr - tcg_ctx->code_gen_buffer,
+ tcg_ctx->code_gen_highwater - tcg_ctx->code_gen_buffer);
cpu_fprintf(f, "TB count %zu\n", nb_tbs);
cpu_fprintf(f, "TB avg target size %zu max=%zu bytes\n",
nb_tbs ? tst.target_size / nb_tbs : 0,
diff --git a/bsd-user/main.c b/bsd-user/main.c
index 836daac15c..392c0ed5fb 100644
--- a/bsd-user/main.c
+++ b/bsd-user/main.c
@@ -977,7 +977,7 @@ int main(int argc, char **argv)
/* Now that we've loaded the binary, GUEST_BASE is fixed. Delay
generating the prologue until now so that the prologue can take
the real value of GUEST_BASE into account. */
- tcg_prologue_init(&tcg_ctx);
+ tcg_prologue_init(tcg_ctx);
/* build Task State */
memset(ts, 0, sizeof(TaskState));
diff --git a/linux-user/main.c b/linux-user/main.c
index 0a2a0d75b3..8814906409 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -4476,7 +4476,7 @@ int main(int argc, char **argv, char **envp)
/* Now that we've loaded the binary, GUEST_BASE is fixed. Delay
generating the prologue until now so that the prologue can take
the real value of GUEST_BASE into account. */
- tcg_prologue_init(&tcg_ctx);
+ tcg_prologue_init(tcg_ctx);
#if defined(TARGET_I386)
env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK;
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
index 53b8c036e2..f6247bf38d 100644
--- a/target/alpha/translate.c
+++ b/target/alpha/translate.c
@@ -127,7 +127,7 @@ void alpha_translate_init(void)
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
- tcg_ctx.tcg_env = cpu_env;
+ tcg_ctx->tcg_env = cpu_env;
for (i = 0; i < 31; i++) {
cpu_std_ir[i] = tcg_global_mem_new_i64(cpu_env,
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 397cc7afea..7873c03ae8 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -82,7 +82,7 @@ void arm_translate_init(void)
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
- tcg_ctx.tcg_env = cpu_env;
+ tcg_ctx->tcg_env = cpu_env;
for (i = 0; i < 16; i++) {
cpu_R[i] = tcg_global_mem_new_i32(cpu_env,
diff --git a/target/cris/translate.c b/target/cris/translate.c
index 6774acc7af..6687b838d5 100644
--- a/target/cris/translate.c
+++ b/target/cris/translate.c
@@ -3369,7 +3369,7 @@ void cris_initialize_tcg(void)
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
- tcg_ctx.tcg_env = cpu_env;
+ tcg_ctx->tcg_env = cpu_env;
cc_x = tcg_global_mem_new(cpu_env,
offsetof(CPUCRISState, cc_x), "cc_x");
cc_src = tcg_global_mem_new(cpu_env,
diff --git a/target/cris/translate_v10.c b/target/cris/translate_v10.c
index 4a0b485d8e..5d489203f4 100644
--- a/target/cris/translate_v10.c
+++ b/target/cris/translate_v10.c
@@ -1273,7 +1273,7 @@ void cris_initialize_crisv10_tcg(void)
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
- tcg_ctx.tcg_env = cpu_env;
+ tcg_ctx->tcg_env = cpu_env;
cc_x = tcg_global_mem_new(cpu_env,
offsetof(CPUCRISState, cc_x), "cc_x");
cc_src = tcg_global_mem_new(cpu_env,
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 08b2c73291..9059812d4e 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -127,7 +127,7 @@ void hppa_translate_init(void)
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
- tcg_ctx.tcg_env = cpu_env;
+ tcg_ctx->tcg_env = cpu_env;
TCGV_UNUSED(cpu_gr[0]);
for (i = 1; i < 32; i++) {
diff --git a/target/i386/translate.c b/target/i386/translate.c
index 70ba0b2d5a..649004393d 100644
--- a/target/i386/translate.c
+++ b/target/i386/translate.c
@@ -8368,7 +8368,7 @@ void tcg_x86_init(void)
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
- tcg_ctx.tcg_env = cpu_env;
+ tcg_ctx->tcg_env = cpu_env;
cpu_cc_op = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUX86State, cc_op), "cc_op");
cpu_cc_dst = tcg_global_mem_new(cpu_env, offsetof(CPUX86State, cc_dst),
diff --git a/target/lm32/translate.c b/target/lm32/translate.c
index d4a2e00165..6707967a2c 100644
--- a/target/lm32/translate.c
+++ b/target/lm32/translate.c
@@ -1209,7 +1209,7 @@ void lm32_translate_init(void)
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
- tcg_ctx.tcg_env = cpu_env;
+ tcg_ctx->tcg_env = cpu_env;
for (i = 0; i < ARRAY_SIZE(cpu_R); i++) {
cpu_R[i] = tcg_global_mem_new(cpu_env,
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index d751faed7c..f6e902f2b6 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -70,7 +70,7 @@ void m68k_tcg_init(void)
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
- tcg_ctx.tcg_env = cpu_env;
+ tcg_ctx->tcg_env = cpu_env;
#define DEFO32(name, offset) \
QREG_##name = tcg_global_mem_new_i32(cpu_env, \
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index c70a2d6644..22f8d6230b 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -1856,7 +1856,7 @@ void mb_tcg_init(void)
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
- tcg_ctx.tcg_env = cpu_env;
+ tcg_ctx->tcg_env = cpu_env;
env_debug = tcg_global_mem_new(cpu_env,
offsetof(CPUMBState, debug),
diff --git a/target/mips/translate.c b/target/mips/translate.c
index aadffbec39..7dfa94ab26 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -20455,7 +20455,7 @@ void mips_tcg_init(void)
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
- tcg_ctx.tcg_env = cpu_env;
+ tcg_ctx->tcg_env = cpu_env;
TCGV_UNUSED(cpu_gpr[0]);
for (i = 1; i < 32; i++)
diff --git a/target/moxie/translate.c b/target/moxie/translate.c
index 3f1e609028..59c70b5cef 100644
--- a/target/moxie/translate.c
+++ b/target/moxie/translate.c
@@ -102,7 +102,7 @@ void moxie_translate_init(void)
};
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
- tcg_ctx.tcg_env = cpu_env;
+ tcg_ctx->tcg_env = cpu_env;
cpu_pc = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUMoxieState, pc), "$pc");
for (i = 0; i < 16; i++)
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
index d33e365892..b91fd206fb 100644
--- a/target/nios2/translate.c
+++ b/target/nios2/translate.c
@@ -948,7 +948,7 @@ void nios2_tcg_init(void)
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
- tcg_ctx.tcg_env = cpu_env;
+ tcg_ctx->tcg_env = cpu_env;
for (i = 0; i < NUM_CORE_REGS; i++) {
cpu_R[i] = tcg_global_mem_new(cpu_env,
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index 666d050650..b031f2db97 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -81,7 +81,7 @@ void openrisc_translate_init(void)
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
- tcg_ctx.tcg_env = cpu_env;
+ tcg_ctx->tcg_env = cpu_env;
cpu_sr = tcg_global_mem_new(cpu_env,
offsetof(CPUOpenRISCState, sr), "sr");
cpu_dflag = tcg_global_mem_new_i32(cpu_env,
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index ac5b8ea9a5..0ad84a75e4 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -86,7 +86,7 @@ void ppc_translate_init(void)
size_t cpu_reg_names_size;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
- tcg_ctx.tcg_env = cpu_env;
+ tcg_ctx->tcg_env = cpu_env;
p = cpu_reg_names;
cpu_reg_names_size = sizeof(cpu_reg_names);
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index 241b708502..2bf6f48089 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -113,7 +113,7 @@ void s390x_translate_init(void)
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
- tcg_ctx.tcg_env = cpu_env;
+ tcg_ctx->tcg_env = cpu_env;
psw_addr = tcg_global_mem_new_i64(cpu_env,
offsetof(CPUS390XState, psw.addr),
"psw_addr");
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index f918bae978..c13be851ba 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -100,7 +100,7 @@ void sh4_translate_init(void)
};
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
- tcg_ctx.tcg_env = cpu_env;
+ tcg_ctx->tcg_env = cpu_env;
for (i = 0; i < 24; i++) {
cpu_gregs[i] = tcg_global_mem_new_i32(cpu_env,
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 9dc41869a4..afef77976b 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -5912,7 +5912,7 @@ void sparc_tcg_init(void)
unsigned int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
- tcg_ctx.tcg_env = cpu_env;
+ tcg_ctx->tcg_env = cpu_env;
cpu_regwptr = tcg_global_mem_new_ptr(cpu_env,
offsetof(CPUSPARCState, regwptr),
diff --git a/target/tilegx/translate.c b/target/tilegx/translate.c
index 5cd84f6b25..a744c38bb7 100644
--- a/target/tilegx/translate.c
+++ b/target/tilegx/translate.c
@@ -2446,7 +2446,7 @@ void tilegx_tcg_init(void)
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
- tcg_ctx.tcg_env = cpu_env;
+ tcg_ctx->tcg_env = cpu_env;
cpu_pc = tcg_global_mem_new_i64(cpu_env, offsetof(CPUTLGState, pc), "pc");
for (i = 0; i < TILEGX_R_COUNT; i++) {
cpu_regs[i] = tcg_global_mem_new_i64(cpu_env,
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 042c0e69bc..590cbbee8b 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -8882,7 +8882,7 @@ void tricore_tcg_init(void)
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
- tcg_ctx.tcg_env = cpu_env;
+ tcg_ctx->tcg_env = cpu_env;
/* reg init */
for (i = 0 ; i < 16 ; i++) {
cpu_gpr_a[i] = tcg_global_mem_new(cpu_env,
diff --git a/target/unicore32/translate.c b/target/unicore32/translate.c
index d717de0335..070653e2d1 100644
--- a/target/unicore32/translate.c
+++ b/target/unicore32/translate.c
@@ -75,7 +75,7 @@ void uc32_translate_init(void)
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
- tcg_ctx.tcg_env = cpu_env;
+ tcg_ctx->tcg_env = cpu_env;
for (i = 0; i < 32; i++) {
cpu_R[i] = tcg_global_mem_new_i32(cpu_env,
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index f62319eddd..ab96b77d88 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -222,7 +222,7 @@ void xtensa_translate_init(void)
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
- tcg_ctx.tcg_env = cpu_env;
+ tcg_ctx->tcg_env = cpu_env;
cpu_pc = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUXtensaState, pc), "pc");
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index 8c7668de60..ba603281d3 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -48,7 +48,7 @@ extern TCGv_i32 TCGV_HIGH_link_error(TCGv_i64);
static inline TCGOp *tcg_emit_op(TCGOpcode opc)
{
- TCGContext *ctx = &tcg_ctx;
+ TCGContext *ctx = tcg_ctx;
int oi = ctx->gen_next_op_idx;
int ni = oi + 1;
int pi = oi - 1;
@@ -121,7 +121,7 @@ void tcg_gen_op6(TCGOpcode opc, TCGArg a1, TCGArg a2, TCGArg a3,
void tcg_gen_mb(TCGBar mb_type)
{
- if (tcg_ctx.tb_cflags & CF_PARALLEL) {
+ if (tcg_ctx->tb_cflags & CF_PARALLEL) {
tcg_gen_op1(INDEX_op_mb, mb_type);
}
}
@@ -2552,8 +2552,8 @@ void tcg_gen_goto_tb(unsigned idx)
tcg_debug_assert(idx <= 1);
#ifdef CONFIG_DEBUG_TCG
/* Verify that we havn't seen this numbered exit before. */
- tcg_debug_assert((tcg_ctx.goto_tb_issue_mask & (1 << idx)) == 0);
- tcg_ctx.goto_tb_issue_mask |= 1 << idx;
+ tcg_debug_assert((tcg_ctx->goto_tb_issue_mask & (1 << idx)) == 0);
+ tcg_ctx->goto_tb_issue_mask |= 1 << idx;
#endif
tcg_gen_op1i(INDEX_op_goto_tb, idx);
}
@@ -2562,7 +2562,7 @@ void tcg_gen_lookup_and_goto_ptr(void)
{
if (TCG_TARGET_HAS_goto_ptr && !qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)) {
TCGv_ptr ptr = tcg_temp_new_ptr();
- gen_helper_lookup_tb_ptr(ptr, tcg_ctx.tcg_env);
+ gen_helper_lookup_tb_ptr(ptr, tcg_ctx->tcg_env);
tcg_gen_op1i(INDEX_op_goto_ptr, tcgv_ptr_arg(ptr));
tcg_temp_free_ptr(ptr);
} else {
@@ -2648,7 +2648,7 @@ void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop)
{
tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD);
memop = tcg_canonicalize_memop(memop, 0, 0);
- trace_guest_mem_before_tcg(tcg_ctx.cpu, tcg_ctx.tcg_env,
+ trace_guest_mem_before_tcg(tcg_ctx->cpu, tcg_ctx->tcg_env,
addr, trace_mem_get_info(memop, 0));
gen_ldst_i32(INDEX_op_qemu_ld_i32, val, addr, memop, idx);
}
@@ -2657,7 +2657,7 @@ void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop)
{
tcg_gen_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST);
memop = tcg_canonicalize_memop(memop, 0, 1);
- trace_guest_mem_before_tcg(tcg_ctx.cpu, tcg_ctx.tcg_env,
+ trace_guest_mem_before_tcg(tcg_ctx->cpu, tcg_ctx->tcg_env,
addr, trace_mem_get_info(memop, 1));
gen_ldst_i32(INDEX_op_qemu_st_i32, val, addr, memop, idx);
}
@@ -2676,7 +2676,7 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop)
}
memop = tcg_canonicalize_memop(memop, 1, 0);
- trace_guest_mem_before_tcg(tcg_ctx.cpu, tcg_ctx.tcg_env,
+ trace_guest_mem_before_tcg(tcg_ctx->cpu, tcg_ctx->tcg_env,
addr, trace_mem_get_info(memop, 0));
gen_ldst_i64(INDEX_op_qemu_ld_i64, val, addr, memop, idx);
}
@@ -2690,7 +2690,7 @@ void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop)
}
memop = tcg_canonicalize_memop(memop, 1, 1);
- trace_guest_mem_before_tcg(tcg_ctx.cpu, tcg_ctx.tcg_env,
+ trace_guest_mem_before_tcg(tcg_ctx->cpu, tcg_ctx->tcg_env,
addr, trace_mem_get_info(memop, 1));
gen_ldst_i64(INDEX_op_qemu_st_i64, val, addr, memop, idx);
}
@@ -2780,7 +2780,7 @@ void tcg_gen_atomic_cmpxchg_i32(TCGv_i32 retv, TCGv addr, TCGv_i32 cmpv,
{
memop = tcg_canonicalize_memop(memop, 0, 0);
- if (!(tcg_ctx.tb_cflags & CF_PARALLEL)) {
+ if (!(tcg_ctx->tb_cflags & CF_PARALLEL)) {
TCGv_i32 t1 = tcg_temp_new_i32();
TCGv_i32 t2 = tcg_temp_new_i32();
@@ -2806,11 +2806,11 @@ void tcg_gen_atomic_cmpxchg_i32(TCGv_i32 retv, TCGv addr, TCGv_i32 cmpv,
#ifdef CONFIG_SOFTMMU
{
TCGv_i32 oi = tcg_const_i32(make_memop_idx(memop & ~MO_SIGN, idx));
- gen(retv, tcg_ctx.tcg_env, addr, cmpv, newv, oi);
+ gen(retv, tcg_ctx->tcg_env, addr, cmpv, newv, oi);
tcg_temp_free_i32(oi);
}
#else
- gen(retv, tcg_ctx.tcg_env, addr, cmpv, newv);
+ gen(retv, tcg_ctx->tcg_env, addr, cmpv, newv);
#endif
if (memop & MO_SIGN) {
@@ -2824,7 +2824,7 @@ void tcg_gen_atomic_cmpxchg_i64(TCGv_i64 retv, TCGv addr, TCGv_i64 cmpv,
{
memop = tcg_canonicalize_memop(memop, 1, 0);
- if (!(tcg_ctx.tb_cflags & CF_PARALLEL)) {
+ if (!(tcg_ctx->tb_cflags & CF_PARALLEL)) {
TCGv_i64 t1 = tcg_temp_new_i64();
TCGv_i64 t2 = tcg_temp_new_i64();
@@ -2851,14 +2851,14 @@ void tcg_gen_atomic_cmpxchg_i64(TCGv_i64 retv, TCGv addr, TCGv_i64 cmpv,
#ifdef CONFIG_SOFTMMU
{
TCGv_i32 oi = tcg_const_i32(make_memop_idx(memop, idx));
- gen(retv, tcg_ctx.tcg_env, addr, cmpv, newv, oi);
+ gen(retv, tcg_ctx->tcg_env, addr, cmpv, newv, oi);
tcg_temp_free_i32(oi);
}
#else
- gen(retv, tcg_ctx.tcg_env, addr, cmpv, newv);
+ gen(retv, tcg_ctx->tcg_env, addr, cmpv, newv);
#endif
#else
- gen_helper_exit_atomic(tcg_ctx.tcg_env);
+ gen_helper_exit_atomic(tcg_ctx->tcg_env);
/* Produce a result, so that we have a well-formed opcode stream
with respect to uses of the result in the (dead) code following. */
tcg_gen_movi_i64(retv, 0);
@@ -2914,11 +2914,11 @@ static void do_atomic_op_i32(TCGv_i32 ret, TCGv addr, TCGv_i32 val,
#ifdef CONFIG_SOFTMMU
{
TCGv_i32 oi = tcg_const_i32(make_memop_idx(memop & ~MO_SIGN, idx));
- gen(ret, tcg_ctx.tcg_env, addr, val, oi);
+ gen(ret, tcg_ctx->tcg_env, addr, val, oi);
tcg_temp_free_i32(oi);
}
#else
- gen(ret, tcg_ctx.tcg_env, addr, val);
+ gen(ret, tcg_ctx->tcg_env, addr, val);
#endif
if (memop & MO_SIGN) {
@@ -2959,14 +2959,14 @@ static void do_atomic_op_i64(TCGv_i64 ret, TCGv addr, TCGv_i64 val,
#ifdef CONFIG_SOFTMMU
{
TCGv_i32 oi = tcg_const_i32(make_memop_idx(memop & ~MO_SIGN, idx));
- gen(ret, tcg_ctx.tcg_env, addr, val, oi);
+ gen(ret, tcg_ctx->tcg_env, addr, val, oi);
tcg_temp_free_i32(oi);
}
#else
- gen(ret, tcg_ctx.tcg_env, addr, val);
+ gen(ret, tcg_ctx->tcg_env, addr, val);
#endif
#else
- gen_helper_exit_atomic(tcg_ctx.tcg_env);
+ gen_helper_exit_atomic(tcg_ctx->tcg_env);
/* Produce a result, so that we have a well-formed opcode stream
with respect to uses of the result in the (dead) code following. */
tcg_gen_movi_i64(ret, 0);
@@ -3001,7 +3001,7 @@ static void * const table_##NAME[16] = { \
void tcg_gen_atomic_##NAME##_i32 \
(TCGv_i32 ret, TCGv addr, TCGv_i32 val, TCGArg idx, TCGMemOp memop) \
{ \
- if (tcg_ctx.tb_cflags & CF_PARALLEL) { \
+ if (tcg_ctx->tb_cflags & CF_PARALLEL) { \
do_atomic_op_i32(ret, addr, val, idx, memop, table_##NAME); \
} else { \
do_nonatomic_op_i32(ret, addr, val, idx, memop, NEW, \
@@ -3011,7 +3011,7 @@ void tcg_gen_atomic_##NAME##_i32 \
void tcg_gen_atomic_##NAME##_i64 \
(TCGv_i64 ret, TCGv addr, TCGv_i64 val, TCGArg idx, TCGMemOp memop) \
{ \
- if (tcg_ctx.tb_cflags & CF_PARALLEL) { \
+ if (tcg_ctx->tb_cflags & CF_PARALLEL) { \
do_atomic_op_i64(ret, addr, val, idx, memop, table_##NAME); \
} else { \
do_nonatomic_op_i64(ret, addr, val, idx, memop, NEW, \
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 3a73912827..62f418ac8a 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -243,7 +243,7 @@ static void tcg_out_label(TCGContext *s, TCGLabel *l, tcg_insn_unit *ptr)
TCGLabel *gen_new_label(void)
{
- TCGContext *s = &tcg_ctx;
+ TCGContext *s = tcg_ctx;
TCGLabel *l = tcg_malloc(sizeof(TCGLabel));
*l = (TCGLabel){
@@ -382,6 +382,8 @@ void tcg_context_init(TCGContext *s)
for (; i < ARRAY_SIZE(tcg_target_reg_alloc_order); ++i) {
indirect_reg_alloc_order[i] = tcg_target_reg_alloc_order[i];
}
+
+ tcg_ctx = s;
}
/*
@@ -522,7 +524,7 @@ void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size)
TCGv_i32 tcg_global_reg_new_i32(TCGReg reg, const char *name)
{
- TCGContext *s = &tcg_ctx;
+ TCGContext *s = tcg_ctx;
TCGTemp *t;
if (tcg_regset_test_reg(s->reserved_regs, reg)) {
@@ -534,7 +536,7 @@ TCGv_i32 tcg_global_reg_new_i32(TCGReg reg, const char *name)
TCGv_i64 tcg_global_reg_new_i64(TCGReg reg, const char *name)
{
- TCGContext *s = &tcg_ctx;
+ TCGContext *s = tcg_ctx;
TCGTemp *t;
if (tcg_regset_test_reg(s->reserved_regs, reg)) {
@@ -547,7 +549,7 @@ TCGv_i64 tcg_global_reg_new_i64(TCGReg reg, const char *name)
TCGTemp *tcg_global_mem_new_internal(TCGType type, TCGv_ptr base,
intptr_t offset, const char *name)
{
- TCGContext *s = &tcg_ctx;
+ TCGContext *s = tcg_ctx;
TCGTemp *base_ts = tcgv_ptr_temp(base);
TCGTemp *ts = tcg_global_alloc(s);
int indirect_reg = 0, bigendian = 0;
@@ -602,7 +604,7 @@ TCGTemp *tcg_global_mem_new_internal(TCGType type, TCGv_ptr base,
static TCGTemp *tcg_temp_new_internal(TCGType type, int temp_local)
{
- TCGContext *s = &tcg_ctx;
+ TCGContext *s = tcg_ctx;
TCGTemp *ts;
int idx, k;
@@ -659,7 +661,7 @@ TCGv_i64 tcg_temp_new_internal_i64(int temp_local)
static void tcg_temp_free_internal(TCGTemp *ts)
{
- TCGContext *s = &tcg_ctx;
+ TCGContext *s = tcg_ctx;
int k, idx;
#if defined(CONFIG_DEBUG_TCG)
@@ -723,13 +725,13 @@ TCGv_i64 tcg_const_local_i64(int64_t val)
#if defined(CONFIG_DEBUG_TCG)
void tcg_clear_temp_count(void)
{
- TCGContext *s = &tcg_ctx;
+ TCGContext *s = tcg_ctx;
s->temps_in_use = 0;
}
int tcg_check_temp_count(void)
{
- TCGContext *s = &tcg_ctx;
+ TCGContext *s = tcg_ctx;
if (s->temps_in_use) {
/* Clear the count so that we don't give another
* warning immediately next time around.
@@ -969,7 +971,7 @@ bool tcg_op_supported(TCGOpcode op)
and endian swap in tcg_reg_alloc_call(). */
void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args)
{
- TCGContext *s = &tcg_ctx;
+ TCGContext *s = tcg_ctx;
int i, real_args, nb_rets, pi;
unsigned sizemask, flags;
TCGHelperInfo *info;
@@ -2908,7 +2910,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb)
#ifdef CONFIG_PROFILER
void tcg_dump_info(FILE *f, fprintf_function cpu_fprintf)
{
- TCGContext *s = &tcg_ctx;
+ TCGContext *s = tcg_ctx;
int64_t tb_count = s->tb_count;
int64_t tb_div_count = tb_count ? tb_count : 1;
int64_t tot = s->interm_time + s->code_time;
--
2.13.6
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [Qemu-devel] [PULL 42/51] gen-icount: fold exitreq_label into TCGContext
2017-10-25 9:34 [Qemu-devel] [PULL 00/51] tcg queued patches Richard Henderson
` (40 preceding siblings ...)
2017-10-25 9:35 ` [Qemu-devel] [PULL 41/51] tcg: define tcg_init_ctx and make tcg_ctx a pointer Richard Henderson
@ 2017-10-25 9:35 ` Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 43/51] tcg: introduce **tcg_ctxs to keep track of all TCGContext's Richard Henderson
` (11 subsequent siblings)
53 siblings, 0 replies; 59+ messages in thread
From: Richard Henderson @ 2017-10-25 9:35 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Emilio G. Cota
From: "Emilio G. Cota" <cota@braap.org>
Groundwork for supporting multiple TCG contexts.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/gen-icount.h | 7 +++----
tcg/tcg.h | 2 ++
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/include/exec/gen-icount.h b/include/exec/gen-icount.h
index c58b0b2585..fe80176462 100644
--- a/include/exec/gen-icount.h
+++ b/include/exec/gen-icount.h
@@ -6,13 +6,12 @@
/* Helpers for instruction counting code generation. */
static int icount_start_insn_idx;
-static TCGLabel *exitreq_label;
static inline void gen_tb_start(TranslationBlock *tb)
{
TCGv_i32 count, imm;
- exitreq_label = gen_new_label();
+ tcg_ctx->exitreq_label = gen_new_label();
if (tb_cflags(tb) & CF_USE_ICOUNT) {
count = tcg_temp_local_new_i32();
} else {
@@ -34,7 +33,7 @@ static inline void gen_tb_start(TranslationBlock *tb)
tcg_temp_free_i32(imm);
}
- tcg_gen_brcondi_i32(TCG_COND_LT, count, 0, exitreq_label);
+ tcg_gen_brcondi_i32(TCG_COND_LT, count, 0, tcg_ctx->exitreq_label);
if (tb_cflags(tb) & CF_USE_ICOUNT) {
tcg_gen_st16_i32(count, tcg_ctx->tcg_env,
@@ -52,7 +51,7 @@ static inline void gen_tb_end(TranslationBlock *tb, int num_insns)
tcg_set_insn_param(icount_start_insn_idx, 1, num_insns);
}
- gen_set_label(exitreq_label);
+ gen_set_label(tcg_ctx->exitreq_label);
tcg_gen_exit_tb((uintptr_t)tb + TB_EXIT_REQUESTED);
/* Terminate the linked list. */
diff --git a/tcg/tcg.h b/tcg/tcg.h
index 17fd146557..cca85b4d85 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -675,6 +675,8 @@ struct TCGContext {
struct TCGLabelPoolData *pool_labels;
#endif
+ TCGLabel *exitreq_label;
+
TCGTempSet free_temps[TCG_TYPE_COUNT * 2];
TCGTemp temps[TCG_MAX_TEMPS]; /* globals first, temps after */
--
2.13.6
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [Qemu-devel] [PULL 43/51] tcg: introduce **tcg_ctxs to keep track of all TCGContext's
2017-10-25 9:34 [Qemu-devel] [PULL 00/51] tcg queued patches Richard Henderson
` (41 preceding siblings ...)
2017-10-25 9:35 ` [Qemu-devel] [PULL 42/51] gen-icount: fold exitreq_label into TCGContext Richard Henderson
@ 2017-10-25 9:35 ` Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 44/51] tcg: distribute profiling counters across TCGContext's Richard Henderson
` (10 subsequent siblings)
53 siblings, 0 replies; 59+ messages in thread
From: Richard Henderson @ 2017-10-25 9:35 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Emilio G. Cota
From: "Emilio G. Cota" <cota@braap.org>
Groundwork for supporting multiple TCG contexts.
Note that having n_tcg_ctxs is unnecessary. However, it is
convenient to have it, since it will simplify iterating over the
array: we'll have just a for loop instead of having to iterate
over a NULL-terminated array (which would require n+1 elems)
or having to check with ifdef's for usermode/softmmu.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tcg.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 62f418ac8a..24ef6df6b5 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -118,6 +118,9 @@ static bool tcg_out_ldst_finalize(TCGContext *s);
#define TCG_HIGHWATER 1024
+static TCGContext **tcg_ctxs;
+static unsigned int n_tcg_ctxs;
+
static TCGRegSet tcg_target_available_regs[2];
static TCGRegSet tcg_target_call_clobber_regs;
@@ -384,6 +387,8 @@ void tcg_context_init(TCGContext *s)
}
tcg_ctx = s;
+ tcg_ctxs = &tcg_ctx;
+ n_tcg_ctxs = 1;
}
/*
--
2.13.6
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [Qemu-devel] [PULL 44/51] tcg: distribute profiling counters across TCGContext's
2017-10-25 9:34 [Qemu-devel] [PULL 00/51] tcg queued patches Richard Henderson
` (42 preceding siblings ...)
2017-10-25 9:35 ` [Qemu-devel] [PULL 43/51] tcg: introduce **tcg_ctxs to keep track of all TCGContext's Richard Henderson
@ 2017-10-25 9:35 ` Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 45/51] tcg: allocate optimizer temps with tcg_malloc Richard Henderson
` (9 subsequent siblings)
53 siblings, 0 replies; 59+ messages in thread
From: Richard Henderson @ 2017-10-25 9:35 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Emilio G. Cota
From: "Emilio G. Cota" <cota@braap.org>
This is groundwork for supporting multiple TCG contexts.
To avoid scalability issues when profiling info is enabled, this patch
makes the profiling info counters distributed via the following changes:
1) Consolidate profile info into its own struct, TCGProfile, which
TCGContext also includes. Note that tcg_table_op_count is brought
into TCGProfile after dropping the tcg_ prefix.
2) Iterate over the TCG contexts in the system to obtain the total counts.
This change also requires updating the accessors to TCGProfile fields to
use atomic_read/set whenever there may be conflicting accesses (as defined
in C11) to them.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tcg.h | 38 +++++++++-------
accel/tcg/translate-all.c | 23 +++++-----
tcg/tcg.c | 110 ++++++++++++++++++++++++++++++++++++++--------
3 files changed, 126 insertions(+), 45 deletions(-)
diff --git a/tcg/tcg.h b/tcg/tcg.h
index cca85b4d85..4b9958a179 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -599,6 +599,26 @@ QEMU_BUILD_BUG_ON(sizeof(TCGOp) != 8 + sizeof(TCGArg) * MAX_OPC_PARAM);
QEMU_BUILD_BUG_ON(NB_OPS > (1 << 8));
QEMU_BUILD_BUG_ON(OPC_BUF_SIZE > (1 << 16));
+typedef struct TCGProfile {
+ int64_t tb_count1;
+ int64_t tb_count;
+ int64_t op_count; /* total insn count */
+ int op_count_max; /* max insn per TB */
+ int64_t temp_count;
+ int temp_count_max;
+ int64_t del_op_count;
+ int64_t code_in_len;
+ int64_t code_out_len;
+ int64_t search_out_len;
+ int64_t interm_time;
+ int64_t code_time;
+ int64_t la_time;
+ int64_t opt_time;
+ int64_t restore_count;
+ int64_t restore_time;
+ int64_t table_op_count[NB_OPS];
+} TCGProfile;
+
struct TCGContext {
uint8_t *pool_cur, *pool_end;
TCGPool *pool_first, *pool_current, *pool_first_large;
@@ -623,23 +643,7 @@ struct TCGContext {
tcg_insn_unit *code_ptr;
#ifdef CONFIG_PROFILER
- /* profiling info */
- int64_t tb_count1;
- int64_t tb_count;
- int64_t op_count; /* total insn count */
- int op_count_max; /* max insn per TB */
- int64_t temp_count;
- int temp_count_max;
- int64_t del_op_count;
- int64_t code_in_len;
- int64_t code_out_len;
- int64_t search_out_len;
- int64_t interm_time;
- int64_t code_time;
- int64_t la_time;
- int64_t opt_time;
- int64_t restore_count;
- int64_t restore_time;
+ TCGProfile prof;
#endif
#ifdef CONFIG_DEBUG_TCG
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index 7cd9ad5f9c..78c150af3e 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -310,6 +310,7 @@ static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
uint8_t *p = tb->tc.ptr + tb->tc.size;
int i, j, num_insns = tb->icount;
#ifdef CONFIG_PROFILER
+ TCGProfile *prof = &tcg_ctx->prof;
int64_t ti = profile_getclock();
#endif
@@ -344,8 +345,9 @@ static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
restore_state_to_opc(env, tb, data);
#ifdef CONFIG_PROFILER
- tcg_ctx->restore_time += profile_getclock() - ti;
- tcg_ctx->restore_count++;
+ atomic_set(&prof->restore_time,
+ prof->restore_time + profile_getclock() - ti);
+ atomic_set(&prof->restore_count, prof->restore_count + 1);
#endif
return 0;
}
@@ -1300,6 +1302,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
tcg_insn_unit *gen_code_buf;
int gen_code_size, search_size;
#ifdef CONFIG_PROFILER
+ TCGProfile *prof = &tcg_ctx->prof;
int64_t ti;
#endif
assert_memory_lock();
@@ -1327,8 +1330,8 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
tcg_ctx->tb_cflags = cflags;
#ifdef CONFIG_PROFILER
- tcg_ctx->tb_count1++; /* includes aborted translations because of
- exceptions */
+ /* includes aborted translations because of exceptions */
+ atomic_set(&prof->tb_count1, prof->tb_count1 + 1);
ti = profile_getclock();
#endif
@@ -1353,8 +1356,8 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
}
#ifdef CONFIG_PROFILER
- tcg_ctx->tb_count++;
- tcg_ctx->interm_time += profile_getclock() - ti;
+ atomic_set(&prof->tb_count, prof->tb_count + 1);
+ atomic_set(&prof->interm_time, prof->interm_time + profile_getclock() - ti);
ti = profile_getclock();
#endif
@@ -1374,10 +1377,10 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
tb->tc.size = gen_code_size;
#ifdef CONFIG_PROFILER
- tcg_ctx->code_time += profile_getclock() - ti;
- tcg_ctx->code_in_len += tb->size;
- tcg_ctx->code_out_len += gen_code_size;
- tcg_ctx->search_out_len += search_size;
+ atomic_set(&prof->code_time, prof->code_time + profile_getclock() - ti);
+ atomic_set(&prof->code_in_len, prof->code_in_len + tb->size);
+ atomic_set(&prof->code_out_len, prof->code_out_len + gen_code_size);
+ atomic_set(&prof->search_out_len, prof->search_out_len + search_size);
#endif
#ifdef DEBUG_DISAS
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 24ef6df6b5..f1bbfe37ff 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1547,7 +1547,7 @@ void tcg_op_remove(TCGContext *s, TCGOp *op)
memset(op, 0, sizeof(*op));
#ifdef CONFIG_PROFILER
- s->del_op_count++;
+ atomic_set(&s->prof.del_op_count, s->prof.del_op_count + 1);
#endif
}
@@ -2715,15 +2715,79 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op)
#ifdef CONFIG_PROFILER
-static int64_t tcg_table_op_count[NB_OPS];
+/* avoid copy/paste errors */
+#define PROF_ADD(to, from, field) \
+ do { \
+ (to)->field += atomic_read(&((from)->field)); \
+ } while (0)
+
+#define PROF_MAX(to, from, field) \
+ do { \
+ typeof((from)->field) val__ = atomic_read(&((from)->field)); \
+ if (val__ > (to)->field) { \
+ (to)->field = val__; \
+ } \
+ } while (0)
+
+/* Pass in a zero'ed @prof */
+static inline
+void tcg_profile_snapshot(TCGProfile *prof, bool counters, bool table)
+{
+ unsigned int i;
+
+ for (i = 0; i < n_tcg_ctxs; i++) {
+ const TCGProfile *orig = &tcg_ctxs[i]->prof;
+
+ if (counters) {
+ PROF_ADD(prof, orig, tb_count1);
+ PROF_ADD(prof, orig, tb_count);
+ PROF_ADD(prof, orig, op_count);
+ PROF_MAX(prof, orig, op_count_max);
+ PROF_ADD(prof, orig, temp_count);
+ PROF_MAX(prof, orig, temp_count_max);
+ PROF_ADD(prof, orig, del_op_count);
+ PROF_ADD(prof, orig, code_in_len);
+ PROF_ADD(prof, orig, code_out_len);
+ PROF_ADD(prof, orig, search_out_len);
+ PROF_ADD(prof, orig, interm_time);
+ PROF_ADD(prof, orig, code_time);
+ PROF_ADD(prof, orig, la_time);
+ PROF_ADD(prof, orig, opt_time);
+ PROF_ADD(prof, orig, restore_count);
+ PROF_ADD(prof, orig, restore_time);
+ }
+ if (table) {
+ int i;
+
+ for (i = 0; i < NB_OPS; i++) {
+ PROF_ADD(prof, orig, table_op_count[i]);
+ }
+ }
+ }
+}
+
+#undef PROF_ADD
+#undef PROF_MAX
+
+static void tcg_profile_snapshot_counters(TCGProfile *prof)
+{
+ tcg_profile_snapshot(prof, true, false);
+}
+
+static void tcg_profile_snapshot_table(TCGProfile *prof)
+{
+ tcg_profile_snapshot(prof, false, true);
+}
void tcg_dump_op_count(FILE *f, fprintf_function cpu_fprintf)
{
+ TCGProfile prof = {};
int i;
+ tcg_profile_snapshot_table(&prof);
for (i = 0; i < NB_OPS; i++) {
cpu_fprintf(f, "%s %" PRId64 "\n", tcg_op_defs[i].name,
- tcg_table_op_count[i]);
+ prof.table_op_count[i]);
}
}
#else
@@ -2736,6 +2800,9 @@ void tcg_dump_op_count(FILE *f, fprintf_function cpu_fprintf)
int tcg_gen_code(TCGContext *s, TranslationBlock *tb)
{
+#ifdef CONFIG_PROFILER
+ TCGProfile *prof = &s->prof;
+#endif
int i, oi, oi_next, num_insns;
#ifdef CONFIG_PROFILER
@@ -2743,15 +2810,15 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb)
int n;
n = s->gen_op_buf[0].prev + 1;
- s->op_count += n;
- if (n > s->op_count_max) {
- s->op_count_max = n;
+ atomic_set(&prof->op_count, prof->op_count + n);
+ if (n > prof->op_count_max) {
+ atomic_set(&prof->op_count_max, n);
}
n = s->nb_temps;
- s->temp_count += n;
- if (n > s->temp_count_max) {
- s->temp_count_max = n;
+ atomic_set(&prof->temp_count, prof->temp_count + n);
+ if (n > prof->temp_count_max) {
+ atomic_set(&prof->temp_count_max, n);
}
}
#endif
@@ -2768,7 +2835,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb)
#endif
#ifdef CONFIG_PROFILER
- s->opt_time -= profile_getclock();
+ atomic_set(&prof->opt_time, prof->opt_time - profile_getclock());
#endif
#ifdef USE_TCG_OPTIMIZATIONS
@@ -2776,8 +2843,8 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb)
#endif
#ifdef CONFIG_PROFILER
- s->opt_time += profile_getclock();
- s->la_time -= profile_getclock();
+ atomic_set(&prof->opt_time, prof->opt_time + profile_getclock());
+ atomic_set(&prof->la_time, prof->la_time - profile_getclock());
#endif
liveness_pass_1(s);
@@ -2801,7 +2868,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb)
}
#ifdef CONFIG_PROFILER
- s->la_time += profile_getclock();
+ atomic_set(&prof->la_time, prof->la_time + profile_getclock());
#endif
#ifdef DEBUG_DISAS
@@ -2834,7 +2901,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb)
oi_next = op->next;
#ifdef CONFIG_PROFILER
- tcg_table_op_count[opc]++;
+ atomic_set(&prof->table_op_count[opc], prof->table_op_count[opc] + 1);
#endif
switch (opc) {
@@ -2915,10 +2982,17 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb)
#ifdef CONFIG_PROFILER
void tcg_dump_info(FILE *f, fprintf_function cpu_fprintf)
{
- TCGContext *s = tcg_ctx;
- int64_t tb_count = s->tb_count;
- int64_t tb_div_count = tb_count ? tb_count : 1;
- int64_t tot = s->interm_time + s->code_time;
+ TCGProfile prof = {};
+ const TCGProfile *s;
+ int64_t tb_count;
+ int64_t tb_div_count;
+ int64_t tot;
+
+ tcg_profile_snapshot_counters(&prof);
+ s = &prof;
+ tb_count = s->tb_count;
+ tb_div_count = tb_count ? tb_count : 1;
+ tot = s->interm_time + s->code_time;
cpu_fprintf(f, "JIT cycles %" PRId64 " (%0.3f s at 2.4 GHz)\n",
tot, tot / 2.4e9);
--
2.13.6
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [Qemu-devel] [PULL 45/51] tcg: allocate optimizer temps with tcg_malloc
2017-10-25 9:34 [Qemu-devel] [PULL 00/51] tcg queued patches Richard Henderson
` (43 preceding siblings ...)
2017-10-25 9:35 ` [Qemu-devel] [PULL 44/51] tcg: distribute profiling counters across TCGContext's Richard Henderson
@ 2017-10-25 9:35 ` Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 46/51] osdep: introduce qemu_mprotect_rwx/none Richard Henderson
` (8 subsequent siblings)
53 siblings, 0 replies; 59+ messages in thread
From: Richard Henderson @ 2017-10-25 9:35 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Emilio G. Cota
From: "Emilio G. Cota" <cota@braap.org>
Groundwork for supporting multiple TCG contexts.
While at it, also allocate temps_used directly as a bitmap of the
required size, instead of using a bitmap of TCG_MAX_TEMPS via
TCGTempSet.
Performance-wise we lose about 1.12% in a translation-heavy workload
such as booting+shutting down debian-arm:
Performance counter stats for 'taskset -c 0 arm-softmmu/qemu-system-arm \
-machine type=virt -nographic -smp 1 -m 4096 \
-netdev user,id=unet,hostfwd=tcp::2222-:22 \
-device virtio-net-device,netdev=unet \
-drive file=die-on-boot.qcow2,id=myblock,index=0,if=none \
-device virtio-blk-device,drive=myblock \
-kernel kernel.img -append console=ttyAMA0 root=/dev/vda1 \
-name arm,debug-threads=on -smp 1' (10 runs):
exec time (s) Relative slowdown wrt original (%)
---------------------------------------------------------------
original 20.213321616 0.
tcg_malloc 20.441130078 1.1270214
TCGContext 20.477846517 1.3086662
g_malloc 20.780527895 2.8061013
The other two alternatives shown in the table are:
- TCGContext: embed temps[TCG_MAX_TEMPS] and TCGTempSet used_temps
in TCGContext. This is simple enough but it isn't faster than using
tcg_malloc; moreover, it wastes memory.
- g_malloc: allocate/deallocate both temps and used_temps every time
tcg_optimize is executed.
Suggested-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/optimize.c | 42 +++++++++++++++++++-----------------------
1 file changed, 19 insertions(+), 23 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 66daced167..438321c6cc 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -40,9 +40,6 @@ struct tcg_temp_info {
tcg_target_ulong mask;
};
-static struct tcg_temp_info temps[TCG_MAX_TEMPS];
-static TCGTempSet temps_used;
-
static inline struct tcg_temp_info *ts_info(TCGTemp *ts)
{
return ts->state_ptr;
@@ -88,31 +85,27 @@ static void reset_temp(TCGArg arg)
reset_ts(arg_temp(arg));
}
-/* Reset all temporaries, given that there are NB_TEMPS of them. */
-static void reset_all_temps(int nb_temps)
-{
- bitmap_zero(temps_used.l, nb_temps);
-}
-
/* Initialize and activate a temporary. */
-static void init_ts_info(TCGTemp *ts)
+static void init_ts_info(struct tcg_temp_info *infos,
+ TCGTempSet *temps_used, TCGTemp *ts)
{
size_t idx = temp_idx(ts);
- if (!test_bit(idx, temps_used.l)) {
- struct tcg_temp_info *ti = &temps[idx];
+ if (!test_bit(idx, temps_used->l)) {
+ struct tcg_temp_info *ti = &infos[idx];
ts->state_ptr = ti;
ti->next_copy = ts;
ti->prev_copy = ts;
ti->is_const = false;
ti->mask = -1;
- set_bit(idx, temps_used.l);
+ set_bit(idx, temps_used->l);
}
}
-static void init_arg_info(TCGArg arg)
+static void init_arg_info(struct tcg_temp_info *infos,
+ TCGTempSet *temps_used, TCGArg arg)
{
- init_ts_info(arg_temp(arg));
+ init_ts_info(infos, temps_used, arg_temp(arg));
}
static int op_bits(TCGOpcode op)
@@ -611,6 +604,8 @@ void tcg_optimize(TCGContext *s)
{
int oi, oi_next, nb_temps, nb_globals;
TCGOp *prev_mb = NULL;
+ struct tcg_temp_info *infos;
+ TCGTempSet temps_used;
/* Array VALS has an element for each temp.
If this temp holds a constant then its value is kept in VALS' element.
@@ -619,7 +614,8 @@ void tcg_optimize(TCGContext *s)
nb_temps = s->nb_temps;
nb_globals = s->nb_globals;
- reset_all_temps(nb_temps);
+ bitmap_zero(temps_used.l, nb_temps);
+ infos = tcg_malloc(sizeof(struct tcg_temp_info) * nb_temps);
for (oi = s->gen_op_buf[0].next; oi != 0; oi = oi_next) {
tcg_target_ulong mask, partmask, affected;
@@ -640,14 +636,14 @@ void tcg_optimize(TCGContext *s)
for (i = 0; i < nb_oargs + nb_iargs; i++) {
TCGTemp *ts = arg_temp(op->args[i]);
if (ts) {
- init_ts_info(ts);
+ init_ts_info(infos, &temps_used, ts);
}
}
} else {
nb_oargs = def->nb_oargs;
nb_iargs = def->nb_iargs;
for (i = 0; i < nb_oargs + nb_iargs; i++) {
- init_arg_info(op->args[i]);
+ init_arg_info(infos, &temps_used, op->args[i]);
}
}
@@ -1208,7 +1204,7 @@ void tcg_optimize(TCGContext *s)
op->args[1], op->args[2]);
if (tmp != 2) {
if (tmp) {
- reset_all_temps(nb_temps);
+ bitmap_zero(temps_used.l, nb_temps);
op->opc = INDEX_op_br;
op->args[0] = op->args[3];
} else {
@@ -1297,7 +1293,7 @@ void tcg_optimize(TCGContext *s)
if (tmp != 2) {
if (tmp) {
do_brcond_true:
- reset_all_temps(nb_temps);
+ bitmap_zero(temps_used.l, nb_temps);
op->opc = INDEX_op_br;
op->args[0] = op->args[5];
} else {
@@ -1313,7 +1309,7 @@ void tcg_optimize(TCGContext *s)
/* Simplify LT/GE comparisons vs zero to a single compare
vs the high word of the input. */
do_brcond_high:
- reset_all_temps(nb_temps);
+ bitmap_zero(temps_used.l, nb_temps);
op->opc = INDEX_op_brcond_i32;
op->args[0] = op->args[1];
op->args[1] = op->args[3];
@@ -1339,7 +1335,7 @@ void tcg_optimize(TCGContext *s)
goto do_default;
}
do_brcond_low:
- reset_all_temps(nb_temps);
+ bitmap_zero(temps_used.l, nb_temps);
op->opc = INDEX_op_brcond_i32;
op->args[1] = op->args[2];
op->args[2] = op->args[4];
@@ -1459,7 +1455,7 @@ void tcg_optimize(TCGContext *s)
block, otherwise we only trash the output args. "mask" is
the non-zero bits mask for the first output arg. */
if (def->flags & TCG_OPF_BB_END) {
- reset_all_temps(nb_temps);
+ bitmap_zero(temps_used.l, nb_temps);
} else {
do_reset_output:
for (i = 0; i < nb_oargs; i++) {
--
2.13.6
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [Qemu-devel] [PULL 46/51] osdep: introduce qemu_mprotect_rwx/none
2017-10-25 9:34 [Qemu-devel] [PULL 00/51] tcg queued patches Richard Henderson
` (44 preceding siblings ...)
2017-10-25 9:35 ` [Qemu-devel] [PULL 45/51] tcg: allocate optimizer temps with tcg_malloc Richard Henderson
@ 2017-10-25 9:35 ` Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 47/51] translate-all: use qemu_protect_rwx/none helpers Richard Henderson
` (7 subsequent siblings)
53 siblings, 0 replies; 59+ messages in thread
From: Richard Henderson @ 2017-10-25 9:35 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Emilio G. Cota
From: "Emilio G. Cota" <cota@braap.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/qemu/osdep.h | 2 ++
util/osdep.c | 41 +++++++++++++++++++++++++++++++++++++++++
2 files changed, 43 insertions(+)
diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h
index 826650c58a..281782d526 100644
--- a/include/qemu/osdep.h
+++ b/include/qemu/osdep.h
@@ -371,6 +371,8 @@ void sigaction_invoke(struct sigaction *action,
#endif
int qemu_madvise(void *addr, size_t len, int advice);
+int qemu_mprotect_rwx(void *addr, size_t size);
+int qemu_mprotect_none(void *addr, size_t size);
int qemu_open(const char *name, int flags, ...);
int qemu_close(int fd);
diff --git a/util/osdep.c b/util/osdep.c
index a479fedc4a..1231f9f876 100644
--- a/util/osdep.c
+++ b/util/osdep.c
@@ -73,6 +73,47 @@ int qemu_madvise(void *addr, size_t len, int advice)
#endif
}
+static int qemu_mprotect__osdep(void *addr, size_t size, int prot)
+{
+ g_assert(!((uintptr_t)addr & ~qemu_real_host_page_mask));
+ g_assert(!(size & ~qemu_real_host_page_mask));
+
+#ifdef _WIN32
+ DWORD old_protect;
+
+ if (!VirtualProtect(addr, size, prot, &old_protect)) {
+ error_report("%s: VirtualProtect failed with error code %ld",
+ __func__, GetLastError());
+ return -1;
+ }
+ return 0;
+#else
+ if (mprotect(addr, size, prot)) {
+ error_report("%s: mprotect failed: %s", __func__, strerror(errno));
+ return -1;
+ }
+ return 0;
+#endif
+}
+
+int qemu_mprotect_rwx(void *addr, size_t size)
+{
+#ifdef _WIN32
+ return qemu_mprotect__osdep(addr, size, PAGE_EXECUTE_READWRITE);
+#else
+ return qemu_mprotect__osdep(addr, size, PROT_READ | PROT_WRITE | PROT_EXEC);
+#endif
+}
+
+int qemu_mprotect_none(void *addr, size_t size)
+{
+#ifdef _WIN32
+ return qemu_mprotect__osdep(addr, size, PAGE_NOACCESS);
+#else
+ return qemu_mprotect__osdep(addr, size, PROT_NONE);
+#endif
+}
+
#ifndef _WIN32
static int fcntl_op_setlk = -1;
--
2.13.6
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [Qemu-devel] [PULL 47/51] translate-all: use qemu_protect_rwx/none helpers
2017-10-25 9:34 [Qemu-devel] [PULL 00/51] tcg queued patches Richard Henderson
` (45 preceding siblings ...)
2017-10-25 9:35 ` [Qemu-devel] [PULL 46/51] osdep: introduce qemu_mprotect_rwx/none Richard Henderson
@ 2017-10-25 9:35 ` Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 48/51] tcg: introduce regions to split code_gen_buffer Richard Henderson
` (6 subsequent siblings)
53 siblings, 0 replies; 59+ messages in thread
From: Richard Henderson @ 2017-10-25 9:35 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Emilio G. Cota
From: "Emilio G. Cota" <cota@braap.org>
The helpers require the address and size to be page-aligned, so
do that before calling them.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/translate-all.c | 61 ++++++++++-------------------------------------
1 file changed, 13 insertions(+), 48 deletions(-)
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index 78c150af3e..9061c0508c 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -602,63 +602,24 @@ static inline void *split_cross_256mb(void *buf1, size_t size1)
static uint8_t static_code_gen_buffer[DEFAULT_CODE_GEN_BUFFER_SIZE]
__attribute__((aligned(CODE_GEN_ALIGN)));
-# ifdef _WIN32
-static inline void do_protect(void *addr, long size, int prot)
-{
- DWORD old_protect;
- VirtualProtect(addr, size, prot, &old_protect);
-}
-
-static inline void map_exec(void *addr, long size)
-{
- do_protect(addr, size, PAGE_EXECUTE_READWRITE);
-}
-
-static inline void map_none(void *addr, long size)
-{
- do_protect(addr, size, PAGE_NOACCESS);
-}
-# else
-static inline void do_protect(void *addr, long size, int prot)
-{
- uintptr_t start, end;
-
- start = (uintptr_t)addr;
- start &= qemu_real_host_page_mask;
-
- end = (uintptr_t)addr + size;
- end = ROUND_UP(end, qemu_real_host_page_size);
-
- mprotect((void *)start, end - start, prot);
-}
-
-static inline void map_exec(void *addr, long size)
-{
- do_protect(addr, size, PROT_READ | PROT_WRITE | PROT_EXEC);
-}
-
-static inline void map_none(void *addr, long size)
-{
- do_protect(addr, size, PROT_NONE);
-}
-# endif /* WIN32 */
-
static inline void *alloc_code_gen_buffer(void)
{
void *buf = static_code_gen_buffer;
+ void *end = static_code_gen_buffer + sizeof(static_code_gen_buffer);
size_t full_size, size;
- /* The size of the buffer, rounded down to end on a page boundary. */
- full_size = (((uintptr_t)buf + sizeof(static_code_gen_buffer))
- & qemu_real_host_page_mask) - (uintptr_t)buf;
+ /* page-align the beginning and end of the buffer */
+ buf = QEMU_ALIGN_PTR_UP(buf, qemu_real_host_page_size);
+ end = QEMU_ALIGN_PTR_DOWN(end, qemu_real_host_page_size);
/* Reserve a guard page. */
+ full_size = end - buf;
size = full_size - qemu_real_host_page_size;
/* Honor a command-line option limiting the size of the buffer. */
if (size > tcg_ctx->code_gen_buffer_size) {
- size = (((uintptr_t)buf + tcg_ctx->code_gen_buffer_size)
- & qemu_real_host_page_mask) - (uintptr_t)buf;
+ size = QEMU_ALIGN_DOWN(tcg_ctx->code_gen_buffer_size,
+ qemu_real_host_page_size);
}
tcg_ctx->code_gen_buffer_size = size;
@@ -669,8 +630,12 @@ static inline void *alloc_code_gen_buffer(void)
}
#endif
- map_exec(buf, size);
- map_none(buf + size, qemu_real_host_page_size);
+ if (qemu_mprotect_rwx(buf, size)) {
+ abort();
+ }
+ if (qemu_mprotect_none(buf + size, qemu_real_host_page_size)) {
+ abort();
+ }
qemu_madvise(buf, size, QEMU_MADV_HUGEPAGE);
return buf;
--
2.13.6
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [Qemu-devel] [PULL 48/51] tcg: introduce regions to split code_gen_buffer
2017-10-25 9:34 [Qemu-devel] [PULL 00/51] tcg queued patches Richard Henderson
` (46 preceding siblings ...)
2017-10-25 9:35 ` [Qemu-devel] [PULL 47/51] translate-all: use qemu_protect_rwx/none helpers Richard Henderson
@ 2017-10-25 9:35 ` Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 49/51] tcg: enable multiple TCG contexts in softmmu Richard Henderson
` (5 subsequent siblings)
53 siblings, 0 replies; 59+ messages in thread
From: Richard Henderson @ 2017-10-25 9:35 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Emilio G. Cota
From: "Emilio G. Cota" <cota@braap.org>
This is groundwork for supporting multiple TCG contexts.
The naive solution here is to split code_gen_buffer statically
among the TCG threads; this however results in poor utilization
if translation needs are different across TCG threads.
What we do here is to add an extra layer of indirection, assigning
regions that act just like pages do in virtual memory allocation.
(BTW if you are wondering about the chosen naming, I did not want
to use blocks or pages because those are already heavily used in QEMU).
We use a global lock to serialize allocations as well as statistics
reporting (we now export the size of the used code_gen_buffer with
tcg_code_size()). Note that for the allocator we could just use
a counter and atomic_inc; however, that would complicate the gathering
of tcg_code_size()-like stats. So given that the region operations are
not a fast path, a lock seems the most reasonable choice.
The effectiveness of this approach is clear after seeing some numbers.
I used the bootup+shutdown of debian-arm with '-tb-size 80' as a benchmark.
Note that I'm evaluating this after enabling per-thread TCG (which
is done by a subsequent commit).
* -smp 1, 1 region (entire buffer):
qemu: flush code_size=83885014 nb_tbs=154739 avg_tb_size=357
qemu: flush code_size=83884902 nb_tbs=153136 avg_tb_size=363
qemu: flush code_size=83885014 nb_tbs=152777 avg_tb_size=364
qemu: flush code_size=83884950 nb_tbs=150057 avg_tb_size=373
qemu: flush code_size=83884998 nb_tbs=150234 avg_tb_size=373
qemu: flush code_size=83885014 nb_tbs=154009 avg_tb_size=360
qemu: flush code_size=83885014 nb_tbs=151007 avg_tb_size=370
qemu: flush code_size=83885014 nb_tbs=151816 avg_tb_size=367
That is, 8 flushes.
* -smp 8, 32 regions (80/32 MB per region) [i.e. this patch]:
qemu: flush code_size=76328008 nb_tbs=141040 avg_tb_size=356
qemu: flush code_size=75366534 nb_tbs=138000 avg_tb_size=361
qemu: flush code_size=76864546 nb_tbs=140653 avg_tb_size=361
qemu: flush code_size=76309084 nb_tbs=135945 avg_tb_size=375
qemu: flush code_size=74581856 nb_tbs=132909 avg_tb_size=375
qemu: flush code_size=73927256 nb_tbs=135616 avg_tb_size=360
qemu: flush code_size=78629426 nb_tbs=142896 avg_tb_size=365
qemu: flush code_size=76667052 nb_tbs=138508 avg_tb_size=368
Again, 8 flushes. Note how buffer utilization is not 100%, but it
is close. Smaller region sizes would yield higher utilization,
but we want region allocation to be rare (it acquires a lock), so
we do not want to go too small.
* -smp 8, static partitioning of 8 regions (10 MB per region):
qemu: flush code_size=21936504 nb_tbs=40570 avg_tb_size=354
qemu: flush code_size=11472174 nb_tbs=20633 avg_tb_size=370
qemu: flush code_size=11603976 nb_tbs=21059 avg_tb_size=365
qemu: flush code_size=23254872 nb_tbs=41243 avg_tb_size=377
qemu: flush code_size=28289496 nb_tbs=52057 avg_tb_size=358
qemu: flush code_size=43605160 nb_tbs=78896 avg_tb_size=367
qemu: flush code_size=45166552 nb_tbs=82158 avg_tb_size=364
qemu: flush code_size=63289640 nb_tbs=116494 avg_tb_size=358
qemu: flush code_size=51389960 nb_tbs=93937 avg_tb_size=362
qemu: flush code_size=59665928 nb_tbs=107063 avg_tb_size=372
qemu: flush code_size=38380824 nb_tbs=68597 avg_tb_size=374
qemu: flush code_size=44884568 nb_tbs=79901 avg_tb_size=376
qemu: flush code_size=50782632 nb_tbs=90681 avg_tb_size=374
qemu: flush code_size=39848888 nb_tbs=71433 avg_tb_size=372
qemu: flush code_size=64708840 nb_tbs=119052 avg_tb_size=359
qemu: flush code_size=49830008 nb_tbs=90992 avg_tb_size=362
qemu: flush code_size=68372408 nb_tbs=123442 avg_tb_size=368
qemu: flush code_size=33555560 nb_tbs=59514 avg_tb_size=378
qemu: flush code_size=44748344 nb_tbs=80974 avg_tb_size=367
qemu: flush code_size=37104248 nb_tbs=67609 avg_tb_size=364
That is, 20 flushes. Note how a static partitioning approach uses
the code buffer poorly, leading to many unnecessary flushes.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tcg.h | 6 ++
accel/tcg/translate-all.c | 63 +++++--------
bsd-user/main.c | 1 +
cpus.c | 12 +++
linux-user/main.c | 1 +
tcg/tcg.c | 222 +++++++++++++++++++++++++++++++++++++++++++++-
6 files changed, 260 insertions(+), 45 deletions(-)
diff --git a/tcg/tcg.h b/tcg/tcg.h
index 4b9958a179..9f95648282 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -802,6 +802,12 @@ void *tcg_malloc_internal(TCGContext *s, int size);
void tcg_pool_reset(TCGContext *s);
TranslationBlock *tcg_tb_alloc(TCGContext *s);
+void tcg_region_init(void);
+void tcg_region_reset_all(void);
+
+size_t tcg_code_size(void);
+size_t tcg_code_capacity(void);
+
/* Called with tb_lock held. */
static inline void *tcg_malloc(int size)
{
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index 9061c0508c..f99bfd9309 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -606,15 +606,13 @@ static inline void *alloc_code_gen_buffer(void)
{
void *buf = static_code_gen_buffer;
void *end = static_code_gen_buffer + sizeof(static_code_gen_buffer);
- size_t full_size, size;
+ size_t size;
/* page-align the beginning and end of the buffer */
buf = QEMU_ALIGN_PTR_UP(buf, qemu_real_host_page_size);
end = QEMU_ALIGN_PTR_DOWN(end, qemu_real_host_page_size);
- /* Reserve a guard page. */
- full_size = end - buf;
- size = full_size - qemu_real_host_page_size;
+ size = end - buf;
/* Honor a command-line option limiting the size of the buffer. */
if (size > tcg_ctx->code_gen_buffer_size) {
@@ -633,9 +631,6 @@ static inline void *alloc_code_gen_buffer(void)
if (qemu_mprotect_rwx(buf, size)) {
abort();
}
- if (qemu_mprotect_none(buf + size, qemu_real_host_page_size)) {
- abort();
- }
qemu_madvise(buf, size, QEMU_MADV_HUGEPAGE);
return buf;
@@ -644,22 +639,16 @@ static inline void *alloc_code_gen_buffer(void)
static inline void *alloc_code_gen_buffer(void)
{
size_t size = tcg_ctx->code_gen_buffer_size;
- void *buf1, *buf2;
-
- /* Perform the allocation in two steps, so that the guard page
- is reserved but uncommitted. */
- buf1 = VirtualAlloc(NULL, size + qemu_real_host_page_size,
- MEM_RESERVE, PAGE_NOACCESS);
- if (buf1 != NULL) {
- buf2 = VirtualAlloc(buf1, size, MEM_COMMIT, PAGE_EXECUTE_READWRITE);
- assert(buf1 == buf2);
- }
+ void *buf;
- return buf1;
+ buf = VirtualAlloc(NULL, size, MEM_RESERVE | MEM_COMMIT,
+ PAGE_EXECUTE_READWRITE);
+ return buf;
}
#else
static inline void *alloc_code_gen_buffer(void)
{
+ int prot = PROT_WRITE | PROT_READ | PROT_EXEC;
int flags = MAP_PRIVATE | MAP_ANONYMOUS;
uintptr_t start = 0;
size_t size = tcg_ctx->code_gen_buffer_size;
@@ -693,8 +682,7 @@ static inline void *alloc_code_gen_buffer(void)
# endif
# endif
- buf = mmap((void *)start, size + qemu_real_host_page_size,
- PROT_NONE, flags, -1, 0);
+ buf = mmap((void *)start, size, prot, flags, -1, 0);
if (buf == MAP_FAILED) {
return NULL;
}
@@ -704,24 +692,23 @@ static inline void *alloc_code_gen_buffer(void)
/* Try again, with the original still mapped, to avoid re-acquiring
that 256mb crossing. This time don't specify an address. */
size_t size2;
- void *buf2 = mmap(NULL, size + qemu_real_host_page_size,
- PROT_NONE, flags, -1, 0);
+ void *buf2 = mmap(NULL, size, prot, flags, -1, 0);
switch ((int)(buf2 != MAP_FAILED)) {
case 1:
if (!cross_256mb(buf2, size)) {
/* Success! Use the new buffer. */
- munmap(buf, size + qemu_real_host_page_size);
+ munmap(buf, size);
break;
}
/* Failure. Work with what we had. */
- munmap(buf2, size + qemu_real_host_page_size);
+ munmap(buf2, size);
/* fallthru */
default:
/* Split the original buffer. Free the smaller half. */
buf2 = split_cross_256mb(buf, size);
size2 = tcg_ctx->code_gen_buffer_size;
if (buf == buf2) {
- munmap(buf + size2 + qemu_real_host_page_size, size - size2);
+ munmap(buf + size2, size - size2);
} else {
munmap(buf, size - size2);
}
@@ -732,10 +719,6 @@ static inline void *alloc_code_gen_buffer(void)
}
#endif
- /* Make the final buffer accessible. The guard page at the end
- will remain inaccessible with PROT_NONE. */
- mprotect(buf, size, PROT_WRITE | PROT_READ | PROT_EXEC);
-
/* Request large pages for the buffer. */
qemu_madvise(buf, size, QEMU_MADV_HUGEPAGE);
@@ -916,13 +899,8 @@ static void do_tb_flush(CPUState *cpu, run_on_cpu_data tb_flush_count)
size_t host_size = 0;
g_tree_foreach(tb_ctx.tb_tree, tb_host_size_iter, &host_size);
- printf("qemu: flush code_size=%td nb_tbs=%zu avg_tb_size=%zu\n",
- tcg_ctx->code_gen_ptr - tcg_ctx->code_gen_buffer, nb_tbs,
- nb_tbs > 0 ? host_size / nb_tbs : 0);
- }
- if ((unsigned long)(tcg_ctx->code_gen_ptr - tcg_ctx->code_gen_buffer)
- > tcg_ctx->code_gen_buffer_size) {
- cpu_abort(cpu, "Internal error: code buffer overflow\n");
+ printf("qemu: flush code_size=%zu nb_tbs=%zu avg_tb_size=%zu\n",
+ tcg_code_size(), nb_tbs, nb_tbs > 0 ? host_size / nb_tbs : 0);
}
CPU_FOREACH(cpu) {
@@ -936,7 +914,7 @@ static void do_tb_flush(CPUState *cpu, run_on_cpu_data tb_flush_count)
qht_reset_size(&tb_ctx.htable, CODE_GEN_HTABLE_SIZE);
page_flush_tb();
- tcg_ctx->code_gen_ptr = tcg_ctx->code_gen_buffer;
+ tcg_region_reset_all();
/* XXX: flush processor icache at this point if cache flush is
expensive */
atomic_mb_set(&tb_ctx.tb_flush_count, tb_ctx.tb_flush_count + 1);
@@ -1274,9 +1252,9 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
phys_pc = get_page_addr_code(env, pc);
+ buffer_overflow:
tb = tb_alloc(pc);
if (unlikely(!tb)) {
- buffer_overflow:
/* flush must be done */
tb_flush(cpu);
mmap_unlock();
@@ -1380,9 +1358,9 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
}
#endif
- tcg_ctx->code_gen_ptr = (void *)
+ atomic_set(&tcg_ctx->code_gen_ptr, (void *)
ROUND_UP((uintptr_t)gen_code_buf + gen_code_size + search_size,
- CODE_GEN_ALIGN);
+ CODE_GEN_ALIGN));
/* init jump list */
assert(((uintptr_t)tb & 3) == 0);
@@ -1908,9 +1886,8 @@ void dump_exec_info(FILE *f, fprintf_function cpu_fprintf)
* otherwise users might think "-tb-size" is not honoured.
* For avg host size we use the precise numbers from tb_tree_stats though.
*/
- cpu_fprintf(f, "gen code size %td/%zd\n",
- tcg_ctx->code_gen_ptr - tcg_ctx->code_gen_buffer,
- tcg_ctx->code_gen_highwater - tcg_ctx->code_gen_buffer);
+ cpu_fprintf(f, "gen code size %zu/%zu\n",
+ tcg_code_size(), tcg_code_capacity());
cpu_fprintf(f, "TB count %zu\n", nb_tbs);
cpu_fprintf(f, "TB avg target size %zu max=%zu bytes\n",
nb_tbs ? tst.target_size / nb_tbs : 0,
diff --git a/bsd-user/main.c b/bsd-user/main.c
index 392c0ed5fb..f1b244b59b 100644
--- a/bsd-user/main.c
+++ b/bsd-user/main.c
@@ -978,6 +978,7 @@ int main(int argc, char **argv)
generating the prologue until now so that the prologue can take
the real value of GUEST_BASE into account. */
tcg_prologue_init(tcg_ctx);
+ tcg_region_init();
/* build Task State */
memset(ts, 0, sizeof(TaskState));
diff --git a/cpus.c b/cpus.c
index c9a624003a..8e06257a74 100644
--- a/cpus.c
+++ b/cpus.c
@@ -1664,6 +1664,18 @@ static void qemu_tcg_init_vcpu(CPUState *cpu)
char thread_name[VCPU_THREAD_NAME_SIZE];
static QemuCond *single_tcg_halt_cond;
static QemuThread *single_tcg_cpu_thread;
+ static int tcg_region_inited;
+
+ /*
+ * Initialize TCG regions--once. Now is a good time, because:
+ * (1) TCG's init context, prologue and target globals have been set up.
+ * (2) qemu_tcg_mttcg_enabled() works now (TCG init code runs before the
+ * -accel flag is processed, so the check doesn't work then).
+ */
+ if (!tcg_region_inited) {
+ tcg_region_inited = 1;
+ tcg_region_init();
+ }
if (qemu_tcg_mttcg_enabled() || !single_tcg_cpu_thread) {
cpu->thread = g_malloc0(sizeof(QemuThread));
diff --git a/linux-user/main.c b/linux-user/main.c
index 8814906409..28353f1a75 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -4477,6 +4477,7 @@ int main(int argc, char **argv, char **envp)
generating the prologue until now so that the prologue can take
the real value of GUEST_BASE into account. */
tcg_prologue_init(tcg_ctx);
+ tcg_region_init();
#if defined(TARGET_I386)
env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK;
diff --git a/tcg/tcg.c b/tcg/tcg.c
index f1bbfe37ff..3de5f7cf97 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -121,6 +121,30 @@ static bool tcg_out_ldst_finalize(TCGContext *s);
static TCGContext **tcg_ctxs;
static unsigned int n_tcg_ctxs;
+/*
+ * We divide code_gen_buffer into equally-sized "regions" that TCG threads
+ * dynamically allocate from as demand dictates. Given appropriate region
+ * sizing, this minimizes flushes even when some TCG threads generate a lot
+ * more code than others.
+ */
+struct tcg_region_state {
+ QemuMutex lock;
+
+ /* fields set at init time */
+ void *start;
+ void *start_aligned;
+ void *end;
+ size_t n;
+ size_t size; /* size of one region */
+ size_t stride; /* .size + guard size */
+
+ /* fields protected by the lock */
+ size_t current; /* current region index */
+ size_t agg_size_full; /* aggregate size of full regions */
+};
+
+static struct tcg_region_state region;
+
static TCGRegSet tcg_target_available_regs[2];
static TCGRegSet tcg_target_call_clobber_regs;
@@ -258,6 +282,196 @@ TCGLabel *gen_new_label(void)
#include "tcg-target.inc.c"
+static void tcg_region_bounds(size_t curr_region, void **pstart, void **pend)
+{
+ void *start, *end;
+
+ start = region.start_aligned + curr_region * region.stride;
+ end = start + region.size;
+
+ if (curr_region == 0) {
+ start = region.start;
+ }
+ if (curr_region == region.n - 1) {
+ end = region.end;
+ }
+
+ *pstart = start;
+ *pend = end;
+}
+
+static void tcg_region_assign(TCGContext *s, size_t curr_region)
+{
+ void *start, *end;
+
+ tcg_region_bounds(curr_region, &start, &end);
+
+ s->code_gen_buffer = start;
+ s->code_gen_ptr = start;
+ s->code_gen_buffer_size = end - start;
+ s->code_gen_highwater = end - TCG_HIGHWATER;
+}
+
+static bool tcg_region_alloc__locked(TCGContext *s)
+{
+ if (region.current == region.n) {
+ return true;
+ }
+ tcg_region_assign(s, region.current);
+ region.current++;
+ return false;
+}
+
+/*
+ * Request a new region once the one in use has filled up.
+ * Returns true on error.
+ */
+static bool tcg_region_alloc(TCGContext *s)
+{
+ bool err;
+ /* read the region size now; alloc__locked will overwrite it on success */
+ size_t size_full = s->code_gen_buffer_size;
+
+ qemu_mutex_lock(®ion.lock);
+ err = tcg_region_alloc__locked(s);
+ if (!err) {
+ region.agg_size_full += size_full - TCG_HIGHWATER;
+ }
+ qemu_mutex_unlock(®ion.lock);
+ return err;
+}
+
+/*
+ * Perform a context's first region allocation.
+ * This function does _not_ increment region.agg_size_full.
+ */
+static inline bool tcg_region_initial_alloc__locked(TCGContext *s)
+{
+ return tcg_region_alloc__locked(s);
+}
+
+/* Call from a safe-work context */
+void tcg_region_reset_all(void)
+{
+ unsigned int i;
+
+ qemu_mutex_lock(®ion.lock);
+ region.current = 0;
+ region.agg_size_full = 0;
+
+ for (i = 0; i < n_tcg_ctxs; i++) {
+ bool err = tcg_region_initial_alloc__locked(tcg_ctxs[i]);
+
+ g_assert(!err);
+ }
+ qemu_mutex_unlock(®ion.lock);
+}
+
+/*
+ * Initializes region partitioning.
+ *
+ * Called at init time from the parent thread (i.e. the one calling
+ * tcg_context_init), after the target's TCG globals have been set.
+ */
+void tcg_region_init(void)
+{
+ void *buf = tcg_init_ctx.code_gen_buffer;
+ void *aligned;
+ size_t size = tcg_init_ctx.code_gen_buffer_size;
+ size_t page_size = qemu_real_host_page_size;
+ size_t region_size;
+ size_t n_regions;
+ size_t i;
+
+ /* We do not yet support multiple TCG contexts, so use one region for now */
+ n_regions = 1;
+
+ /* The first region will be 'aligned - buf' bytes larger than the others */
+ aligned = QEMU_ALIGN_PTR_UP(buf, page_size);
+ g_assert(aligned < tcg_init_ctx.code_gen_buffer + size);
+ /*
+ * Make region_size a multiple of page_size, using aligned as the start.
+ * As a result of this we might end up with a few extra pages at the end of
+ * the buffer; we will assign those to the last region.
+ */
+ region_size = (size - (aligned - buf)) / n_regions;
+ region_size = QEMU_ALIGN_DOWN(region_size, page_size);
+
+ /* A region must have at least 2 pages; one code, one guard */
+ g_assert(region_size >= 2 * page_size);
+
+ /* init the region struct */
+ qemu_mutex_init(®ion.lock);
+ region.n = n_regions;
+ region.size = region_size - page_size;
+ region.stride = region_size;
+ region.start = buf;
+ region.start_aligned = aligned;
+ /* page-align the end, since its last page will be a guard page */
+ region.end = QEMU_ALIGN_PTR_DOWN(buf + size, page_size);
+ /* account for that last guard page */
+ region.end -= page_size;
+
+ /* set guard pages */
+ for (i = 0; i < region.n; i++) {
+ void *start, *end;
+ int rc;
+
+ tcg_region_bounds(i, &start, &end);
+ rc = qemu_mprotect_none(end, page_size);
+ g_assert(!rc);
+ }
+
+ /* We do not yet support multiple TCG contexts so allocate the region now */
+ {
+ bool err = tcg_region_initial_alloc__locked(tcg_ctx);
+
+ g_assert(!err);
+ }
+}
+
+/*
+ * Returns the size (in bytes) of all translated code (i.e. from all regions)
+ * currently in the cache.
+ * See also: tcg_code_capacity()
+ * Do not confuse with tcg_current_code_size(); that one applies to a single
+ * TCG context.
+ */
+size_t tcg_code_size(void)
+{
+ unsigned int i;
+ size_t total;
+
+ qemu_mutex_lock(®ion.lock);
+ total = region.agg_size_full;
+ for (i = 0; i < n_tcg_ctxs; i++) {
+ const TCGContext *s = tcg_ctxs[i];
+ size_t size;
+
+ size = atomic_read(&s->code_gen_ptr) - s->code_gen_buffer;
+ g_assert(size <= s->code_gen_buffer_size);
+ total += size;
+ }
+ qemu_mutex_unlock(®ion.lock);
+ return total;
+}
+
+/*
+ * Returns the code capacity (in bytes) of the entire cache, i.e. including all
+ * regions.
+ * See also: tcg_code_size()
+ */
+size_t tcg_code_capacity(void)
+{
+ size_t guard_size, capacity;
+
+ /* no need for synchronization; these variables are set at init time */
+ guard_size = region.stride - region.size;
+ capacity = region.end + guard_size - region.start;
+ capacity -= region.n * (guard_size + TCG_HIGHWATER);
+ return capacity;
+}
+
/* pool based memory allocation */
void *tcg_malloc_internal(TCGContext *s, int size)
{
@@ -401,13 +615,17 @@ TranslationBlock *tcg_tb_alloc(TCGContext *s)
TranslationBlock *tb;
void *next;
+ retry:
tb = (void *)ROUND_UP((uintptr_t)s->code_gen_ptr, align);
next = (void *)ROUND_UP((uintptr_t)(tb + 1), align);
if (unlikely(next > s->code_gen_highwater)) {
- return NULL;
+ if (tcg_region_alloc(s)) {
+ return NULL;
+ }
+ goto retry;
}
- s->code_gen_ptr = next;
+ atomic_set(&s->code_gen_ptr, next);
s->data_gen_ptr = NULL;
return tb;
}
--
2.13.6
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [Qemu-devel] [PULL 49/51] tcg: enable multiple TCG contexts in softmmu
2017-10-25 9:34 [Qemu-devel] [PULL 00/51] tcg queued patches Richard Henderson
` (47 preceding siblings ...)
2017-10-25 9:35 ` [Qemu-devel] [PULL 48/51] tcg: introduce regions to split code_gen_buffer Richard Henderson
@ 2017-10-25 9:35 ` Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 50/51] tcg: Initialize cpu_env generically Richard Henderson
` (4 subsequent siblings)
53 siblings, 0 replies; 59+ messages in thread
From: Richard Henderson @ 2017-10-25 9:35 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Emilio G. Cota
From: "Emilio G. Cota" <cota@braap.org>
This enables parallel TCG code generation. However, we do not take
advantage of it yet since tb_lock is still held during tb_gen_code.
In user-mode we use a single TCG context; see the documentation
added to tcg_region_init for the rationale.
Note that targets do not need any conversion: targets initialize a
TCGContext (e.g. defining TCG globals), and after this initialization
has finished, the context is cloned by the vCPU threads, each of
them keeping a separate copy.
TCG threads claim one entry in tcg_ctxs[] by atomically increasing
n_tcg_ctxs. Do not be too annoyed by the subsequent atomic_read's
of that variable and tcg_ctxs; they are there just to play nice with
analysis tools such as thread sanitizer.
Note that we do not allocate an array of contexts (we allocate
an array of pointers instead) because when tcg_context_init
is called, we do not know yet how many contexts we'll use since
the bool behind qemu_tcg_mttcg_enabled() isn't set yet.
Previous patches folded some TCG globals into TCGContext. The non-const
globals remaining are only set at init time, i.e. before the TCG
threads are spawned. Here is a list of these set-at-init-time globals
under tcg/:
Only written by tcg_context_init:
- indirect_reg_alloc_order
- tcg_op_defs
Only written by tcg_target_init (called from tcg_context_init):
- tcg_target_available_regs
- tcg_target_call_clobber_regs
- arm: arm_arch, use_idiv_instructions
- i386: have_cmov, have_bmi1, have_bmi2, have_lzcnt,
have_movbe, have_popcnt
- mips: use_movnz_instructions, use_mips32_instructions,
use_mips32r2_instructions, got_sigill (tcg_target_detect_isa)
- ppc: have_isa_2_06, have_isa_3_00, tb_ret_addr
- s390: tb_ret_addr, s390_facilities
- sparc: qemu_ld_trampoline, qemu_st_trampoline (build_trampolines),
use_vis3_instructions
Only written by tcg_prologue_init:
- 'struct jit_code_entry one_entry'
- aarch64: tb_ret_addr
- arm: tb_ret_addr
- i386: tb_ret_addr, guest_base_flags
- ia64: tb_ret_addr
- mips: tb_ret_addr, bswap32_addr, bswap32u_addr, bswap64_addr
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tcg.h | 7 ++-
accel/tcg/translate-all.c | 2 +-
cpus.c | 2 +
linux-user/syscall.c | 1 +
tcg/tcg.c | 146 +++++++++++++++++++++++++++++++++++++++++++---
5 files changed, 145 insertions(+), 13 deletions(-)
diff --git a/tcg/tcg.h b/tcg/tcg.h
index 9f95648282..3d022e448b 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -695,7 +695,7 @@ struct TCGContext {
};
extern TCGContext tcg_init_ctx;
-extern TCGContext *tcg_ctx;
+extern __thread TCGContext *tcg_ctx;
static inline size_t temp_idx(TCGTemp *ts)
{
@@ -797,7 +797,7 @@ static inline bool tcg_op_buf_full(void)
/* pool based memory allocation */
-/* tb_lock must be held for tcg_malloc_internal. */
+/* user-mode: tb_lock must be held for tcg_malloc_internal. */
void *tcg_malloc_internal(TCGContext *s, int size);
void tcg_pool_reset(TCGContext *s);
TranslationBlock *tcg_tb_alloc(TCGContext *s);
@@ -808,7 +808,7 @@ void tcg_region_reset_all(void);
size_t tcg_code_size(void);
size_t tcg_code_capacity(void);
-/* Called with tb_lock held. */
+/* user-mode: Called with tb_lock held. */
static inline void *tcg_malloc(int size)
{
TCGContext *s = tcg_ctx;
@@ -828,6 +828,7 @@ static inline void *tcg_malloc(int size)
}
void tcg_context_init(TCGContext *s);
+void tcg_register_thread(void);
void tcg_prologue_init(TCGContext *s);
void tcg_func_start(TCGContext *s);
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index f99bfd9309..5724149289 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -154,7 +154,7 @@ static void *l1_map[V_L1_MAX_SIZE];
/* code generation context */
TCGContext tcg_init_ctx;
-TCGContext *tcg_ctx;
+__thread TCGContext *tcg_ctx;
TBContext tb_ctx;
bool parallel_cpus;
diff --git a/cpus.c b/cpus.c
index 8e06257a74..114c29b6a0 100644
--- a/cpus.c
+++ b/cpus.c
@@ -1307,6 +1307,7 @@ static void *qemu_tcg_rr_cpu_thread_fn(void *arg)
CPUState *cpu = arg;
rcu_register_thread();
+ tcg_register_thread();
qemu_mutex_lock_iothread();
qemu_thread_get_self(cpu->thread);
@@ -1454,6 +1455,7 @@ static void *qemu_tcg_cpu_thread_fn(void *arg)
g_assert(!use_icount);
rcu_register_thread();
+ tcg_register_thread();
qemu_mutex_lock_iothread();
qemu_thread_get_self(cpu->thread);
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 9bf901fa11..d4497dec5d 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -6218,6 +6218,7 @@ static void *clone_func(void *arg)
TaskState *ts;
rcu_register_thread();
+ tcg_register_thread();
env = info->env;
cpu = ENV_GET_CPU(env);
thread_cpu = cpu;
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 3de5f7cf97..5574317736 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -58,6 +58,7 @@
#include "elf.h"
#include "exec/log.h"
+#include "sysemu/sysemu.h"
/* Forward declarations for functions declared in tcg-target.inc.c and
used here. */
@@ -353,25 +354,87 @@ static inline bool tcg_region_initial_alloc__locked(TCGContext *s)
/* Call from a safe-work context */
void tcg_region_reset_all(void)
{
+ unsigned int n_ctxs = atomic_read(&n_tcg_ctxs);
unsigned int i;
qemu_mutex_lock(®ion.lock);
region.current = 0;
region.agg_size_full = 0;
- for (i = 0; i < n_tcg_ctxs; i++) {
- bool err = tcg_region_initial_alloc__locked(tcg_ctxs[i]);
+ for (i = 0; i < n_ctxs; i++) {
+ TCGContext *s = atomic_read(&tcg_ctxs[i]);
+ bool err = tcg_region_initial_alloc__locked(s);
g_assert(!err);
}
qemu_mutex_unlock(®ion.lock);
}
+#ifdef CONFIG_USER_ONLY
+static size_t tcg_n_regions(void)
+{
+ return 1;
+}
+#else
+/*
+ * It is likely that some vCPUs will translate more code than others, so we
+ * first try to set more regions than max_cpus, with those regions being of
+ * reasonable size. If that's not possible we make do by evenly dividing
+ * the code_gen_buffer among the vCPUs.
+ */
+static size_t tcg_n_regions(void)
+{
+ size_t i;
+
+ /* Use a single region if all we have is one vCPU thread */
+ if (max_cpus == 1 || !qemu_tcg_mttcg_enabled()) {
+ return 1;
+ }
+
+ /* Try to have more regions than max_cpus, with each region being >= 2 MB */
+ for (i = 8; i > 0; i--) {
+ size_t regions_per_thread = i;
+ size_t region_size;
+
+ region_size = tcg_init_ctx.code_gen_buffer_size;
+ region_size /= max_cpus * regions_per_thread;
+
+ if (region_size >= 2 * 1024u * 1024) {
+ return max_cpus * regions_per_thread;
+ }
+ }
+ /* If we can't, then just allocate one region per vCPU thread */
+ return max_cpus;
+}
+#endif
+
/*
* Initializes region partitioning.
*
* Called at init time from the parent thread (i.e. the one calling
* tcg_context_init), after the target's TCG globals have been set.
+ *
+ * Region partitioning works by splitting code_gen_buffer into separate regions,
+ * and then assigning regions to TCG threads so that the threads can translate
+ * code in parallel without synchronization.
+ *
+ * In softmmu the number of TCG threads is bounded by max_cpus, so we use at
+ * least max_cpus regions in MTTCG. In !MTTCG we use a single region.
+ * Note that the TCG options from the command-line (i.e. -accel accel=tcg,[...])
+ * must have been parsed before calling this function, since it calls
+ * qemu_tcg_mttcg_enabled().
+ *
+ * In user-mode we use a single region. Having multiple regions in user-mode
+ * is not supported, because the number of vCPU threads (recall that each thread
+ * spawned by the guest corresponds to a vCPU thread) is only bounded by the
+ * OS, and usually this number is huge (tens of thousands is not uncommon).
+ * Thus, given this large bound on the number of vCPU threads and the fact
+ * that code_gen_buffer is allocated at compile-time, we cannot guarantee
+ * that the availability of at least one region per vCPU thread.
+ *
+ * However, this user-mode limitation is unlikely to be a significant problem
+ * in practice. Multi-threaded guests share most if not all of their translated
+ * code, which makes parallel code generation less appealing than in softmmu.
*/
void tcg_region_init(void)
{
@@ -383,8 +446,7 @@ void tcg_region_init(void)
size_t n_regions;
size_t i;
- /* We do not yet support multiple TCG contexts, so use one region for now */
- n_regions = 1;
+ n_regions = tcg_n_regions();
/* The first region will be 'aligned - buf' bytes larger than the others */
aligned = QEMU_ALIGN_PTR_UP(buf, page_size);
@@ -422,13 +484,66 @@ void tcg_region_init(void)
g_assert(!rc);
}
- /* We do not yet support multiple TCG contexts so allocate the region now */
+ /* In user-mode we support only one ctx, so do the initial allocation now */
+#ifdef CONFIG_USER_ONLY
{
bool err = tcg_region_initial_alloc__locked(tcg_ctx);
g_assert(!err);
}
+#endif
+}
+
+/*
+ * All TCG threads except the parent (i.e. the one that called tcg_context_init
+ * and registered the target's TCG globals) must register with this function
+ * before initiating translation.
+ *
+ * In user-mode we just point tcg_ctx to tcg_init_ctx. See the documentation
+ * of tcg_region_init() for the reasoning behind this.
+ *
+ * In softmmu each caller registers its context in tcg_ctxs[]. Note that in
+ * softmmu tcg_ctxs[] does not track tcg_ctx_init, since the initial context
+ * is not used anymore for translation once this function is called.
+ *
+ * Not tracking tcg_init_ctx in tcg_ctxs[] in softmmu keeps code that iterates
+ * over the array (e.g. tcg_code_size() the same for both softmmu and user-mode.
+ */
+#ifdef CONFIG_USER_ONLY
+void tcg_register_thread(void)
+{
+ tcg_ctx = &tcg_init_ctx;
+}
+#else
+void tcg_register_thread(void)
+{
+ TCGContext *s = g_malloc(sizeof(*s));
+ unsigned int i, n;
+ bool err;
+
+ *s = tcg_init_ctx;
+
+ /* Relink mem_base. */
+ for (i = 0, n = tcg_init_ctx.nb_globals; i < n; ++i) {
+ if (tcg_init_ctx.temps[i].mem_base) {
+ ptrdiff_t b = tcg_init_ctx.temps[i].mem_base - tcg_init_ctx.temps;
+ tcg_debug_assert(b >= 0 && b < n);
+ s->temps[i].mem_base = &s->temps[b];
+ }
+ }
+
+ /* Claim an entry in tcg_ctxs */
+ n = atomic_fetch_inc(&n_tcg_ctxs);
+ g_assert(n < max_cpus);
+ atomic_set(&tcg_ctxs[n], s);
+
+ tcg_ctx = s;
+ qemu_mutex_lock(®ion.lock);
+ err = tcg_region_initial_alloc__locked(tcg_ctx);
+ g_assert(!err);
+ qemu_mutex_unlock(®ion.lock);
}
+#endif /* !CONFIG_USER_ONLY */
/*
* Returns the size (in bytes) of all translated code (i.e. from all regions)
@@ -439,13 +554,14 @@ void tcg_region_init(void)
*/
size_t tcg_code_size(void)
{
+ unsigned int n_ctxs = atomic_read(&n_tcg_ctxs);
unsigned int i;
size_t total;
qemu_mutex_lock(®ion.lock);
total = region.agg_size_full;
- for (i = 0; i < n_tcg_ctxs; i++) {
- const TCGContext *s = tcg_ctxs[i];
+ for (i = 0; i < n_ctxs; i++) {
+ const TCGContext *s = atomic_read(&tcg_ctxs[i]);
size_t size;
size = atomic_read(&s->code_gen_ptr) - s->code_gen_buffer;
@@ -601,8 +717,18 @@ void tcg_context_init(TCGContext *s)
}
tcg_ctx = s;
+ /*
+ * In user-mode we simply share the init context among threads, since we
+ * use a single region. See the documentation tcg_region_init() for the
+ * reasoning behind this.
+ * In softmmu we will have at most max_cpus TCG threads.
+ */
+#ifdef CONFIG_USER_ONLY
tcg_ctxs = &tcg_ctx;
n_tcg_ctxs = 1;
+#else
+ tcg_ctxs = g_new(TCGContext *, max_cpus);
+#endif
}
/*
@@ -2951,10 +3077,12 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op)
static inline
void tcg_profile_snapshot(TCGProfile *prof, bool counters, bool table)
{
+ unsigned int n_ctxs = atomic_read(&n_tcg_ctxs);
unsigned int i;
- for (i = 0; i < n_tcg_ctxs; i++) {
- const TCGProfile *orig = &tcg_ctxs[i]->prof;
+ for (i = 0; i < n_ctxs; i++) {
+ TCGContext *s = atomic_read(&tcg_ctxs[i]);
+ const TCGProfile *orig = &s->prof;
if (counters) {
PROF_ADD(prof, orig, tb_count1);
--
2.13.6
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [Qemu-devel] [PULL 50/51] tcg: Initialize cpu_env generically
2017-10-25 9:34 [Qemu-devel] [PULL 00/51] tcg queued patches Richard Henderson
` (48 preceding siblings ...)
2017-10-25 9:35 ` [Qemu-devel] [PULL 49/51] tcg: enable multiple TCG contexts in softmmu Richard Henderson
@ 2017-10-25 9:35 ` Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 51/51] translate-all: exit from tb_phys_invalidate if qht_remove fails Richard Henderson
` (3 subsequent siblings)
53 siblings, 0 replies; 59+ messages in thread
From: Richard Henderson @ 2017-10-25 9:35 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
This is identical for each target. So, move the initialization to
common code. Move the variable itself out of tcg_ctx and name it
cpu_env to minimize changes within targets.
This also means we can remove tcg_global_reg_new_{ptr,i32,i64},
since there are no longer global-register temps created by targets.
Reviewed-by: Emilio G. Cota <cota@braap.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/gen-icount.h | 10 ++++------
target/arm/translate.h | 1 -
tcg/tcg.h | 9 +--------
target/alpha/translate.c | 4 ----
target/arm/translate.c | 4 ----
target/cris/translate.c | 3 ---
target/cris/translate_v10.c | 2 --
target/hppa/translate.c | 4 ----
target/i386/translate.c | 3 ---
target/lm32/translate.c | 4 ----
target/m68k/translate.c | 5 -----
target/microblaze/translate.c | 4 ----
target/mips/translate.c | 4 ----
target/moxie/translate.c | 3 ---
target/nios2/translate.c | 4 ----
target/openrisc/translate.c | 3 ---
target/ppc/translate.c | 4 ----
target/s390x/translate.c | 6 ------
target/sh4/translate.c | 4 ----
target/sparc/translate.c | 4 ----
target/tilegx/translate.c | 3 ---
target/tricore/translate.c | 4 ----
target/unicore32/translate.c | 4 ----
target/xtensa/translate.c | 3 ---
tcg/tcg-op.c | 30 +++++++++++++++---------------
tcg/tcg.c | 32 ++++++++------------------------
26 files changed, 28 insertions(+), 133 deletions(-)
diff --git a/include/exec/gen-icount.h b/include/exec/gen-icount.h
index fe80176462..049bba86e9 100644
--- a/include/exec/gen-icount.h
+++ b/include/exec/gen-icount.h
@@ -18,7 +18,7 @@ static inline void gen_tb_start(TranslationBlock *tb)
count = tcg_temp_new_i32();
}
- tcg_gen_ld_i32(count, tcg_ctx->tcg_env,
+ tcg_gen_ld_i32(count, cpu_env,
-ENV_OFFSET + offsetof(CPUState, icount_decr.u32));
if (tb_cflags(tb) & CF_USE_ICOUNT) {
@@ -36,7 +36,7 @@ static inline void gen_tb_start(TranslationBlock *tb)
tcg_gen_brcondi_i32(TCG_COND_LT, count, 0, tcg_ctx->exitreq_label);
if (tb_cflags(tb) & CF_USE_ICOUNT) {
- tcg_gen_st16_i32(count, tcg_ctx->tcg_env,
+ tcg_gen_st16_i32(count, cpu_env,
-ENV_OFFSET + offsetof(CPUState, icount_decr.u16.low));
}
@@ -61,16 +61,14 @@ static inline void gen_tb_end(TranslationBlock *tb, int num_insns)
static inline void gen_io_start(void)
{
TCGv_i32 tmp = tcg_const_i32(1);
- tcg_gen_st_i32(tmp, tcg_ctx->tcg_env,
- -ENV_OFFSET + offsetof(CPUState, can_do_io));
+ tcg_gen_st_i32(tmp, cpu_env, -ENV_OFFSET + offsetof(CPUState, can_do_io));
tcg_temp_free_i32(tmp);
}
static inline void gen_io_end(void)
{
TCGv_i32 tmp = tcg_const_i32(0);
- tcg_gen_st_i32(tmp, tcg_ctx->tcg_env,
- -ENV_OFFSET + offsetof(CPUState, can_do_io));
+ tcg_gen_st_i32(tmp, cpu_env, -ENV_OFFSET + offsetof(CPUState, can_do_io));
tcg_temp_free_i32(tmp);
}
diff --git a/target/arm/translate.h b/target/arm/translate.h
index 3c96aec956..410ba79c0d 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -80,7 +80,6 @@ typedef struct DisasCompare {
} DisasCompare;
/* Share the TCG temporaries common between 32 and 64 bit modes. */
-extern TCGv_env cpu_env;
extern TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF;
extern TCGv_i64 cpu_exclusive_addr;
extern TCGv_i64 cpu_exclusive_val;
diff --git a/tcg/tcg.h b/tcg/tcg.h
index 3d022e448b..cb7b329876 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -669,7 +669,6 @@ struct TCGContext {
/* Track which vCPU triggers events */
CPUState *cpu; /* *_trans */
- TCGv_env tcg_env; /* *_exec */
/* These structures are private to tcg-target.inc.c. */
#ifdef TCG_TARGET_NEED_LDST_LABELS
@@ -696,6 +695,7 @@ struct TCGContext {
extern TCGContext tcg_init_ctx;
extern __thread TCGContext *tcg_ctx;
+extern TCGv_env cpu_env;
static inline size_t temp_idx(TCGTemp *ts)
{
@@ -839,9 +839,6 @@ void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size);
TCGTemp *tcg_global_mem_new_internal(TCGType, TCGv_ptr,
intptr_t, const char *);
-TCGv_i32 tcg_global_reg_new_i32(TCGReg reg, const char *name);
-TCGv_i64 tcg_global_reg_new_i64(TCGReg reg, const char *name);
-
TCGv_i32 tcg_temp_new_internal_i32(int temp_local);
TCGv_i64 tcg_temp_new_internal_i64(int temp_local);
@@ -960,8 +957,6 @@ static inline TCGv_ptr TCGV_NAT_TO_PTR(TCGv_i32 n) { return (TCGv_ptr)n; }
static inline TCGv_i32 TCGV_PTR_TO_NAT(TCGv_ptr n) { return (TCGv_i32)n; }
#define tcg_const_ptr(V) TCGV_NAT_TO_PTR(tcg_const_i32((intptr_t)(V)))
-#define tcg_global_reg_new_ptr(R, N) \
- TCGV_NAT_TO_PTR(tcg_global_reg_new_i32((R), (N)))
#define tcg_global_mem_new_ptr(R, O, N) \
TCGV_NAT_TO_PTR(tcg_global_mem_new_i32((R), (O), (N)))
#define tcg_temp_new_ptr() TCGV_NAT_TO_PTR(tcg_temp_new_i32())
@@ -971,8 +966,6 @@ static inline TCGv_ptr TCGV_NAT_TO_PTR(TCGv_i64 n) { return (TCGv_ptr)n; }
static inline TCGv_i64 TCGV_PTR_TO_NAT(TCGv_ptr n) { return (TCGv_i64)n; }
#define tcg_const_ptr(V) TCGV_NAT_TO_PTR(tcg_const_i64((intptr_t)(V)))
-#define tcg_global_reg_new_ptr(R, N) \
- TCGV_NAT_TO_PTR(tcg_global_reg_new_i64((R), (N)))
#define tcg_global_mem_new_ptr(R, O, N) \
TCGV_NAT_TO_PTR(tcg_global_mem_new_i64((R), (O), (N)))
#define tcg_temp_new_ptr() TCGV_NAT_TO_PTR(tcg_temp_new_i64())
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
index f6247bf38d..cfd63d5c1f 100644
--- a/target/alpha/translate.c
+++ b/target/alpha/translate.c
@@ -78,7 +78,6 @@ struct DisasContext {
#define DISAS_PC_STALE DISAS_TARGET_2
/* global register indexes */
-static TCGv_env cpu_env;
static TCGv cpu_std_ir[31];
static TCGv cpu_fir[31];
static TCGv cpu_pc;
@@ -126,9 +125,6 @@ void alpha_translate_init(void)
int i;
- cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
- tcg_ctx->tcg_env = cpu_env;
-
for (i = 0; i < 31; i++) {
cpu_std_ir[i] = tcg_global_mem_new_i64(cpu_env,
offsetof(CPUAlphaState, ir[i]),
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 7873c03ae8..a252429e68 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -58,7 +58,6 @@
#define IS_USER(s) (s->user)
#endif
-TCGv_env cpu_env;
/* We reuse the same 64-bit temporaries for efficiency. */
static TCGv_i64 cpu_V0, cpu_V1, cpu_M0;
static TCGv_i32 cpu_R[16];
@@ -81,9 +80,6 @@ void arm_translate_init(void)
{
int i;
- cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
- tcg_ctx->tcg_env = cpu_env;
-
for (i = 0; i < 16; i++) {
cpu_R[i] = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUARMState, regs[i]),
diff --git a/target/cris/translate.c b/target/cris/translate.c
index 6687b838d5..aa95f6701a 100644
--- a/target/cris/translate.c
+++ b/target/cris/translate.c
@@ -66,7 +66,6 @@
#define CC_MASK_NZVC 0xf
#define CC_MASK_RNZV 0x10e
-static TCGv_env cpu_env;
static TCGv cpu_R[16];
static TCGv cpu_PR[16];
static TCGv cc_x;
@@ -3368,8 +3367,6 @@ void cris_initialize_tcg(void)
{
int i;
- cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
- tcg_ctx->tcg_env = cpu_env;
cc_x = tcg_global_mem_new(cpu_env,
offsetof(CPUCRISState, cc_x), "cc_x");
cc_src = tcg_global_mem_new(cpu_env,
diff --git a/target/cris/translate_v10.c b/target/cris/translate_v10.c
index 5d489203f4..fce78825cc 100644
--- a/target/cris/translate_v10.c
+++ b/target/cris/translate_v10.c
@@ -1272,8 +1272,6 @@ void cris_initialize_crisv10_tcg(void)
{
int i;
- cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
- tcg_ctx->tcg_env = cpu_env;
cc_x = tcg_global_mem_new(cpu_env,
offsetof(CPUCRISState, cc_x), "cc_x");
cc_src = tcg_global_mem_new(cpu_env,
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 9059812d4e..dbd4cd8615 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -83,7 +83,6 @@ typedef struct DisasInsn {
} DisasInsn;
/* global register indexes */
-static TCGv_env cpu_env;
static TCGv cpu_gr[32];
static TCGv cpu_iaoq_f;
static TCGv cpu_iaoq_b;
@@ -126,9 +125,6 @@ void hppa_translate_init(void)
int i;
- cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
- tcg_ctx->tcg_env = cpu_env;
-
TCGV_UNUSED(cpu_gr[0]);
for (i = 1; i < 32; i++) {
cpu_gr[i] = tcg_global_mem_new(cpu_env,
diff --git a/target/i386/translate.c b/target/i386/translate.c
index 649004393d..7df9233ded 100644
--- a/target/i386/translate.c
+++ b/target/i386/translate.c
@@ -72,7 +72,6 @@
//#define MACRO_TEST 1
/* global register indexes */
-static TCGv_env cpu_env;
static TCGv cpu_A0;
static TCGv cpu_cc_dst, cpu_cc_src, cpu_cc_src2, cpu_cc_srcT;
static TCGv_i32 cpu_cc_op;
@@ -8367,8 +8366,6 @@ void tcg_x86_init(void)
};
int i;
- cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
- tcg_ctx->tcg_env = cpu_env;
cpu_cc_op = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUX86State, cc_op), "cc_op");
cpu_cc_dst = tcg_global_mem_new(cpu_env, offsetof(CPUX86State, cc_dst),
diff --git a/target/lm32/translate.c b/target/lm32/translate.c
index 6707967a2c..02ad3edad3 100644
--- a/target/lm32/translate.c
+++ b/target/lm32/translate.c
@@ -53,7 +53,6 @@
#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */
#define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */
-static TCGv_env cpu_env;
static TCGv cpu_R[32];
static TCGv cpu_pc;
static TCGv cpu_ie;
@@ -1208,9 +1207,6 @@ void lm32_translate_init(void)
{
int i;
- cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
- tcg_ctx->tcg_env = cpu_env;
-
for (i = 0; i < ARRAY_SIZE(cpu_R); i++) {
cpu_R[i] = tcg_global_mem_new(cpu_env,
offsetof(CPULM32State, regs[i]),
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index f6e902f2b6..e7eaf03e55 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -44,8 +44,6 @@
static TCGv_i32 cpu_halted;
static TCGv_i32 cpu_exception_index;
-static TCGv_env cpu_env;
-
static char cpu_reg_names[2 * 8 * 3 + 5 * 4];
static TCGv cpu_dregs[8];
static TCGv cpu_aregs[8];
@@ -69,9 +67,6 @@ void m68k_tcg_init(void)
char *p;
int i;
- cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
- tcg_ctx->tcg_env = cpu_env;
-
#define DEFO32(name, offset) \
QREG_##name = tcg_global_mem_new_i32(cpu_env, \
offsetof(CPUM68KState, offset), #name);
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 22f8d6230b..e51821d6bd 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -53,7 +53,6 @@
#define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */
static TCGv env_debug;
-static TCGv_env cpu_env;
static TCGv cpu_R[32];
static TCGv cpu_SR[18];
static TCGv env_imm;
@@ -1855,9 +1854,6 @@ void mb_tcg_init(void)
{
int i;
- cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
- tcg_ctx->tcg_env = cpu_env;
-
env_debug = tcg_global_mem_new(cpu_env,
offsetof(CPUMBState, debug),
"debug0");
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 7dfa94ab26..82622c550e 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1376,7 +1376,6 @@ enum {
};
/* global register indices */
-static TCGv_env cpu_env;
static TCGv cpu_gpr[32], cpu_PC;
static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC];
static TCGv cpu_dspctrl, btarget, bcond;
@@ -20454,9 +20453,6 @@ void mips_tcg_init(void)
{
int i;
- cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
- tcg_ctx->tcg_env = cpu_env;
-
TCGV_UNUSED(cpu_gpr[0]);
for (i = 1; i < 32; i++)
cpu_gpr[i] = tcg_global_mem_new(cpu_env,
diff --git a/target/moxie/translate.c b/target/moxie/translate.c
index 59c70b5cef..28b405f0e4 100644
--- a/target/moxie/translate.c
+++ b/target/moxie/translate.c
@@ -56,7 +56,6 @@ enum {
static TCGv cpu_pc;
static TCGv cpu_gregs[16];
-static TCGv_env cpu_env;
static TCGv cc_a, cc_b;
#include "exec/gen-icount.h"
@@ -101,8 +100,6 @@ void moxie_translate_init(void)
"$r10", "$r11", "$r12", "$r13"
};
- cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
- tcg_ctx->tcg_env = cpu_env;
cpu_pc = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUMoxieState, pc), "$pc");
for (i = 0; i < 16; i++)
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
index b91fd206fb..b5aaf56e86 100644
--- a/target/nios2/translate.c
+++ b/target/nios2/translate.c
@@ -789,7 +789,6 @@ static const char * const regnames[] = {
"rpc"
};
-static TCGv_ptr cpu_env;
static TCGv cpu_R[NUM_CORE_REGS];
#include "exec/gen-icount.h"
@@ -947,9 +946,6 @@ void nios2_tcg_init(void)
{
int i;
- cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
- tcg_ctx->tcg_env = cpu_env;
-
for (i = 0; i < NUM_CORE_REGS; i++) {
cpu_R[i] = tcg_global_mem_new(cpu_env,
offsetof(CPUNios2State, regs[i]),
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index b031f2db97..c9cbd2319f 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -53,7 +53,6 @@ typedef struct DisasContext {
bool singlestep_enabled;
} DisasContext;
-static TCGv_env cpu_env;
static TCGv cpu_sr;
static TCGv cpu_R[32];
static TCGv cpu_R0;
@@ -80,8 +79,6 @@ void openrisc_translate_init(void)
};
int i;
- cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
- tcg_ctx->tcg_env = cpu_env;
cpu_sr = tcg_global_mem_new(cpu_env,
offsetof(CPUOpenRISCState, sr), "sr");
cpu_dflag = tcg_global_mem_new_i32(cpu_env,
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 0ad84a75e4..e7e4983cbf 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -51,7 +51,6 @@
/* Code translation helpers */
/* global register indexes */
-static TCGv_env cpu_env;
static char cpu_reg_names[10*3 + 22*4 /* GPR */
+ 10*4 + 22*5 /* SPE GPRh */
+ 10*4 + 22*5 /* FPR */
@@ -85,9 +84,6 @@ void ppc_translate_init(void)
char* p;
size_t cpu_reg_names_size;
- cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
- tcg_ctx->tcg_env = cpu_env;
-
p = cpu_reg_names;
cpu_reg_names_size = sizeof(cpu_reg_names);
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index 2bf6f48089..55db8f3446 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -37,10 +37,6 @@
#include "qemu/log.h"
#include "qemu/host-utils.h"
#include "exec/cpu_ldst.h"
-
-/* global register indexes */
-static TCGv_env cpu_env;
-
#include "exec/gen-icount.h"
#include "exec/helper-proto.h"
#include "exec/helper-gen.h"
@@ -112,8 +108,6 @@ void s390x_translate_init(void)
{
int i;
- cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
- tcg_ctx->tcg_env = cpu_env;
psw_addr = tcg_global_mem_new_i64(cpu_env,
offsetof(CPUS390XState, psw.addr),
"psw_addr");
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index c13be851ba..c98f8d31e3 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -65,7 +65,6 @@ enum {
};
/* global register indexes */
-static TCGv_env cpu_env;
static TCGv cpu_gregs[32];
static TCGv cpu_sr, cpu_sr_m, cpu_sr_q, cpu_sr_t;
static TCGv cpu_pc, cpu_ssr, cpu_spc, cpu_gbr;
@@ -99,9 +98,6 @@ void sh4_translate_init(void)
"FPR12_BANK1", "FPR13_BANK1", "FPR14_BANK1", "FPR15_BANK1",
};
- cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
- tcg_ctx->tcg_env = cpu_env;
-
for (i = 0; i < 24; i++) {
cpu_gregs[i] = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUSH4State, gregs[i]),
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index afef77976b..d5e866fe0d 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -41,7 +41,6 @@
according to jump_pc[T2] */
/* global register indexes */
-static TCGv_env cpu_env;
static TCGv_ptr cpu_regwptr;
static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
static TCGv_i32 cpu_cc_op;
@@ -5911,9 +5910,6 @@ void sparc_tcg_init(void)
unsigned int i;
- cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
- tcg_ctx->tcg_env = cpu_env;
-
cpu_regwptr = tcg_global_mem_new_ptr(cpu_env,
offsetof(CPUSPARCState, regwptr),
"regwptr");
diff --git a/target/tilegx/translate.c b/target/tilegx/translate.c
index a744c38bb7..d55549dabc 100644
--- a/target/tilegx/translate.c
+++ b/target/tilegx/translate.c
@@ -33,7 +33,6 @@
#define FMT64X "%016" PRIx64
-static TCGv_env cpu_env;
static TCGv cpu_pc;
static TCGv cpu_regs[TILEGX_R_COUNT];
@@ -2445,8 +2444,6 @@ void tilegx_tcg_init(void)
{
int i;
- cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
- tcg_ctx->tcg_env = cpu_env;
cpu_pc = tcg_global_mem_new_i64(cpu_env, offsetof(CPUTLGState, pc), "pc");
for (i = 0; i < TILEGX_R_COUNT; i++) {
cpu_regs[i] = tcg_global_mem_new_i64(cpu_env,
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 590cbbee8b..18102e54cb 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -47,8 +47,6 @@ static TCGv cpu_PSW_V;
static TCGv cpu_PSW_SV;
static TCGv cpu_PSW_AV;
static TCGv cpu_PSW_SAV;
-/* CPU env */
-static TCGv_env cpu_env;
#include "exec/gen-icount.h"
@@ -8881,8 +8879,6 @@ void tricore_tcg_init(void)
{
int i;
- cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
- tcg_ctx->tcg_env = cpu_env;
/* reg init */
for (i = 0 ; i < 16 ; i++) {
cpu_gpr_a[i] = tcg_global_mem_new(cpu_env,
diff --git a/target/unicore32/translate.c b/target/unicore32/translate.c
index 070653e2d1..de2a7ceee7 100644
--- a/target/unicore32/translate.c
+++ b/target/unicore32/translate.c
@@ -54,7 +54,6 @@ typedef struct DisasContext {
conditional executions state has been updated. */
#define DISAS_SYSCALL DISAS_TARGET_3
-static TCGv_env cpu_env;
static TCGv_i32 cpu_R[32];
/* FIXME: These should be removed. */
@@ -74,9 +73,6 @@ void uc32_translate_init(void)
{
int i;
- cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
- tcg_ctx->tcg_env = cpu_env;
-
for (i = 0; i < 32; i++) {
cpu_R[i] = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUUniCore32State, regs[i]), regnames[i]);
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index ab96b77d88..32c4159949 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -77,7 +77,6 @@ typedef struct DisasContext {
unsigned cpenable;
} DisasContext;
-static TCGv_env cpu_env;
static TCGv_i32 cpu_pc;
static TCGv_i32 cpu_R[16];
static TCGv_i32 cpu_FR[16];
@@ -221,8 +220,6 @@ void xtensa_translate_init(void)
};
int i;
- cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
- tcg_ctx->tcg_env = cpu_env;
cpu_pc = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUXtensaState, pc), "pc");
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index ba603281d3..3cad30b1f2 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -2562,7 +2562,7 @@ void tcg_gen_lookup_and_goto_ptr(void)
{
if (TCG_TARGET_HAS_goto_ptr && !qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)) {
TCGv_ptr ptr = tcg_temp_new_ptr();
- gen_helper_lookup_tb_ptr(ptr, tcg_ctx->tcg_env);
+ gen_helper_lookup_tb_ptr(ptr, cpu_env);
tcg_gen_op1i(INDEX_op_goto_ptr, tcgv_ptr_arg(ptr));
tcg_temp_free_ptr(ptr);
} else {
@@ -2648,7 +2648,7 @@ void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop)
{
tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD);
memop = tcg_canonicalize_memop(memop, 0, 0);
- trace_guest_mem_before_tcg(tcg_ctx->cpu, tcg_ctx->tcg_env,
+ trace_guest_mem_before_tcg(tcg_ctx->cpu, cpu_env,
addr, trace_mem_get_info(memop, 0));
gen_ldst_i32(INDEX_op_qemu_ld_i32, val, addr, memop, idx);
}
@@ -2657,7 +2657,7 @@ void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop)
{
tcg_gen_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST);
memop = tcg_canonicalize_memop(memop, 0, 1);
- trace_guest_mem_before_tcg(tcg_ctx->cpu, tcg_ctx->tcg_env,
+ trace_guest_mem_before_tcg(tcg_ctx->cpu, cpu_env,
addr, trace_mem_get_info(memop, 1));
gen_ldst_i32(INDEX_op_qemu_st_i32, val, addr, memop, idx);
}
@@ -2676,7 +2676,7 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop)
}
memop = tcg_canonicalize_memop(memop, 1, 0);
- trace_guest_mem_before_tcg(tcg_ctx->cpu, tcg_ctx->tcg_env,
+ trace_guest_mem_before_tcg(tcg_ctx->cpu, cpu_env,
addr, trace_mem_get_info(memop, 0));
gen_ldst_i64(INDEX_op_qemu_ld_i64, val, addr, memop, idx);
}
@@ -2690,7 +2690,7 @@ void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop)
}
memop = tcg_canonicalize_memop(memop, 1, 1);
- trace_guest_mem_before_tcg(tcg_ctx->cpu, tcg_ctx->tcg_env,
+ trace_guest_mem_before_tcg(tcg_ctx->cpu, cpu_env,
addr, trace_mem_get_info(memop, 1));
gen_ldst_i64(INDEX_op_qemu_st_i64, val, addr, memop, idx);
}
@@ -2806,11 +2806,11 @@ void tcg_gen_atomic_cmpxchg_i32(TCGv_i32 retv, TCGv addr, TCGv_i32 cmpv,
#ifdef CONFIG_SOFTMMU
{
TCGv_i32 oi = tcg_const_i32(make_memop_idx(memop & ~MO_SIGN, idx));
- gen(retv, tcg_ctx->tcg_env, addr, cmpv, newv, oi);
+ gen(retv, cpu_env, addr, cmpv, newv, oi);
tcg_temp_free_i32(oi);
}
#else
- gen(retv, tcg_ctx->tcg_env, addr, cmpv, newv);
+ gen(retv, cpu_env, addr, cmpv, newv);
#endif
if (memop & MO_SIGN) {
@@ -2851,14 +2851,14 @@ void tcg_gen_atomic_cmpxchg_i64(TCGv_i64 retv, TCGv addr, TCGv_i64 cmpv,
#ifdef CONFIG_SOFTMMU
{
TCGv_i32 oi = tcg_const_i32(make_memop_idx(memop, idx));
- gen(retv, tcg_ctx->tcg_env, addr, cmpv, newv, oi);
+ gen(retv, cpu_env, addr, cmpv, newv, oi);
tcg_temp_free_i32(oi);
}
#else
- gen(retv, tcg_ctx->tcg_env, addr, cmpv, newv);
+ gen(retv, cpu_env, addr, cmpv, newv);
#endif
#else
- gen_helper_exit_atomic(tcg_ctx->tcg_env);
+ gen_helper_exit_atomic(cpu_env);
/* Produce a result, so that we have a well-formed opcode stream
with respect to uses of the result in the (dead) code following. */
tcg_gen_movi_i64(retv, 0);
@@ -2914,11 +2914,11 @@ static void do_atomic_op_i32(TCGv_i32 ret, TCGv addr, TCGv_i32 val,
#ifdef CONFIG_SOFTMMU
{
TCGv_i32 oi = tcg_const_i32(make_memop_idx(memop & ~MO_SIGN, idx));
- gen(ret, tcg_ctx->tcg_env, addr, val, oi);
+ gen(ret, cpu_env, addr, val, oi);
tcg_temp_free_i32(oi);
}
#else
- gen(ret, tcg_ctx->tcg_env, addr, val);
+ gen(ret, cpu_env, addr, val);
#endif
if (memop & MO_SIGN) {
@@ -2959,14 +2959,14 @@ static void do_atomic_op_i64(TCGv_i64 ret, TCGv addr, TCGv_i64 val,
#ifdef CONFIG_SOFTMMU
{
TCGv_i32 oi = tcg_const_i32(make_memop_idx(memop & ~MO_SIGN, idx));
- gen(ret, tcg_ctx->tcg_env, addr, val, oi);
+ gen(ret, cpu_env, addr, val, oi);
tcg_temp_free_i32(oi);
}
#else
- gen(ret, tcg_ctx->tcg_env, addr, val);
+ gen(ret, cpu_env, addr, val);
#endif
#else
- gen_helper_exit_atomic(tcg_ctx->tcg_env);
+ gen_helper_exit_atomic(cpu_env);
/* Produce a result, so that we have a well-formed opcode stream
with respect to uses of the result in the (dead) code following. */
tcg_gen_movi_i64(ret, 0);
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 5574317736..683ff4abb7 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -121,6 +121,7 @@ static bool tcg_out_ldst_finalize(TCGContext *s);
static TCGContext **tcg_ctxs;
static unsigned int n_tcg_ctxs;
+TCGv_env cpu_env = 0;
/*
* We divide code_gen_buffer into equally-sized "regions" that TCG threads
@@ -657,6 +658,8 @@ static GHashTable *helper_table;
static int indirect_reg_alloc_order[ARRAY_SIZE(tcg_target_reg_alloc_order)];
static void process_op_defs(TCGContext *s);
+static TCGTemp *tcg_global_reg_new_internal(TCGContext *s, TCGType type,
+ TCGReg reg, const char *name);
void tcg_context_init(TCGContext *s)
{
@@ -664,6 +667,7 @@ void tcg_context_init(TCGContext *s)
TCGOpDef *def;
TCGArgConstraint *args_ct;
int *sorted_args;
+ TCGTemp *ts;
memset(s, 0, sizeof(*s));
s->nb_globals = 0;
@@ -729,6 +733,10 @@ void tcg_context_init(TCGContext *s)
#else
tcg_ctxs = g_new(TCGContext *, max_cpus);
#endif
+
+ tcg_debug_assert(!tcg_regset_test_reg(s->reserved_regs, TCG_AREG0));
+ ts = tcg_global_reg_new_internal(s, TCG_TYPE_PTR, TCG_AREG0, "env");
+ cpu_env = temp_tcgv_ptr(ts);
}
/*
@@ -871,30 +879,6 @@ void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size)
= tcg_global_reg_new_internal(s, TCG_TYPE_PTR, reg, "_frame");
}
-TCGv_i32 tcg_global_reg_new_i32(TCGReg reg, const char *name)
-{
- TCGContext *s = tcg_ctx;
- TCGTemp *t;
-
- if (tcg_regset_test_reg(s->reserved_regs, reg)) {
- tcg_abort();
- }
- t = tcg_global_reg_new_internal(s, TCG_TYPE_I32, reg, name);
- return temp_tcgv_i32(t);
-}
-
-TCGv_i64 tcg_global_reg_new_i64(TCGReg reg, const char *name)
-{
- TCGContext *s = tcg_ctx;
- TCGTemp *t;
-
- if (tcg_regset_test_reg(s->reserved_regs, reg)) {
- tcg_abort();
- }
- t = tcg_global_reg_new_internal(s, TCG_TYPE_I64, reg, name);
- return temp_tcgv_i64(t);
-}
-
TCGTemp *tcg_global_mem_new_internal(TCGType type, TCGv_ptr base,
intptr_t offset, const char *name)
{
--
2.13.6
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [Qemu-devel] [PULL 51/51] translate-all: exit from tb_phys_invalidate if qht_remove fails
2017-10-25 9:34 [Qemu-devel] [PULL 00/51] tcg queued patches Richard Henderson
` (49 preceding siblings ...)
2017-10-25 9:35 ` [Qemu-devel] [PULL 50/51] tcg: Initialize cpu_env generically Richard Henderson
@ 2017-10-25 9:35 ` Richard Henderson
2017-10-25 10:33 ` [Qemu-devel] [PULL 00/51] tcg queued patches no-reply
` (2 subsequent siblings)
53 siblings, 0 replies; 59+ messages in thread
From: Richard Henderson @ 2017-10-25 9:35 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Emilio G. Cota
From: "Emilio G. Cota" <cota@braap.org>
Two or more threads might race while invalidating the same TB. We currently
do not check for this at all despite taking tb_lock, which means we would
wrongly invalidate the same TB more than once. This bug has actually been
hit by users: I recently saw a report on IRC, although I have yet to see
the corresponding test case.
Fix this by using qht_remove as the synchronization point; if it fails,
that means the TB has already been invalidated, and therefore there
is nothing left to do in tb_phys_invalidate.
Note that this solution works now that we still have tb_lock, and will
continue working once we remove tb_lock.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Emilio G. Cota <cota@braap.org>
Message-Id: <1508445114-4717-1-git-send-email-cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/translate-all.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index 5724149289..34c5e28d07 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -1079,7 +1079,9 @@ void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr)
phys_pc = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK);
h = tb_hash_func(phys_pc, tb->pc, tb->flags, tb->cflags & CF_HASH_MASK,
tb->trace_vcpu_dstate);
- qht_remove(&tb_ctx.htable, tb, h);
+ if (!qht_remove(&tb_ctx.htable, tb, h)) {
+ return;
+ }
/* remove the TB from the page list */
if (tb->page_addr[0] != page_addr) {
--
2.13.6
^ permalink raw reply related [flat|nested] 59+ messages in thread
* Re: [Qemu-devel] [PULL 00/51] tcg queued patches
2017-10-25 9:34 [Qemu-devel] [PULL 00/51] tcg queued patches Richard Henderson
` (50 preceding siblings ...)
2017-10-25 9:35 ` [Qemu-devel] [PULL 51/51] translate-all: exit from tb_phys_invalidate if qht_remove fails Richard Henderson
@ 2017-10-25 10:33 ` no-reply
2017-10-25 19:03 ` Peter Maydell
2017-11-01 17:34 ` Thomas Huth
53 siblings, 0 replies; 59+ messages in thread
From: no-reply @ 2017-10-25 10:33 UTC (permalink / raw)
To: richard.henderson; +Cc: famz, qemu-devel, peter.maydell
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PULL 00/51] tcg queued patches
Type: series
Message-id: 20171025093535.10175-1-richard.henderson@linaro.org
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0
git config --local diff.renamelimit 0
git config --local diff.renames True
commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
failed=1
echo
fi
n=$((n+1))
done
exit $failed
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
* [new tag] patchew/20171025093535.10175-1-richard.henderson@linaro.org -> patchew/20171025093535.10175-1-richard.henderson@linaro.org
Switched to a new branch 'test'
77626a041c translate-all: exit from tb_phys_invalidate if qht_remove fails
4a90f4ebe9 tcg: Initialize cpu_env generically
2152c41bd3 tcg: enable multiple TCG contexts in softmmu
58ccac2561 tcg: introduce regions to split code_gen_buffer
9127fe5b64 translate-all: use qemu_protect_rwx/none helpers
86abfd9e92 osdep: introduce qemu_mprotect_rwx/none
b98ae7360f tcg: allocate optimizer temps with tcg_malloc
356db0bab8 tcg: distribute profiling counters across TCGContext's
8b52922c45 tcg: introduce **tcg_ctxs to keep track of all TCGContext's
1f81eecd3a gen-icount: fold exitreq_label into TCGContext
59e4a38c26 tcg: define tcg_init_ctx and make tcg_ctx a pointer
3103c47aaf tcg: take tb_ctx out of TCGContext
0bf9f60518 translate-all: report correct avg host TB size
3c88306ec2 exec-all: rename tb_free to tb_remove
42857d44ba translate-all: use a binary search tree to track TBs in TBContext
65eedf9e8d tcg: Remove CF_IGNORE_ICOUNT
d4c9947316 tcg: Add CF_LAST_IO + CF_USE_ICOUNT to CF_HASH_MASK
f823bdd39d cpu-exec: lookup/generate TB outside exclusive region during step_atomic
10287570c7 tcg: check CF_PARALLEL instead of parallel_cpus
0e5ad6e79e target/sparc: check CF_PARALLEL instead of parallel_cpus
56024229c8 target/sh4: check CF_PARALLEL instead of parallel_cpus
1de3863b5b target/s390x: check CF_PARALLEL instead of parallel_cpus
40235bc3c1 target/m68k: check CF_PARALLEL instead of parallel_cpus
07ae79e853 target/i386: check CF_PARALLEL instead of parallel_cpus
af968dcdfa target/hppa: check CF_PARALLEL instead of parallel_cpus
8ae9c37655 target/arm: check CF_PARALLEL instead of parallel_cpus
c6903f61b8 tcg: convert tb->cflags reads to tb_cflags(tb)
857e9bace7 tcg: Include CF_COUNT_MASK in CF_HASH_MASK
664c0a988f tcg: Add CPUState cflags_next_tb
d00a1708d4 tcg: define CF_PARALLEL and use it for TB hashing along with CF_COUNT_MASK
ab6636facc tcg: Use offsets not indices for TCGv_*
158a9ef727 qom: Introduce CPUClass.tcg_initialize
2c3836bc80 tcg: Remove TCGV_EQUAL*
37ba8ce8e9 tcg: Remove GET_TCGV_* and MAKE_TCGV_*
ac1bcac6c9 tcg: Introduce temp_tcgv_{i32,i64,ptr}
7a2668fa18 tcg: Introduce tcgv_{i32, i64, ptr}_{arg, temp}
50712fd38b tcg: Push tcg_ctx into tcg_gen_callN
9e01153d05 tcg: Push tcg_ctx into generator functions
8496a5236b tcg: Use per-temp state data in optimize
818b8ab51f tcg: Remove unused TCG_CALL_DUMMY_TCGV
72bbb04702 tcg: Change temp_allocate_frame arg to TCGTemp
7d35604262 tcg: Avoid loops against variable bounds
fa2959c5ca tcg: Use per-temp state data in liveness
988d1b1378 tcg: Introduce temp_arg, export temp_idx
d275e8c996 tcg: Return NULL temp for TCG_CALL_DUMMY_ARG
9a6fd94cb4 tcg: Add temp_global bit to TCGTemp
21db94e37e tcg: Introduce arg_temp
a1d9d381b7 tcg: Propagate TCGOp down to allocators
37e9e9eb62 tcg: Propagate args to op->args in tcg.c
a34134aa11 tcg: Propagate args to op->args in optimizer
c912ac427e tcg: Merge opcode arguments into TCGOp
=== OUTPUT BEGIN ===
Checking PATCH 1/51: tcg: Merge opcode arguments into TCGOp...
ERROR: spaces prohibited around that ':' (ctx:WxW)
#482: FILE: tcg/tcg.h:613:
+ unsigned calli : 4; /* 12 */
^
ERROR: spaces prohibited around that ':' (ctx:WxW)
#483: FILE: tcg/tcg.h:614:
+ unsigned callo : 2; /* 14 */
^
ERROR: space prohibited before that ':' (ctx:WxW)
#484: FILE: tcg/tcg.h:615:
+ unsigned : 2; /* 16 */
^
ERROR: spaces prohibited around that ':' (ctx:WxW)
#489: FILE: tcg/tcg.h:618:
+ unsigned prev : 16; /* 32 */
^
ERROR: spaces prohibited around that ':' (ctx:WxW)
#490: FILE: tcg/tcg.h:619:
+ unsigned next : 16; /* 48 */
^
total: 5 errors, 0 warnings, 485 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 2/51: tcg: Propagate args to op->args in optimizer...
ERROR: spaces required around that '-' (ctx:VxV)
#649: FILE: tcg/optimize.c:1165:
+ tcg_opt_gen_mov(s, op, op->args[0], op->args[4-tmp]);
^
total: 1 errors, 0 warnings, 912 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 3/51: tcg: Propagate args to op->args in tcg.c...
Checking PATCH 4/51: tcg: Propagate TCGOp down to allocators...
Checking PATCH 5/51: tcg: Introduce arg_temp...
Checking PATCH 6/51: tcg: Add temp_global bit to TCGTemp...
Checking PATCH 7/51: tcg: Return NULL temp for TCG_CALL_DUMMY_ARG...
Checking PATCH 8/51: tcg: Introduce temp_arg, export temp_idx...
Checking PATCH 9/51: tcg: Use per-temp state data in liveness...
WARNING: line over 80 characters
#187: FILE: tcg/tcg.c:1808:
+ } else if (arg_temp(op->args[0])->state == TS_DEAD && have_opc_new2) {
total: 0 errors, 1 warnings, 441 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 10/51: tcg: Avoid loops against variable bounds...
Checking PATCH 11/51: tcg: Change temp_allocate_frame arg to TCGTemp...
Checking PATCH 12/51: tcg: Remove unused TCG_CALL_DUMMY_TCGV...
Checking PATCH 13/51: tcg: Use per-temp state data in optimize...
Checking PATCH 14/51: tcg: Push tcg_ctx into generator functions...
Checking PATCH 15/51: tcg: Push tcg_ctx into tcg_gen_callN...
Checking PATCH 16/51: tcg: Introduce tcgv_{i32, i64, ptr}_{arg, temp}...
Checking PATCH 17/51: tcg: Introduce temp_tcgv_{i32,i64,ptr}...
Checking PATCH 18/51: tcg: Remove GET_TCGV_* and MAKE_TCGV_*...
Checking PATCH 19/51: tcg: Remove TCGV_EQUAL*...
Checking PATCH 20/51: qom: Introduce CPUClass.tcg_initialize...
Checking PATCH 21/51: tcg: Use offsets not indices for TCGv_*...
Checking PATCH 22/51: tcg: define CF_PARALLEL and use it for TB hashing along with CF_COUNT_MASK...
Checking PATCH 23/51: tcg: Add CPUState cflags_next_tb...
Checking PATCH 24/51: tcg: Include CF_COUNT_MASK in CF_HASH_MASK...
Checking PATCH 25/51: tcg: convert tb->cflags reads to tb_cflags(tb)...
ERROR: return is not a function, parentheses are not required
#103: FILE: target/alpha/translate.c:458:
+ return ((tb_cflags(ctx->base.tb) & CF_LAST_IO)
WARNING: line over 80 characters
#219: FILE: target/hppa/translate.c:472:
+ if ((tb_cflags(ctx->base.tb) & CF_LAST_IO) || ctx->base.singlestep_enabled) {
total: 1 errors, 1 warnings, 924 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 26/51: target/arm: check CF_PARALLEL instead of parallel_cpus...
Checking PATCH 27/51: target/hppa: check CF_PARALLEL instead of parallel_cpus...
Checking PATCH 28/51: target/i386: check CF_PARALLEL instead of parallel_cpus...
WARNING: line over 80 characters
#23: FILE: target/i386/translate.c:5310:
+ if ((s->prefix & PREFIX_LOCK) && (tb_cflags(s->base.tb) & CF_PARALLEL)) {
WARNING: line over 80 characters
#32: FILE: target/i386/translate.c:5321:
+ if ((s->prefix & PREFIX_LOCK) && (tb_cflags(s->base.tb) & CF_PARALLEL)) {
total: 0 errors, 2 warnings, 16 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 29/51: target/m68k: check CF_PARALLEL instead of parallel_cpus...
Checking PATCH 30/51: target/s390x: check CF_PARALLEL instead of parallel_cpus...
Checking PATCH 31/51: target/sh4: check CF_PARALLEL instead of parallel_cpus...
Checking PATCH 32/51: target/sparc: check CF_PARALLEL instead of parallel_cpus...
Checking PATCH 33/51: tcg: check CF_PARALLEL instead of parallel_cpus...
Checking PATCH 34/51: cpu-exec: lookup/generate TB outside exclusive region during step_atomic...
Checking PATCH 35/51: tcg: Add CF_LAST_IO + CF_USE_ICOUNT to CF_HASH_MASK...
Checking PATCH 36/51: tcg: Remove CF_IGNORE_ICOUNT...
Checking PATCH 37/51: translate-all: use a binary search tree to track TBs in TBContext...
Checking PATCH 38/51: exec-all: rename tb_free to tb_remove...
Checking PATCH 39/51: translate-all: report correct avg host TB size...
Checking PATCH 40/51: tcg: take tb_ctx out of TCGContext...
Checking PATCH 41/51: tcg: define tcg_init_ctx and make tcg_ctx a pointer...
Checking PATCH 42/51: gen-icount: fold exitreq_label into TCGContext...
Checking PATCH 43/51: tcg: introduce **tcg_ctxs to keep track of all TCGContext's...
Checking PATCH 44/51: tcg: distribute profiling counters across TCGContext's...
Checking PATCH 45/51: tcg: allocate optimizer temps with tcg_malloc...
Checking PATCH 46/51: osdep: introduce qemu_mprotect_rwx/none...
Checking PATCH 47/51: translate-all: use qemu_protect_rwx/none helpers...
Checking PATCH 48/51: tcg: introduce regions to split code_gen_buffer...
Checking PATCH 49/51: tcg: enable multiple TCG contexts in softmmu...
Checking PATCH 50/51: tcg: Initialize cpu_env generically...
ERROR: do not initialise globals to 0 or NULL
#645: FILE: tcg/tcg.c:124:
+TCGv_env cpu_env = 0;
total: 1 errors, 0 warnings, 567 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 51/51: translate-all: exit from tb_phys_invalidate if qht_remove fails...
=== OUTPUT END ===
Test command exited with code: 1
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@freelists.org
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [Qemu-devel] [PULL 00/51] tcg queued patches
2017-10-25 9:34 [Qemu-devel] [PULL 00/51] tcg queued patches Richard Henderson
` (51 preceding siblings ...)
2017-10-25 10:33 ` [Qemu-devel] [PULL 00/51] tcg queued patches no-reply
@ 2017-10-25 19:03 ` Peter Maydell
2017-11-01 17:34 ` Thomas Huth
53 siblings, 0 replies; 59+ messages in thread
From: Peter Maydell @ 2017-10-25 19:03 UTC (permalink / raw)
To: Richard Henderson; +Cc: QEMU Developers
On 25 October 2017 at 10:34, Richard Henderson
<richard.henderson@linaro.org> wrote:
> Primarily Emilio's work toward removing tb_lock, with fixes.
> But there are some other tcg-related patches that are queued.
>
>
> r~
>
>
> The following changes since commit 3d7196d43bfe12efe98568cb60057e273652b99b:
>
> Merge remote-tracking branch 'remotes/kraxel/tags/usb-20171023-pull-request' into staging (2017-10-24 16:05:57 +0100)
>
> are available in the git repository at:
>
> git://github.com/rth7680/qemu.git tags/pull-tcg-20171025
>
> for you to fetch changes up to cc689485ee3e9dca05765326ee8fd619a6ec48f0:
>
> translate-all: exit from tb_phys_invalidate if qht_remove fails (2017-10-24 13:53:42 -0700)
>
> ----------------------------------------------------------------
> TCG patch queue
>
Applied, thanks.
-- PMM
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [Qemu-devel] [PULL 20/51] qom: Introduce CPUClass.tcg_initialize
2017-10-25 9:35 ` [Qemu-devel] [PULL 20/51] qom: Introduce CPUClass.tcg_initialize Richard Henderson
@ 2017-10-26 12:45 ` Eduardo Habkost
0 siblings, 0 replies; 59+ messages in thread
From: Eduardo Habkost @ 2017-10-26 12:45 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, peter.maydell
On Wed, Oct 25, 2017 at 11:35:04AM +0200, Richard Henderson wrote:
> Move target cpu tcg initialization to common code,
> called from cpu_exec_realizefn.
>
> Acked-by: Andreas Färber <afaerber@suse.de>
> Reviewed-by: Emilio G. Cota <cota@braap.org>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
It looks like this broke --disable-tcg:
https://travis-ci.org/qemu/qemu/jobs/292776092
LINK x86_64-softmmu/qemu-system-x86_64
target/i386/cpu.o: In function `x86_cpu_common_class_init':
/home/travis/build/qemu/qemu/target/i386/cpu.c:4215: undefined reference to `tcg_x86_init'
collect2: error: ld returned 1 exit status
make[1]: *** [qemu-system-x86_64] Error 1
make: *** [subdir-x86_64-softmmu] Error 2
The command "make ${MAKEFLAGS} && ${TEST_CMD}" exited with 2.
--
Eduardo
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [Qemu-devel] [PULL 00/51] tcg queued patches
2017-10-25 9:34 [Qemu-devel] [PULL 00/51] tcg queued patches Richard Henderson
` (52 preceding siblings ...)
2017-10-25 19:03 ` Peter Maydell
@ 2017-11-01 17:34 ` Thomas Huth
2017-11-01 20:36 ` Emilio G. Cota
53 siblings, 1 reply; 59+ messages in thread
From: Thomas Huth @ 2017-11-01 17:34 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: peter.maydell, Emilio G. Cota, qemu-arm
On 25.10.2017 11:34, Richard Henderson wrote:
> Primarily Emilio's work toward removing tb_lock, with fixes.
> But there are some other tcg-related patches that are queued.
>
> r~
>
> The following changes since commit 3d7196d43bfe12efe98568cb60057e273652b99b:
>
> Merge remote-tracking branch 'remotes/kraxel/tags/usb-20171023-pull-request' into staging (2017-10-24 16:05:57 +0100)
>
> are available in the git repository at:
>
> git://github.com/rth7680/qemu.git tags/pull-tcg-20171025
>
> for you to fetch changes up to cc689485ee3e9dca05765326ee8fd619a6ec48f0:
>
> translate-all: exit from tb_phys_invalidate if qht_remove fails (2017-10-24 13:53:42 -0700)
>
> ----------------------------------------------------------------
> TCG patch queue
>
> ----------------------------------------------------------------
> Emilio G. Cota (25):
> tcg: define CF_PARALLEL and use it for TB hashing along with CF_COUNT_MASK
> tcg: convert tb->cflags reads to tb_cflags(tb)
> target/arm: check CF_PARALLEL instead of parallel_cpus
> target/hppa: check CF_PARALLEL instead of parallel_cpus
> target/i386: check CF_PARALLEL instead of parallel_cpus
> target/m68k: check CF_PARALLEL instead of parallel_cpus
> target/s390x: check CF_PARALLEL instead of parallel_cpus
> target/sh4: check CF_PARALLEL instead of parallel_cpus
> target/sparc: check CF_PARALLEL instead of parallel_cpus
> tcg: check CF_PARALLEL instead of parallel_cpus
> cpu-exec: lookup/generate TB outside exclusive region during step_atomic
> translate-all: use a binary search tree to track TBs in TBContext
> exec-all: rename tb_free to tb_remove
> translate-all: report correct avg host TB size
> tcg: take tb_ctx out of TCGContext
> tcg: define tcg_init_ctx and make tcg_ctx a pointer
> gen-icount: fold exitreq_label into TCGContext
> tcg: introduce **tcg_ctxs to keep track of all TCGContext's
> tcg: distribute profiling counters across TCGContext's
> tcg: allocate optimizer temps with tcg_malloc
> osdep: introduce qemu_mprotect_rwx/none
> translate-all: use qemu_protect_rwx/none helpers
> tcg: introduce regions to split code_gen_buffer
> tcg: enable multiple TCG contexts in softmmu
Seems like something in this patch series broke a couple of ARM boards
(smdkc210, nuri, raspi2, xlnx-ep108 and xlnx-zcu102). With current
master branch, I just get this error:
$ aarch64-softmmu/qemu-system-aarch64 -machine raspi2
**
ERROR:/home/thuth/devel/qemu/tcg/tcg.c:537:tcg_register_thread:
assertion failed: (n < max_cpus)
Aborted (core dumped)
Could you please have a look at this?
Thanks,
Thomas
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [Qemu-devel] [PULL 00/51] tcg queued patches
2017-11-01 17:34 ` Thomas Huth
@ 2017-11-01 20:36 ` Emilio G. Cota
2017-11-02 13:38 ` Peter Maydell
0 siblings, 1 reply; 59+ messages in thread
From: Emilio G. Cota @ 2017-11-01 20:36 UTC (permalink / raw)
To: Thomas Huth; +Cc: Richard Henderson, qemu-devel, peter.maydell, qemu-arm
On Wed, Nov 01, 2017 at 18:34:23 +0100, Thomas Huth wrote:
> Seems like something in this patch series broke a couple of ARM boards
> (smdkc210, nuri, raspi2, xlnx-ep108 and xlnx-zcu102). With current
> master branch, I just get this error:
>
> $ aarch64-softmmu/qemu-system-aarch64 -machine raspi2
> **
> ERROR:/home/thuth/devel/qemu/tcg/tcg.c:537:tcg_register_thread:
> assertion failed: (n < max_cpus)
> Aborted (core dumped)
>
> Could you please have a look at this?
Turns out some boards initialize a fixed number of vcpus, which
can be > max_cpus.
The below fixes the issue for me, although I'm not entirely happy
with it because if -{smp,max}_cpus < machine_class->max_cpus, some
TCG regions will be wasted. Not a huge deal (in most cases it will be
2MB per unused vCPU), but a better fix might be to just honour -max_cpus
for these boards. We might just not care enough though.
Emilio
---8<---
Subject: [PATCH] hw: define and use machine_class->max_cpus_override
max_cpus needs to be an upper bound on the number of vCPUs
initialized; otherwise TCG region initialization breaks.
Some boards initialize a hard-coded number of vCPUs; mark this
with machine_class->max_cpus_override so that max_cpus is
set to machine_class->max_cpus when set.
Update the ARM boards that hard-code max_cpus, thereby letting
them boot again.
Reported-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Emilio G. Cota <cota@braap.org>
---
hw/arm/exynos4_boards.c | 2 ++
hw/arm/raspi.c | 1 +
hw/arm/xlnx-zcu102.c | 3 +++
include/hw/boards.h | 3 ++-
vl.c | 4 ++++
5 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
index f1441ec..7071505 100644
--- a/hw/arm/exynos4_boards.c
+++ b/hw/arm/exynos4_boards.c
@@ -189,6 +189,7 @@ static void nuri_class_init(ObjectClass *oc, void *data)
mc->desc = "Samsung NURI board (Exynos4210)";
mc->init = nuri_init;
mc->max_cpus = EXYNOS4210_NCPUS;
+ mc->max_cpus_override = 1;
mc->ignore_memory_transaction_failures = true;
}
@@ -205,6 +206,7 @@ static void smdkc210_class_init(ObjectClass *oc, void *data)
mc->desc = "Samsung SMDKC210 board (Exynos4210)";
mc->init = smdkc210_init;
mc->max_cpus = EXYNOS4210_NCPUS;
+ mc->max_cpus_override = 1;
mc->ignore_memory_transaction_failures = true;
}
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index 5941c9f..bf4eec3 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -167,6 +167,7 @@ static void raspi2_machine_init(MachineClass *mc)
mc->no_floppy = 1;
mc->no_cdrom = 1;
mc->max_cpus = BCM2836_NCPUS;
+ mc->max_cpus_override = 1;
mc->default_ram_size = 1024 * 1024 * 1024;
mc->ignore_memory_transaction_failures = true;
};
diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c
index e2d15a1..f7e0004 100644
--- a/hw/arm/xlnx-zcu102.c
+++ b/hw/arm/xlnx-zcu102.c
@@ -185,6 +185,8 @@ static void xlnx_ep108_machine_class_init(ObjectClass *oc, void *data)
mc->block_default_type = IF_IDE;
mc->units_per_default_bus = 1;
mc->ignore_memory_transaction_failures = true;
+ mc->max_cpus = XLNX_ZYNQMP_NUM_APU_CPUS + XLNX_ZYNQMP_NUM_RPU_CPUS;
+ mc->max_cpus_override = 1;
}
static const TypeInfo xlnx_ep108_machine_init_typeinfo = {
@@ -241,6 +243,7 @@ static void xlnx_zcu102_machine_class_init(ObjectClass *oc, void *data)
mc->units_per_default_bus = 1;
mc->ignore_memory_transaction_failures = true;
mc->max_cpus = XLNX_ZYNQMP_NUM_APU_CPUS + XLNX_ZYNQMP_NUM_RPU_CPUS;
+ mc->max_cpus_override = 1;
}
static const TypeInfo xlnx_zcu102_machine_init_typeinfo = {
diff --git a/include/hw/boards.h b/include/hw/boards.h
index 191a5b3..724be45 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -176,7 +176,8 @@ struct MachineClass {
no_sdcard:1,
has_dynamic_sysbus:1,
pci_allow_0_address:1,
- legacy_fw_cfg_order:1;
+ legacy_fw_cfg_order:1,
+ max_cpus_override:1;
int is_default;
const char *default_machine_opts;
const char *default_boot_order;
diff --git a/vl.c b/vl.c
index ec29909..b2f056a 100644
--- a/vl.c
+++ b/vl.c
@@ -4336,6 +4336,10 @@ int main(int argc, char **argv, char **envp)
machine_class->name, machine_class->max_cpus);
exit(1);
}
+ /* some machines initialize a hard-coded number of cpus */
+ if (machine_class->max_cpus_override) {
+ max_cpus = machine_class->max_cpus;
+ }
/*
* Get the default machine options from the machine if it is not already
--
2.7.4
^ permalink raw reply related [flat|nested] 59+ messages in thread
* Re: [Qemu-devel] [PULL 00/51] tcg queued patches
2017-11-01 20:36 ` Emilio G. Cota
@ 2017-11-02 13:38 ` Peter Maydell
2017-11-02 19:53 ` Emilio G. Cota
0 siblings, 1 reply; 59+ messages in thread
From: Peter Maydell @ 2017-11-02 13:38 UTC (permalink / raw)
To: Emilio G. Cota; +Cc: Thomas Huth, Richard Henderson, QEMU Developers, qemu-arm
On 1 November 2017 at 20:36, Emilio G. Cota <cota@braap.org> wrote:
> On Wed, Nov 01, 2017 at 18:34:23 +0100, Thomas Huth wrote:
>> Seems like something in this patch series broke a couple of ARM boards
>> (smdkc210, nuri, raspi2, xlnx-ep108 and xlnx-zcu102). With current
>> master branch, I just get this error:
>>
>> $ aarch64-softmmu/qemu-system-aarch64 -machine raspi2
>> **
>> ERROR:/home/thuth/devel/qemu/tcg/tcg.c:537:tcg_register_thread:
>> assertion failed: (n < max_cpus)
>> Aborted (core dumped)
>>
>> Could you please have a look at this?
>
> Turns out some boards initialize a fixed number of vcpus, which
> can be > max_cpus.
>
> The below fixes the issue for me, although I'm not entirely happy
> with it because if -{smp,max}_cpus < machine_class->max_cpus, some
> TCG regions will be wasted. Not a huge deal (in most cases it will be
> 2MB per unused vCPU), but a better fix might be to just honour -max_cpus
> for these boards. We might just not care enough though.
Maybe we should allow machine models to specify:
* max_cpus (the most they can support; 1 if not set by board,
as in current code)
* min_cpus (the least they can support; 1 if not set by board)
* default_cpus (what you get if you don't ask for something else;
1 if not set by board)
Then:
* these boards which always create a fixed number of CPUs
should set all three to the same thing
* boards which only create the CPUs requested by the user
can leave them unset (as today)
* the generic command line parsing code should stop with an
error message if the user sets max_cpus smaller than
the board's min_cpus setting or greater than the board's
max_cpus, or if they set -smp to less than the board's
min_cpus
* the TCG code can rely on the max_cpus global being right
Incidentally every time we add a field to MachineClass we
should add a doc comment giving its semantics.
thanks
-- PMM
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [Qemu-devel] [PULL 00/51] tcg queued patches
2017-11-02 13:38 ` Peter Maydell
@ 2017-11-02 19:53 ` Emilio G. Cota
0 siblings, 0 replies; 59+ messages in thread
From: Emilio G. Cota @ 2017-11-02 19:53 UTC (permalink / raw)
To: Peter Maydell; +Cc: Thomas Huth, Richard Henderson, QEMU Developers, qemu-arm
On Thu, Nov 02, 2017 at 13:38:07 +0000, Peter Maydell wrote:
> Maybe we should allow machine models to specify:
> * max_cpus (the most they can support; 1 if not set by board,
> as in current code)
> * min_cpus (the least they can support; 1 if not set by board)
> * default_cpus (what you get if you don't ask for something else;
> 1 if not set by board)
>
> Then:
> * these boards which always create a fixed number of CPUs
> should set all three to the same thing
> * boards which only create the CPUs requested by the user
> can leave them unset (as today)
> * the generic command line parsing code should stop with an
> error message if the user sets max_cpus smaller than
> the board's min_cpus setting or greater than the board's
> max_cpus, or if they set -smp to less than the board's
> min_cpus
Shouldn't we just print a warning (like we've been doing in some
boards, e.g. nuri) and upgrade smp_cpus/max_cpus to whatever value?
Changing this now could qualify as a regression.
Also, just noticed 4bd2f93 ("exynos4_boards: Silence lack
of -smp 2 warning for qtest", 2013-11-05); I don't really know how
"-smp 1" is built in qtest code, but doing as above breaks
check-qtest-aarch64.
E.
^ permalink raw reply [flat|nested] 59+ messages in thread
end of thread, other threads:[~2017-11-02 19:53 UTC | newest]
Thread overview: 59+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-10-25 9:34 [Qemu-devel] [PULL 00/51] tcg queued patches Richard Henderson
2017-10-25 9:34 ` [Qemu-devel] [PULL 01/51] tcg: Merge opcode arguments into TCGOp Richard Henderson
2017-10-25 9:34 ` [Qemu-devel] [PULL 02/51] tcg: Propagate args to op->args in optimizer Richard Henderson
2017-10-25 9:34 ` [Qemu-devel] [PULL 03/51] tcg: Propagate args to op->args in tcg.c Richard Henderson
2017-10-25 9:34 ` [Qemu-devel] [PULL 04/51] tcg: Propagate TCGOp down to allocators Richard Henderson
2017-10-25 9:34 ` [Qemu-devel] [PULL 05/51] tcg: Introduce arg_temp Richard Henderson
2017-10-25 9:34 ` [Qemu-devel] [PULL 06/51] tcg: Add temp_global bit to TCGTemp Richard Henderson
2017-10-25 9:34 ` [Qemu-devel] [PULL 07/51] tcg: Return NULL temp for TCG_CALL_DUMMY_ARG Richard Henderson
2017-10-25 9:34 ` [Qemu-devel] [PULL 08/51] tcg: Introduce temp_arg, export temp_idx Richard Henderson
2017-10-25 9:34 ` [Qemu-devel] [PULL 09/51] tcg: Use per-temp state data in liveness Richard Henderson
2017-10-25 9:34 ` [Qemu-devel] [PULL 10/51] tcg: Avoid loops against variable bounds Richard Henderson
2017-10-25 9:34 ` [Qemu-devel] [PULL 11/51] tcg: Change temp_allocate_frame arg to TCGTemp Richard Henderson
2017-10-25 9:34 ` [Qemu-devel] [PULL 12/51] tcg: Remove unused TCG_CALL_DUMMY_TCGV Richard Henderson
2017-10-25 9:34 ` [Qemu-devel] [PULL 13/51] tcg: Use per-temp state data in optimize Richard Henderson
2017-10-25 9:34 ` [Qemu-devel] [PULL 14/51] tcg: Push tcg_ctx into generator functions Richard Henderson
2017-10-25 9:34 ` [Qemu-devel] [PULL 15/51] tcg: Push tcg_ctx into tcg_gen_callN Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 16/51] tcg: Introduce tcgv_{i32, i64, ptr}_{arg, temp} Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 17/51] tcg: Introduce temp_tcgv_{i32,i64,ptr} Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 18/51] tcg: Remove GET_TCGV_* and MAKE_TCGV_* Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 19/51] tcg: Remove TCGV_EQUAL* Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 20/51] qom: Introduce CPUClass.tcg_initialize Richard Henderson
2017-10-26 12:45 ` Eduardo Habkost
2017-10-25 9:35 ` [Qemu-devel] [PULL 21/51] tcg: Use offsets not indices for TCGv_* Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 22/51] tcg: define CF_PARALLEL and use it for TB hashing along with CF_COUNT_MASK Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 23/51] tcg: Add CPUState cflags_next_tb Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 24/51] tcg: Include CF_COUNT_MASK in CF_HASH_MASK Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 25/51] tcg: convert tb->cflags reads to tb_cflags(tb) Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 26/51] target/arm: check CF_PARALLEL instead of parallel_cpus Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 27/51] target/hppa: " Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 28/51] target/i386: " Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 29/51] target/m68k: " Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 30/51] target/s390x: " Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 31/51] target/sh4: " Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 32/51] target/sparc: " Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 33/51] tcg: " Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 34/51] cpu-exec: lookup/generate TB outside exclusive region during step_atomic Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 35/51] tcg: Add CF_LAST_IO + CF_USE_ICOUNT to CF_HASH_MASK Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 36/51] tcg: Remove CF_IGNORE_ICOUNT Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 37/51] translate-all: use a binary search tree to track TBs in TBContext Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 38/51] exec-all: rename tb_free to tb_remove Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 39/51] translate-all: report correct avg host TB size Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 40/51] tcg: take tb_ctx out of TCGContext Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 41/51] tcg: define tcg_init_ctx and make tcg_ctx a pointer Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 42/51] gen-icount: fold exitreq_label into TCGContext Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 43/51] tcg: introduce **tcg_ctxs to keep track of all TCGContext's Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 44/51] tcg: distribute profiling counters across TCGContext's Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 45/51] tcg: allocate optimizer temps with tcg_malloc Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 46/51] osdep: introduce qemu_mprotect_rwx/none Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 47/51] translate-all: use qemu_protect_rwx/none helpers Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 48/51] tcg: introduce regions to split code_gen_buffer Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 49/51] tcg: enable multiple TCG contexts in softmmu Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 50/51] tcg: Initialize cpu_env generically Richard Henderson
2017-10-25 9:35 ` [Qemu-devel] [PULL 51/51] translate-all: exit from tb_phys_invalidate if qht_remove fails Richard Henderson
2017-10-25 10:33 ` [Qemu-devel] [PULL 00/51] tcg queued patches no-reply
2017-10-25 19:03 ` Peter Maydell
2017-11-01 17:34 ` Thomas Huth
2017-11-01 20:36 ` Emilio G. Cota
2017-11-02 13:38 ` Peter Maydell
2017-11-02 19:53 ` Emilio G. Cota
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