From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.6 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING, NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A7054C433DB for ; Fri, 26 Feb 2021 21:44:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6310A64E60 for ; Fri, 26 Feb 2021 21:44:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229990AbhBZVox (ORCPT ); Fri, 26 Feb 2021 16:44:53 -0500 Received: from mx3.molgen.mpg.de ([141.14.17.11]:52211 "EHLO mx1.molgen.mpg.de" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S229622AbhBZVow (ORCPT ); Fri, 26 Feb 2021 16:44:52 -0500 Received: from [192.168.0.5] (ip5f5aed0c.dynamic.kabel-deutschland.de [95.90.237.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: pmenzel) by mx.molgen.mpg.de (Postfix) with ESMTPSA id 527DD20647910; Fri, 26 Feb 2021 22:44:09 +0100 (CET) Subject: Re: [PATCH] iommu/amd: Fix event counter availability check To: Alexander Monakov , Shuah Khan , Suravee Suthikulpanit Cc: iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, David Coe , Joerg Roedel , "Tj (Elloe Linux)" References: <20200529200738.1923-1-amonakov@ispras.ru> From: Paul Menzel Message-ID: <4aba4c61-1878-3d4e-d52e-3ccac9715010@molgen.mpg.de> Date: Fri, 26 Feb 2021 22:44:08 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.8.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org [cc: +suravee, +jörg] Dear Alex, dear Shuah, dear Suravee, dear Jörg, Am 03.06.20 um 08:54 schrieb Alexander Monakov: > On Tue, 2 Jun 2020, Shuah Khan wrote: > >> I changed the logic to read config to get max banks and counters >> before checking if counters are writable and tried writing to all. >> The result is the same and all of them aren't writable. However, >> when disable the writable check and assume they are, I can run > [snip] > > This is similar to what I did. I also noticed that counters can > be successfully used with perf if the initial check is ignored. > I was considering sending a patch to remove the check and adjust > the event counting logic to use counters as read-only, but after > a bit more investigation I've noticed how late pci_enable_device > is done, and came up with this patch. It's a path of less resistance: > I'd expect maintainers to be more averse to removing the check > rather than fixing it so it works as intended (even though I think > the check should not be there in the first place). > > However: > > The ability to modify the counters is needed only for sampling the > events (getting an interrupt when a counter overflows). There's no > code to do that for these AMD IOMMU counters. A solution I would > prefer is to not write to those counters at all. It would simplify or > even remove a bunch of code. I can submit a corresponding patch if > there's general agreement this path is ok. > > What do you think? I like this idea. Suravee, Jörg, what do you think? Commit 6778ff5b21b (iommu/amd: Fix performance counter initialization) delays the boot up to 100 ms, which is over 20 % on fast systems, and also just a workaround, and does not seem to work always. The delay is also not mentioned in the commit message. Kind regards, Paul [1]: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=6778ff5b21bd8e78c8bd547fd66437cf2657fd9b From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.6 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING, NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F20FAC433E0 for ; Fri, 26 Feb 2021 21:44:22 +0000 (UTC) Received: from smtp1.osuosl.org (smtp1.osuosl.org [140.211.166.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9887864F1F for ; Fri, 26 Feb 2021 21:44:21 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9887864F1F Authentication-Results: mail.kernel.org; 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Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.8.0 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US Cc: David Coe , iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, "Tj \(Elloe Linux\)" X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: base64 Content-Type: text/plain; charset="utf-8"; Format="flowed" Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" W2NjOiArc3VyYXZlZSwgK2rDtnJnXQoKRGVhciBBbGV4LCBkZWFyIFNodWFoLCBkZWFyIFN1cmF2 ZWUsIGRlYXIgSsO2cmcsCgoKQW0gMDMuMDYuMjAgdW0gMDg6NTQgc2NocmllYiBBbGV4YW5kZXIg TW9uYWtvdjoKPiBPbiBUdWUsIDIgSnVuIDIwMjAsIFNodWFoIEtoYW4gd3JvdGU6Cj4gCj4+IEkg Y2hhbmdlZCB0aGUgbG9naWMgdG8gcmVhZCBjb25maWcgdG8gZ2V0IG1heCBiYW5rcyBhbmQgY291 bnRlcnMKPj4gYmVmb3JlIGNoZWNraW5nIGlmIGNvdW50ZXJzIGFyZSB3cml0YWJsZSBhbmQgdHJp ZWQgd3JpdGluZyB0byBhbGwuCj4+IFRoZSByZXN1bHQgaXMgdGhlIHNhbWUgYW5kIGFsbCBvZiB0 aGVtIGFyZW4ndCB3cml0YWJsZS4gSG93ZXZlciwKPj4gd2hlbiBkaXNhYmxlIHRoZSB3cml0YWJs ZSBjaGVjayBhbmQgYXNzdW1lIHRoZXkgYXJlLCBJIGNhbiBydW4KPiBbc25pcF0KPiAKPiBUaGlz IGlzIHNpbWlsYXIgdG8gd2hhdCBJIGRpZC4gSSBhbHNvIG5vdGljZWQgdGhhdCBjb3VudGVycyBj YW4KPiBiZSBzdWNjZXNzZnVsbHkgdXNlZCB3aXRoIHBlcmYgaWYgdGhlIGluaXRpYWwgY2hlY2sg aXMgaWdub3JlZC4KPiBJIHdhcyBjb25zaWRlcmluZyBzZW5kaW5nIGEgcGF0Y2ggdG8gcmVtb3Zl IHRoZSBjaGVjayBhbmQgYWRqdXN0Cj4gdGhlIGV2ZW50IGNvdW50aW5nIGxvZ2ljIHRvIHVzZSBj b3VudGVycyBhcyByZWFkLW9ubHksIGJ1dCBhZnRlcgo+IGEgYml0IG1vcmUgaW52ZXN0aWdhdGlv biBJJ3ZlIG5vdGljZWQgaG93IGxhdGUgcGNpX2VuYWJsZV9kZXZpY2UKPiBpcyBkb25lLCBhbmQg Y2FtZSB1cCB3aXRoIHRoaXMgcGF0Y2guIEl0J3MgYSBwYXRoIG9mIGxlc3MgcmVzaXN0YW5jZToK PiBJJ2QgZXhwZWN0IG1haW50YWluZXJzIHRvIGJlIG1vcmUgYXZlcnNlIHRvIHJlbW92aW5nIHRo ZSBjaGVjawo+IHJhdGhlciB0aGFuIGZpeGluZyBpdCBzbyBpdCB3b3JrcyBhcyBpbnRlbmRlZCAo ZXZlbiB0aG91Z2ggSSB0aGluawo+IHRoZSBjaGVjayBzaG91bGQgbm90IGJlIHRoZXJlIGluIHRo ZSBmaXJzdCBwbGFjZSkuCj4gCj4gSG93ZXZlcjoKPiAKPiBUaGUgYWJpbGl0eSB0byBtb2RpZnkg dGhlIGNvdW50ZXJzIGlzIG5lZWRlZCBvbmx5IGZvciBzYW1wbGluZyB0aGUKPiBldmVudHMgKGdl dHRpbmcgYW4gaW50ZXJydXB0IHdoZW4gYSBjb3VudGVyIG92ZXJmbG93cykuIFRoZXJlJ3Mgbm8K PiBjb2RlIHRvIGRvIHRoYXQgZm9yIHRoZXNlIEFNRCBJT01NVSBjb3VudGVycy4gQSBzb2x1dGlv biBJIHdvdWxkCj4gcHJlZmVyIGlzIHRvIG5vdCB3cml0ZSB0byB0aG9zZSBjb3VudGVycyBhdCBh bGwuIEl0IHdvdWxkIHNpbXBsaWZ5IG9yCj4gZXZlbiByZW1vdmUgYSBidW5jaCBvZiBjb2RlLiBJ IGNhbiBzdWJtaXQgYSBjb3JyZXNwb25kaW5nIHBhdGNoIGlmCj4gdGhlcmUncyBnZW5lcmFsIGFn cmVlbWVudCB0aGlzIHBhdGggaXMgb2suCj4gCj4gV2hhdCBkbyB5b3UgdGhpbms/CgpJIGxpa2Ug dGhpcyBpZGVhLiBTdXJhdmVlLCBKw7ZyZywgd2hhdCBkbyB5b3UgdGhpbms/CgpDb21taXQgNjc3 OGZmNWIyMWIgKGlvbW11L2FtZDogRml4IHBlcmZvcm1hbmNlIGNvdW50ZXIgaW5pdGlhbGl6YXRp b24pIApkZWxheXMgdGhlIGJvb3QgdXAgdG8gMTAwIG1zLCB3aGljaCBpcyBvdmVyIDIwICUgb24g ZmFzdCBzeXN0ZW1zLCBhbmQgCmFsc28ganVzdCBhIHdvcmthcm91bmQsIGFuZCBkb2VzIG5vdCBz ZWVtIHRvIHdvcmsgYWx3YXlzLiBUaGUgZGVsYXkgaXMgCmFsc28gbm90IG1lbnRpb25lZCBpbiB0 aGUgY29tbWl0IG1lc3NhZ2UuCgoKS2luZCByZWdhcmRzLAoKUGF1bAoKClsxXTogCmh0dHBzOi8v Z2l0Lmtlcm5lbC5vcmcvcHViL3NjbS9saW51eC9rZXJuZWwvZ2l0L3RvcnZhbGRzL2xpbnV4Lmdp dC9jb21taXQvP2lkPTY3NzhmZjViMjFiZDhlNzhjOGJkNTQ3ZmQ2NjQzN2NmMjY1N2ZkOWIKX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KaW9tbXUgbWFpbGlu ZyBsaXN0CmlvbW11QGxpc3RzLmxpbnV4LWZvdW5kYXRpb24ub3JnCmh0dHBzOi8vbGlzdHMubGlu dXhmb3VuZGF0aW9uLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2lvbW11