From mboxrd@z Thu Jan 1 00:00:00 1970 From: Samuel Holland Date: Thu, 21 Jan 2021 19:43:04 -0600 Subject: [linux-sunxi] Re: [PATCH v2 05/21] sunxi: prcm: Add memory map for H6 like SoCs In-Reply-To: <20210122011431.2532a82d@slackpad.fritz.box> References: <20210111201153.1800440-1-jernej.skrabec@siol.net> <20210111201153.1800440-6-jernej.skrabec@siol.net> <20210122011431.2532a82d@slackpad.fritz.box> Message-ID: <4af0a4de-2cd7-878b-2bc7-662bcdee744b@sholland.org> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 1/21/21 7:14 PM, Andre Przywara wrote: > On Mon, 11 Jan 2021 21:11:37 +0100 > Jernej Skrabec wrote: > >> There was no need to have prcm definitions for H6 and similar SoCs till >> now. However, support R_I2C will be needed soon in SPL. >> >> Move old definitions to prcm_sun6i.h and add new ones in prcm_sun50i.h. >> One of those files will be selected in common prcm.h based on defined >> macros. >> >> This commit doesn't do any functional change. > > That looks alright. > prcm.h and prcm_sun6i.h are identical, apart from the header guards. > I could verify most of the sun50i PRCM fields by comparing to the Linux > CCU_R driver, but not all of them. > Out of curiosity, where do those offsets actually come from? Some BSP > code? And they are actually SUN50I_H6 aka. "NCAT" specific, right? Compare: https://github.com/orangepi-xunlong/linux-orangepi/blob/orange-pi-4.9-sun50iw9/drivers/clk/sunxi/clk-sun50iw6.h#L148 https://github.com/orangepi-xunlong/linux-orangepi/blob/orange-pi-4.9-sun50iw9/drivers/clk/sunxi/clk-sun50iw9.h#L158 (This, and experimentation, is also where my "0x20c is the highest clock-gate-related register" comment on the DTS came from). Cheers, Samuel