From: Like Xu <like.xu.linux@gmail.com>
To: Xiaoyao Li <xiaoyao.li@intel.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>,
Jim Mattson <jmattson@google.com>,
Wanpeng Li <wanpengli@tencent.com>,
Vitaly Kuznetsov <vkuznets@redhat.com>,
Joerg Roedel <joro@8bytes.org>,
x86@kernel.org, kvm@vger.kernel.org,
linux-kernel@vger.kernel.org,
Sean Christopherson <seanjc@google.com>
Subject: Re: [PATCH v2] KVM: x86/pt: Ignore all unknown Intel PT capabilities
Date: Tue, 11 Jan 2022 16:15:36 +0800 [thread overview]
Message-ID: <4afbaf27-04a9-91a6-f9fa-178e4624b482@gmail.com> (raw)
In-Reply-To: <8a6e5b96-1191-7693-314a-1714cb7c9c9c@intel.com>
On 11/1/2022 3:59 pm, Xiaoyao Li wrote:
>>
>> +#define GUEST_SUPPORTED_CPUID_14_EBX \
>> + (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5))
>> +
>> +#define GUEST_SUPPORTED_CPUID_14_ECX \
>> + (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(31))
>> +
>
> I doubt BIT(3) of CPUID_14_ECX can be exposed to guest directly.
>
> It means "output to Trace Transport Subsystem Supported". If I understand
> correctly, it at least needs passthrough of the said Transport Subsystem or
> emulation of it.
I'm not surprised that we can route Intel Guest PT output to a platform-specific
trace endpoint (e.g., physical or emulated JTAG) as an MMIO debug port.
prev parent reply other threads:[~2022-01-11 8:15 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-10 3:47 [PATCH v2] KVM: x86/pt: Ignore all unknown Intel PT capabilities Like Xu
2022-01-11 0:57 ` Sean Christopherson
2022-01-11 4:20 ` Like Xu
2022-01-11 6:24 ` Like Xu
2022-01-11 7:59 ` Xiaoyao Li
2022-01-11 8:15 ` Like Xu [this message]
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