From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 25B1BC4741F for ; Mon, 28 Sep 2020 16:30:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D4E7B214D8 for ; Mon, 28 Sep 2020 16:30:23 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="WzhNVOdn" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726281AbgI1QaW (ORCPT ); Mon, 28 Sep 2020 12:30:22 -0400 Received: from m42-4.mailgun.net ([69.72.42.4]:33793 "EHLO m42-4.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726327AbgI1QaV (ORCPT ); Mon, 28 Sep 2020 12:30:21 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1601310620; h=Message-ID: References: In-Reply-To: Subject: Cc: To: From: Date: Content-Transfer-Encoding: Content-Type: MIME-Version: Sender; bh=SAmnBQWegwIwm9Xn+KJtdwofE2MDCDVVlnjeJizgtgQ=; b=WzhNVOdnZbqaMzNDLCEFBC0ocWF1M6Riq9OkW6tOPz1htnjQcQ4gw/87JB+Z4FNebRnlIx2U IHHQabmq9cZsKNnT27i2l6IwHJ1sQ1YzLuOLKA7bPVduR/7ksiV1iFqw36faGipeozEUSFq8 b9ux/j+/KdgdU2PEXWCyk86821o= X-Mailgun-Sending-Ip: 69.72.42.4 X-Mailgun-Sid: WyI1MzIzYiIsICJsaW51eC1hcm0tbXNtQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n03.prod.us-west-2.postgun.com with SMTP id 5f720f9b7e9d6827ec7f7859 (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Mon, 28 Sep 2020 16:30:19 GMT Sender: saiprakash.ranjan=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id A5797C433CA; Mon, 28 Sep 2020 16:30:19 +0000 (UTC) Received: from mail.codeaurora.org (localhost.localdomain [127.0.0.1]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: saiprakash.ranjan) by smtp.codeaurora.org (Postfix) with ESMTPSA id 1C0E8C433CB; Mon, 28 Sep 2020 16:30:18 +0000 (UTC) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII; format=flowed Content-Transfer-Encoding: 7bit Date: Mon, 28 Sep 2020 22:00:17 +0530 From: Sai Prakash Ranjan To: Jordan Crouse Cc: Will Deacon , Robin Murphy , Joerg Roedel , Rob Clark , iommu@lists.linux-foundation.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Akhil P Oommen , Bjorn Andersson , freedreno@lists.freedesktop.org, "Kristian H . Kristensen" , dri-devel@lists.freedesktop.org, Sharat Masetty , Jonathan Marek , jcrouse=codeaurora.org@codeaurora.org Subject: Re: [PATCHv5 4/6] drm/msm/a6xx: Add support for using system cache(LLC) In-Reply-To: <20200928161125.GA29832@jcrouse1-lnx.qualcomm.com> References: <889a32458cec92ed110b94f393aa1c2f0d64dca5.1600754909.git.saiprakash.ranjan@codeaurora.org> <20200923150320.GD31425@jcrouse1-lnx.qualcomm.com> <800c2108606cb921fef1ffc27569ffb2@codeaurora.org> <20200928161125.GA29832@jcrouse1-lnx.qualcomm.com> Message-ID: <4bac115897afae4fac4401c57201424e@codeaurora.org> X-Sender: saiprakash.ranjan@codeaurora.org User-Agent: Roundcube Webmail/1.3.9 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 2020-09-28 21:41, Jordan Crouse wrote: > On Mon, Sep 28, 2020 at 05:56:55PM +0530, Sai Prakash Ranjan wrote: >> Hi Jordan, >> >> On 2020-09-23 20:33, Jordan Crouse wrote: >> >On Tue, Sep 22, 2020 at 11:48:17AM +0530, Sai Prakash Ranjan wrote: >> >>From: Sharat Masetty >> >> >> >>The last level system cache can be partitioned to 32 different >> >>slices of which GPU has two slices preallocated. One slice is >> >>used for caching GPU buffers and the other slice is used for >> >>caching the GPU SMMU pagetables. This talks to the core system >> >>cache driver to acquire the slice handles, configure the SCID's >> >>to those slices and activates and deactivates the slices upon >> >>GPU power collapse and restore. >> >> >> >>Some support from the IOMMU driver is also needed to make use >> >>of the system cache to set the right TCR attributes. GPU then >> >>has the ability to override a few cacheability parameters which >> >>it does to override write-allocate to write-no-allocate as the >> >>GPU hardware does not benefit much from it. >> >> >> >>DOMAIN_ATTR_SYS_CACHE is another domain level attribute used by the >> >>IOMMU driver to set the right attributes to cache the hardware >> >>pagetables into the system cache. >> >> >> >>Signed-off-by: Sharat Masetty >> >>[saiprakash.ranjan: fix to set attr before device attach to iommu and >> >>rebase] >> >>Signed-off-by: Sai Prakash Ranjan >> >>--- >> >> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 83 +++++++++++++++++++++++++ >> >> drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 4 ++ >> >> drivers/gpu/drm/msm/adreno/adreno_gpu.c | 17 +++++ >> >> 3 files changed, 104 insertions(+) >> >> >> >>diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >> >>b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >> >>index 8915882e4444..151190ff62f7 100644 >> >>--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >> >>+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >> >>@@ -8,7 +8,9 @@ >> >> #include "a6xx_gpu.h" >> >> #include "a6xx_gmu.xml.h" >> >> >> >>+#include >> >> #include >> >>+#include >> >> >> >> #define GPU_PAS_ID 13 >> >> >> >>@@ -1022,6 +1024,79 @@ static irqreturn_t a6xx_irq(struct msm_gpu *gpu) >> >> return IRQ_HANDLED; >> >> } >> >> >> >>+static void a6xx_llc_rmw(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 mask, >> >>u32 or) >> >>+{ >> >>+ return msm_rmw(a6xx_gpu->llc_mmio + (reg << 2), mask, or); >> >>+} >> >>+ >> >>+static void a6xx_llc_write(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 >> >>value) >> >>+{ >> >>+ return msm_writel(value, a6xx_gpu->llc_mmio + (reg << 2)); >> >>+} >> >>+ >> >>+static void a6xx_llc_deactivate(struct a6xx_gpu *a6xx_gpu) >> >>+{ >> >>+ llcc_slice_deactivate(a6xx_gpu->llc_slice); >> >>+ llcc_slice_deactivate(a6xx_gpu->htw_llc_slice); >> >>+} >> >>+ >> >>+static void a6xx_llc_activate(struct a6xx_gpu *a6xx_gpu) >> >>+{ >> >>+ u32 cntl1_regval = 0; >> >>+ >> >>+ if (IS_ERR(a6xx_gpu->llc_mmio)) >> >>+ return; >> >>+ >> >>+ if (!llcc_slice_activate(a6xx_gpu->llc_slice)) { >> >>+ u32 gpu_scid = llcc_get_slice_id(a6xx_gpu->llc_slice); >> >>+ >> >>+ gpu_scid &= 0x1f; >> >>+ cntl1_regval = (gpu_scid << 0) | (gpu_scid << 5) | (gpu_scid << 10) | >> >>+ (gpu_scid << 15) | (gpu_scid << 20); >> >>+ } >> >>+ >> >>+ if (!llcc_slice_activate(a6xx_gpu->htw_llc_slice)) { >> >>+ u32 gpuhtw_scid = llcc_get_slice_id(a6xx_gpu->htw_llc_slice); >> >>+ >> >>+ gpuhtw_scid &= 0x1f; >> >>+ cntl1_regval |= FIELD_PREP(GENMASK(29, 25), gpuhtw_scid); >> >>+ } >> >>+ >> >>+ if (cntl1_regval) { >> >>+ /* >> >>+ * Program the slice IDs for the various GPU blocks and GPU MMU >> >>+ * pagetables >> >>+ */ >> >>+ a6xx_llc_write(a6xx_gpu, REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1, >> >>cntl1_regval); >> >>+ >> >>+ /* >> >>+ * Program cacheability overrides to not allocate cache lines on >> >>+ * a write miss >> >>+ */ >> >>+ a6xx_llc_rmw(a6xx_gpu, REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0, 0xF, >> >>0x03); >> >>+ } >> >>+} >> > >> >This code has been around long enough that it pre-dates a650. On a650 and >> >other >> >MMU-500 targets the htw_llc is configured by the firmware and the >> >llc_slice is >> >configured in a different register. >> > >> >I don't think we need to pause everything and add support for the MMU-500 >> >path, >> >but we do need a way to disallow LLCC on affected targets until such time >> >that >> >we can get it fixed up. >> > >> >> Thanks for taking a close look, does something like below look ok or >> something >> else is needed here? >> >> + /* Till the time we get in LLCC support for A650 */ >> + if (!(info && info->revn == 650)) >> + a6xx_llc_slices_init(pdev, a6xx_gpu); > > It doesn't look like Rob picked this up for 5.10, so we have some time > to do it > right. Would you like me to give you an add-on patch for mmu-500 > targets? > Yes that will be great. Thanks, Sai -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 585DAC2D0A8 for ; Mon, 28 Sep 2020 16:32:17 +0000 (UTC) Received: from fraxinus.osuosl.org (smtp4.osuosl.org [140.211.166.137]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DF3A121548 for ; Mon, 28 Sep 2020 16:32:16 +0000 (UTC) Authentication-Results: mail.kernel.org; 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Mon, 28 Sep 2020 16:30:18 +0000 (UTC) MIME-Version: 1.0 Date: Mon, 28 Sep 2020 22:00:17 +0530 From: Sai Prakash Ranjan To: Jordan Crouse Subject: Re: [PATCHv5 4/6] drm/msm/a6xx: Add support for using system cache(LLC) In-Reply-To: <20200928161125.GA29832@jcrouse1-lnx.qualcomm.com> References: <889a32458cec92ed110b94f393aa1c2f0d64dca5.1600754909.git.saiprakash.ranjan@codeaurora.org> <20200923150320.GD31425@jcrouse1-lnx.qualcomm.com> <800c2108606cb921fef1ffc27569ffb2@codeaurora.org> <20200928161125.GA29832@jcrouse1-lnx.qualcomm.com> Message-ID: <4bac115897afae4fac4401c57201424e@codeaurora.org> X-Sender: saiprakash.ranjan@codeaurora.org User-Agent: Roundcube Webmail/1.3.9 Cc: freedreno@lists.freedesktop.org, jcrouse=codeaurora.org@codeaurora.org, Jonathan Marek , Will Deacon , iommu@lists.linux-foundation.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Akhil P Oommen , linux-arm-msm@vger.kernel.org, "Kristian H . Kristensen" , Robin Murphy , Sharat Masetty , linux-arm-kernel@lists.infradead.org X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" On 2020-09-28 21:41, Jordan Crouse wrote: > On Mon, Sep 28, 2020 at 05:56:55PM +0530, Sai Prakash Ranjan wrote: >> Hi Jordan, >> >> On 2020-09-23 20:33, Jordan Crouse wrote: >> >On Tue, Sep 22, 2020 at 11:48:17AM +0530, Sai Prakash Ranjan wrote: >> >>From: Sharat Masetty >> >> >> >>The last level system cache can be partitioned to 32 different >> >>slices of which GPU has two slices preallocated. One slice is >> >>used for caching GPU buffers and the other slice is used for >> >>caching the GPU SMMU pagetables. This talks to the core system >> >>cache driver to acquire the slice handles, configure the SCID's >> >>to those slices and activates and deactivates the slices upon >> >>GPU power collapse and restore. >> >> >> >>Some support from the IOMMU driver is also needed to make use >> >>of the system cache to set the right TCR attributes. GPU then >> >>has the ability to override a few cacheability parameters which >> >>it does to override write-allocate to write-no-allocate as the >> >>GPU hardware does not benefit much from it. >> >> >> >>DOMAIN_ATTR_SYS_CACHE is another domain level attribute used by the >> >>IOMMU driver to set the right attributes to cache the hardware >> >>pagetables into the system cache. >> >> >> >>Signed-off-by: Sharat Masetty >> >>[saiprakash.ranjan: fix to set attr before device attach to iommu and >> >>rebase] >> >>Signed-off-by: Sai Prakash Ranjan >> >>--- >> >> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 83 +++++++++++++++++++++++++ >> >> drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 4 ++ >> >> drivers/gpu/drm/msm/adreno/adreno_gpu.c | 17 +++++ >> >> 3 files changed, 104 insertions(+) >> >> >> >>diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >> >>b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >> >>index 8915882e4444..151190ff62f7 100644 >> >>--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >> >>+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >> >>@@ -8,7 +8,9 @@ >> >> #include "a6xx_gpu.h" >> >> #include "a6xx_gmu.xml.h" >> >> >> >>+#include >> >> #include >> >>+#include >> >> >> >> #define GPU_PAS_ID 13 >> >> >> >>@@ -1022,6 +1024,79 @@ static irqreturn_t a6xx_irq(struct msm_gpu *gpu) >> >> return IRQ_HANDLED; >> >> } >> >> >> >>+static void a6xx_llc_rmw(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 mask, >> >>u32 or) >> >>+{ >> >>+ return msm_rmw(a6xx_gpu->llc_mmio + (reg << 2), mask, or); >> >>+} >> >>+ >> >>+static void a6xx_llc_write(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 >> >>value) >> >>+{ >> >>+ return msm_writel(value, a6xx_gpu->llc_mmio + (reg << 2)); >> >>+} >> >>+ >> >>+static void a6xx_llc_deactivate(struct a6xx_gpu *a6xx_gpu) >> >>+{ >> >>+ llcc_slice_deactivate(a6xx_gpu->llc_slice); >> >>+ llcc_slice_deactivate(a6xx_gpu->htw_llc_slice); >> >>+} >> >>+ >> >>+static void a6xx_llc_activate(struct a6xx_gpu *a6xx_gpu) >> >>+{ >> >>+ u32 cntl1_regval = 0; >> >>+ >> >>+ if (IS_ERR(a6xx_gpu->llc_mmio)) >> >>+ return; >> >>+ >> >>+ if (!llcc_slice_activate(a6xx_gpu->llc_slice)) { >> >>+ u32 gpu_scid = llcc_get_slice_id(a6xx_gpu->llc_slice); >> >>+ >> >>+ gpu_scid &= 0x1f; >> >>+ cntl1_regval = (gpu_scid << 0) | (gpu_scid << 5) | (gpu_scid << 10) | >> >>+ (gpu_scid << 15) | (gpu_scid << 20); >> >>+ } >> >>+ >> >>+ if (!llcc_slice_activate(a6xx_gpu->htw_llc_slice)) { >> >>+ u32 gpuhtw_scid = llcc_get_slice_id(a6xx_gpu->htw_llc_slice); >> >>+ >> >>+ gpuhtw_scid &= 0x1f; >> >>+ cntl1_regval |= FIELD_PREP(GENMASK(29, 25), gpuhtw_scid); >> >>+ } >> >>+ >> >>+ if (cntl1_regval) { >> >>+ /* >> >>+ * Program the slice IDs for the various GPU blocks and GPU MMU >> >>+ * pagetables >> >>+ */ >> >>+ a6xx_llc_write(a6xx_gpu, REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1, >> >>cntl1_regval); >> >>+ >> >>+ /* >> >>+ * Program cacheability overrides to not allocate cache lines on >> >>+ * a write miss >> >>+ */ >> >>+ a6xx_llc_rmw(a6xx_gpu, REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0, 0xF, >> >>0x03); >> >>+ } >> >>+} >> > >> >This code has been around long enough that it pre-dates a650. On a650 and >> >other >> >MMU-500 targets the htw_llc is configured by the firmware and the >> >llc_slice is >> >configured in a different register. >> > >> >I don't think we need to pause everything and add support for the MMU-500 >> >path, >> >but we do need a way to disallow LLCC on affected targets until such time >> >that >> >we can get it fixed up. >> > >> >> Thanks for taking a close look, does something like below look ok or >> something >> else is needed here? >> >> + /* Till the time we get in LLCC support for A650 */ >> + if (!(info && info->revn == 650)) >> + a6xx_llc_slices_init(pdev, a6xx_gpu); > > It doesn't look like Rob picked this up for 5.10, so we have some time > to do it > right. Would you like me to give you an add-on patch for mmu-500 > targets? > Yes that will be great. Thanks, Sai -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6DE58C2D0A8 for ; Mon, 28 Sep 2020 16:34:09 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 080712100A for ; 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Mon, 28 Sep 2020 16:30:18 +0000 (UTC) MIME-Version: 1.0 Date: Mon, 28 Sep 2020 22:00:17 +0530 From: Sai Prakash Ranjan To: Jordan Crouse Subject: Re: [PATCHv5 4/6] drm/msm/a6xx: Add support for using system cache(LLC) In-Reply-To: <20200928161125.GA29832@jcrouse1-lnx.qualcomm.com> References: <889a32458cec92ed110b94f393aa1c2f0d64dca5.1600754909.git.saiprakash.ranjan@codeaurora.org> <20200923150320.GD31425@jcrouse1-lnx.qualcomm.com> <800c2108606cb921fef1ffc27569ffb2@codeaurora.org> <20200928161125.GA29832@jcrouse1-lnx.qualcomm.com> Message-ID: <4bac115897afae4fac4401c57201424e@codeaurora.org> X-Sender: saiprakash.ranjan@codeaurora.org User-Agent: Roundcube Webmail/1.3.9 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200928_123237_847345_959C1AFB X-CRM114-Status: GOOD ( 28.86 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: freedreno@lists.freedesktop.org, jcrouse=codeaurora.org@codeaurora.org, Jonathan Marek , Will Deacon , Joerg Roedel , iommu@lists.linux-foundation.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Rob Clark , Akhil P Oommen , linux-arm-msm@vger.kernel.org, "Kristian H . Kristensen" , Bjorn Andersson , Robin Murphy , Sharat Masetty , linux-arm-kernel@lists.infradead.org Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 2020-09-28 21:41, Jordan Crouse wrote: > On Mon, Sep 28, 2020 at 05:56:55PM +0530, Sai Prakash Ranjan wrote: >> Hi Jordan, >> >> On 2020-09-23 20:33, Jordan Crouse wrote: >> >On Tue, Sep 22, 2020 at 11:48:17AM +0530, Sai Prakash Ranjan wrote: >> >>From: Sharat Masetty >> >> >> >>The last level system cache can be partitioned to 32 different >> >>slices of which GPU has two slices preallocated. One slice is >> >>used for caching GPU buffers and the other slice is used for >> >>caching the GPU SMMU pagetables. This talks to the core system >> >>cache driver to acquire the slice handles, configure the SCID's >> >>to those slices and activates and deactivates the slices upon >> >>GPU power collapse and restore. >> >> >> >>Some support from the IOMMU driver is also needed to make use >> >>of the system cache to set the right TCR attributes. GPU then >> >>has the ability to override a few cacheability parameters which >> >>it does to override write-allocate to write-no-allocate as the >> >>GPU hardware does not benefit much from it. >> >> >> >>DOMAIN_ATTR_SYS_CACHE is another domain level attribute used by the >> >>IOMMU driver to set the right attributes to cache the hardware >> >>pagetables into the system cache. >> >> >> >>Signed-off-by: Sharat Masetty >> >>[saiprakash.ranjan: fix to set attr before device attach to iommu and >> >>rebase] >> >>Signed-off-by: Sai Prakash Ranjan >> >>--- >> >> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 83 +++++++++++++++++++++++++ >> >> drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 4 ++ >> >> drivers/gpu/drm/msm/adreno/adreno_gpu.c | 17 +++++ >> >> 3 files changed, 104 insertions(+) >> >> >> >>diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >> >>b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >> >>index 8915882e4444..151190ff62f7 100644 >> >>--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >> >>+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >> >>@@ -8,7 +8,9 @@ >> >> #include "a6xx_gpu.h" >> >> #include "a6xx_gmu.xml.h" >> >> >> >>+#include >> >> #include >> >>+#include >> >> >> >> #define GPU_PAS_ID 13 >> >> >> >>@@ -1022,6 +1024,79 @@ static irqreturn_t a6xx_irq(struct msm_gpu *gpu) >> >> return IRQ_HANDLED; >> >> } >> >> >> >>+static void a6xx_llc_rmw(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 mask, >> >>u32 or) >> >>+{ >> >>+ return msm_rmw(a6xx_gpu->llc_mmio + (reg << 2), mask, or); >> >>+} >> >>+ >> >>+static void a6xx_llc_write(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 >> >>value) >> >>+{ >> >>+ return msm_writel(value, a6xx_gpu->llc_mmio + (reg << 2)); >> >>+} >> >>+ >> >>+static void a6xx_llc_deactivate(struct a6xx_gpu *a6xx_gpu) >> >>+{ >> >>+ llcc_slice_deactivate(a6xx_gpu->llc_slice); >> >>+ llcc_slice_deactivate(a6xx_gpu->htw_llc_slice); >> >>+} >> >>+ >> >>+static void a6xx_llc_activate(struct a6xx_gpu *a6xx_gpu) >> >>+{ >> >>+ u32 cntl1_regval = 0; >> >>+ >> >>+ if (IS_ERR(a6xx_gpu->llc_mmio)) >> >>+ return; >> >>+ >> >>+ if (!llcc_slice_activate(a6xx_gpu->llc_slice)) { >> >>+ u32 gpu_scid = llcc_get_slice_id(a6xx_gpu->llc_slice); >> >>+ >> >>+ gpu_scid &= 0x1f; >> >>+ cntl1_regval = (gpu_scid << 0) | (gpu_scid << 5) | (gpu_scid << 10) | >> >>+ (gpu_scid << 15) | (gpu_scid << 20); >> >>+ } >> >>+ >> >>+ if (!llcc_slice_activate(a6xx_gpu->htw_llc_slice)) { >> >>+ u32 gpuhtw_scid = llcc_get_slice_id(a6xx_gpu->htw_llc_slice); >> >>+ >> >>+ gpuhtw_scid &= 0x1f; >> >>+ cntl1_regval |= FIELD_PREP(GENMASK(29, 25), gpuhtw_scid); >> >>+ } >> >>+ >> >>+ if (cntl1_regval) { >> >>+ /* >> >>+ * Program the slice IDs for the various GPU blocks and GPU MMU >> >>+ * pagetables >> >>+ */ >> >>+ a6xx_llc_write(a6xx_gpu, REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1, >> >>cntl1_regval); >> >>+ >> >>+ /* >> >>+ * Program cacheability overrides to not allocate cache lines on >> >>+ * a write miss >> >>+ */ >> >>+ a6xx_llc_rmw(a6xx_gpu, REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0, 0xF, >> >>0x03); >> >>+ } >> >>+} >> > >> >This code has been around long enough that it pre-dates a650. On a650 and >> >other >> >MMU-500 targets the htw_llc is configured by the firmware and the >> >llc_slice is >> >configured in a different register. >> > >> >I don't think we need to pause everything and add support for the MMU-500 >> >path, >> >but we do need a way to disallow LLCC on affected targets until such time >> >that >> >we can get it fixed up. >> > >> >> Thanks for taking a close look, does something like below look ok or >> something >> else is needed here? >> >> + /* Till the time we get in LLCC support for A650 */ >> + if (!(info && info->revn == 650)) >> + a6xx_llc_slices_init(pdev, a6xx_gpu); > > It doesn't look like Rob picked this up for 5.10, so we have some time > to do it > right. Would you like me to give you an add-on patch for mmu-500 > targets? > Yes that will be great. Thanks, Sai -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D882CC47423 for ; Tue, 29 Sep 2020 07:14:38 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 96B7320754 for ; Tue, 29 Sep 2020 07:14:38 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="WzhNVOdn" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 96B7320754 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E95B189C1B; Tue, 29 Sep 2020 07:14:28 +0000 (UTC) Received: from m42-4.mailgun.net (m42-4.mailgun.net [69.72.42.4]) by gabe.freedesktop.org (Postfix) with ESMTPS id 627C789E2B for ; Mon, 28 Sep 2020 16:30:20 +0000 (UTC) DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1601310620; h=Message-ID: References: In-Reply-To: Subject: Cc: To: From: Date: Content-Transfer-Encoding: Content-Type: MIME-Version: Sender; bh=SAmnBQWegwIwm9Xn+KJtdwofE2MDCDVVlnjeJizgtgQ=; b=WzhNVOdnZbqaMzNDLCEFBC0ocWF1M6Riq9OkW6tOPz1htnjQcQ4gw/87JB+Z4FNebRnlIx2U IHHQabmq9cZsKNnT27i2l6IwHJ1sQ1YzLuOLKA7bPVduR/7ksiV1iFqw36faGipeozEUSFq8 b9ux/j+/KdgdU2PEXWCyk86821o= X-Mailgun-Sending-Ip: 69.72.42.4 X-Mailgun-Sid: WyJkOTU5ZSIsICJkcmktZGV2ZWxAbGlzdHMuZnJlZWRlc2t0b3Aub3JnIiwgImJlOWU0YSJd Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n04.prod.us-west-2.postgun.com with SMTP id 5f720f9b19fe605f25694f2c (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Mon, 28 Sep 2020 16:30:19 GMT Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 804C2C43382; Mon, 28 Sep 2020 16:30:19 +0000 (UTC) Received: from mail.codeaurora.org (localhost.localdomain [127.0.0.1]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: saiprakash.ranjan) by smtp.codeaurora.org (Postfix) with ESMTPSA id 1C0E8C433CB; Mon, 28 Sep 2020 16:30:18 +0000 (UTC) MIME-Version: 1.0 Date: Mon, 28 Sep 2020 22:00:17 +0530 From: Sai Prakash Ranjan To: Jordan Crouse Subject: Re: [PATCHv5 4/6] drm/msm/a6xx: Add support for using system cache(LLC) In-Reply-To: <20200928161125.GA29832@jcrouse1-lnx.qualcomm.com> References: <889a32458cec92ed110b94f393aa1c2f0d64dca5.1600754909.git.saiprakash.ranjan@codeaurora.org> <20200923150320.GD31425@jcrouse1-lnx.qualcomm.com> <800c2108606cb921fef1ffc27569ffb2@codeaurora.org> <20200928161125.GA29832@jcrouse1-lnx.qualcomm.com> Message-ID: <4bac115897afae4fac4401c57201424e@codeaurora.org> X-Sender: saiprakash.ranjan@codeaurora.org User-Agent: Roundcube Webmail/1.3.9 X-Mailman-Approved-At: Tue, 29 Sep 2020 07:12:58 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: freedreno@lists.freedesktop.org, jcrouse=codeaurora.org@codeaurora.org, Jonathan Marek , Will Deacon , Joerg Roedel , iommu@lists.linux-foundation.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Akhil P Oommen , linux-arm-msm@vger.kernel.org, "Kristian H . Kristensen" , Bjorn Andersson , Robin Murphy , Sharat Masetty , linux-arm-kernel@lists.infradead.org Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On 2020-09-28 21:41, Jordan Crouse wrote: > On Mon, Sep 28, 2020 at 05:56:55PM +0530, Sai Prakash Ranjan wrote: >> Hi Jordan, >> >> On 2020-09-23 20:33, Jordan Crouse wrote: >> >On Tue, Sep 22, 2020 at 11:48:17AM +0530, Sai Prakash Ranjan wrote: >> >>From: Sharat Masetty >> >> >> >>The last level system cache can be partitioned to 32 different >> >>slices of which GPU has two slices preallocated. One slice is >> >>used for caching GPU buffers and the other slice is used for >> >>caching the GPU SMMU pagetables. This talks to the core system >> >>cache driver to acquire the slice handles, configure the SCID's >> >>to those slices and activates and deactivates the slices upon >> >>GPU power collapse and restore. >> >> >> >>Some support from the IOMMU driver is also needed to make use >> >>of the system cache to set the right TCR attributes. GPU then >> >>has the ability to override a few cacheability parameters which >> >>it does to override write-allocate to write-no-allocate as the >> >>GPU hardware does not benefit much from it. >> >> >> >>DOMAIN_ATTR_SYS_CACHE is another domain level attribute used by the >> >>IOMMU driver to set the right attributes to cache the hardware >> >>pagetables into the system cache. >> >> >> >>Signed-off-by: Sharat Masetty >> >>[saiprakash.ranjan: fix to set attr before device attach to iommu and >> >>rebase] >> >>Signed-off-by: Sai Prakash Ranjan >> >>--- >> >> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 83 +++++++++++++++++++++++++ >> >> drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 4 ++ >> >> drivers/gpu/drm/msm/adreno/adreno_gpu.c | 17 +++++ >> >> 3 files changed, 104 insertions(+) >> >> >> >>diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >> >>b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >> >>index 8915882e4444..151190ff62f7 100644 >> >>--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >> >>+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >> >>@@ -8,7 +8,9 @@ >> >> #include "a6xx_gpu.h" >> >> #include "a6xx_gmu.xml.h" >> >> >> >>+#include >> >> #include >> >>+#include >> >> >> >> #define GPU_PAS_ID 13 >> >> >> >>@@ -1022,6 +1024,79 @@ static irqreturn_t a6xx_irq(struct msm_gpu *gpu) >> >> return IRQ_HANDLED; >> >> } >> >> >> >>+static void a6xx_llc_rmw(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 mask, >> >>u32 or) >> >>+{ >> >>+ return msm_rmw(a6xx_gpu->llc_mmio + (reg << 2), mask, or); >> >>+} >> >>+ >> >>+static void a6xx_llc_write(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 >> >>value) >> >>+{ >> >>+ return msm_writel(value, a6xx_gpu->llc_mmio + (reg << 2)); >> >>+} >> >>+ >> >>+static void a6xx_llc_deactivate(struct a6xx_gpu *a6xx_gpu) >> >>+{ >> >>+ llcc_slice_deactivate(a6xx_gpu->llc_slice); >> >>+ llcc_slice_deactivate(a6xx_gpu->htw_llc_slice); >> >>+} >> >>+ >> >>+static void a6xx_llc_activate(struct a6xx_gpu *a6xx_gpu) >> >>+{ >> >>+ u32 cntl1_regval = 0; >> >>+ >> >>+ if (IS_ERR(a6xx_gpu->llc_mmio)) >> >>+ return; >> >>+ >> >>+ if (!llcc_slice_activate(a6xx_gpu->llc_slice)) { >> >>+ u32 gpu_scid = llcc_get_slice_id(a6xx_gpu->llc_slice); >> >>+ >> >>+ gpu_scid &= 0x1f; >> >>+ cntl1_regval = (gpu_scid << 0) | (gpu_scid << 5) | (gpu_scid << 10) | >> >>+ (gpu_scid << 15) | (gpu_scid << 20); >> >>+ } >> >>+ >> >>+ if (!llcc_slice_activate(a6xx_gpu->htw_llc_slice)) { >> >>+ u32 gpuhtw_scid = llcc_get_slice_id(a6xx_gpu->htw_llc_slice); >> >>+ >> >>+ gpuhtw_scid &= 0x1f; >> >>+ cntl1_regval |= FIELD_PREP(GENMASK(29, 25), gpuhtw_scid); >> >>+ } >> >>+ >> >>+ if (cntl1_regval) { >> >>+ /* >> >>+ * Program the slice IDs for the various GPU blocks and GPU MMU >> >>+ * pagetables >> >>+ */ >> >>+ a6xx_llc_write(a6xx_gpu, REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1, >> >>cntl1_regval); >> >>+ >> >>+ /* >> >>+ * Program cacheability overrides to not allocate cache lines on >> >>+ * a write miss >> >>+ */ >> >>+ a6xx_llc_rmw(a6xx_gpu, REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0, 0xF, >> >>0x03); >> >>+ } >> >>+} >> > >> >This code has been around long enough that it pre-dates a650. On a650 and >> >other >> >MMU-500 targets the htw_llc is configured by the firmware and the >> >llc_slice is >> >configured in a different register. >> > >> >I don't think we need to pause everything and add support for the MMU-500 >> >path, >> >but we do need a way to disallow LLCC on affected targets until such time >> >that >> >we can get it fixed up. >> > >> >> Thanks for taking a close look, does something like below look ok or >> something >> else is needed here? >> >> + /* Till the time we get in LLCC support for A650 */ >> + if (!(info && info->revn == 650)) >> + a6xx_llc_slices_init(pdev, a6xx_gpu); > > It doesn't look like Rob picked this up for 5.10, so we have some time > to do it > right. Would you like me to give you an add-on patch for mmu-500 > targets? > Yes that will be great. Thanks, Sai -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel