From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.3 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AEF1DC433EF for ; Wed, 22 Sep 2021 08:11:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9251B610D1 for ; Wed, 22 Sep 2021 08:11:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233680AbhIVINL (ORCPT ); Wed, 22 Sep 2021 04:13:11 -0400 Received: from foss.arm.com ([217.140.110.172]:44702 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233699AbhIVINJ (ORCPT ); Wed, 22 Sep 2021 04:13:09 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CB52011B3; Wed, 22 Sep 2021 01:11:39 -0700 (PDT) Received: from [10.57.95.67] (unknown [10.57.95.67]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id CB4F93F719; Wed, 22 Sep 2021 01:11:37 -0700 (PDT) Subject: Re: [PATCH v2 10/17] arm64: Enable workaround for TRBE overwrite in FILL mode To: Anshuman Khandual , linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, maz@kernel.org, catalin.marinas@arm.com, mark.rutland@arm.com, james.morse@arm.com, leo.yan@linaro.org, mike.leach@linaro.org, mathieu.poirier@linaro.org, will@kernel.org, lcherian@marvell.com, coresight@lists.linaro.org References: <20210921134121.2423546-1-suzuki.poulose@arm.com> <20210921134121.2423546-11-suzuki.poulose@arm.com> <8b23470b-da5c-c624-dc98-d30ab7c1be5d@arm.com> From: Suzuki K Poulose Message-ID: <4bc00aff-0562-bafd-b31a-d7f9af6651fa@arm.com> Date: Wed, 22 Sep 2021 09:11:36 +0100 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:78.0) Gecko/20100101 Thunderbird/78.14.0 MIME-Version: 1.0 In-Reply-To: <8b23470b-da5c-c624-dc98-d30ab7c1be5d@arm.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 22/09/2021 08:23, Anshuman Khandual wrote: > > > On 9/21/21 7:11 PM, Suzuki K Poulose wrote: >> Now that we have the work around implmented in the TRBE >> driver, add the Kconfig entries and document the errata. >> >> Cc: Mark Rutland >> Cc: Will Deacon >> Cc: Catalin Marinas >> Cc: Anshuman Khandual >> Cc: Mathieu Poirier >> Cc: Mike Leach >> Cc: Leo Yan >> Signed-off-by: Suzuki K Poulose >> --- >> Documentation/arm64/silicon-errata.rst | 4 +++ >> arch/arm64/Kconfig | 39 ++++++++++++++++++++++++++ >> 2 files changed, 43 insertions(+) >> >> diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst >> index d410a47ffa57..2f99229d993c 100644 >> --- a/Documentation/arm64/silicon-errata.rst >> +++ b/Documentation/arm64/silicon-errata.rst >> @@ -92,12 +92,16 @@ stable kernels. >> +----------------+-----------------+-----------------+-----------------------------+ >> | ARM | Cortex-A77 | #1508412 | ARM64_ERRATUM_1508412 | >> +----------------+-----------------+-----------------+-----------------------------+ >> +| ARM | Cortex-A710 | #2119858 | ARM64_ERRATUM_2119858 | >> ++----------------+-----------------+-----------------+-----------------------------+ >> | ARM | Neoverse-N1 | #1188873,1418040| ARM64_ERRATUM_1418040 | >> +----------------+-----------------+-----------------+-----------------------------+ >> | ARM | Neoverse-N1 | #1349291 | N/A | >> +----------------+-----------------+-----------------+-----------------------------+ >> | ARM | Neoverse-N1 | #1542419 | ARM64_ERRATUM_1542419 | >> +----------------+-----------------+-----------------+-----------------------------+ >> +| ARM | Neoverse-N2 | #2139208 | ARM64_ERRATUM_2139208 | >> ++----------------+-----------------+-----------------+-----------------------------+ >> | ARM | MMU-500 | #841119,826419 | N/A | >> +----------------+-----------------+-----------------+-----------------------------+ >> +----------------+-----------------+-----------------+-----------------------------+ >> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig >> index 077f2ec4eeb2..eac4030322df 100644 >> --- a/arch/arm64/Kconfig >> +++ b/arch/arm64/Kconfig >> @@ -666,6 +666,45 @@ config ARM64_ERRATUM_1508412 >> >> If unsure, say Y. >> >> +config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE >> + bool >> + >> +config ARM64_ERRATUM_2119858 >> + bool "Cortex-A710: 2119858: workaround TRBE overwriting trace data in FILL mode" >> + default y >> + depends on CORESIGHT_TRBE >> + select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE >> + help >> + This option adds the workaround for ARM Cortex-A710 erratum 2119858. >> + >> + Affected Cortex-A710 cores could overwrite upto 3 cache lines of trace >> + data at the base of the buffer (ponited by TRBASER_EL1) in FILL mode in >> + the event of a WRAP event. >> + >> + Work around the issue by always making sure we move the TRBPTR_EL1 by >> + 256bytes before enabling the buffer and filling the first 256bytes of >> + the buffer with ETM ignore packets upon disabling. >> + >> + If unsure, say Y. >> + >> +config ARM64_ERRATUM_2139208 >> + bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode" >> + default y >> + depends on CORESIGHT_TRBE >> + select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE >> + help >> + This option adds the workaround for ARM Neoverse-N2 erratum 2139208. >> + >> + Affected Neoverse-N2 cores could overwrite upto 3 cache lines of trace >> + data at the base of the buffer (ponited by TRBASER_EL1) in FILL mode in > > s/ponited/pointed > >> + the event of a WRAP event. >> + >> + Work around the issue by always making sure we move the TRBPTR_EL1 by >> + 256bytes before enabling the buffer and filling the first 256bytes of >> + the buffer with ETM ignore packets upon disabling. >> + >> + If unsure, say Y. >> + >> config CAVIUM_ERRATUM_22375 >> bool "Cavium erratum 22375, 24313" >> default y >> > > The real errata problem description for both these erratums are exactly > the same. Rather a more generalized description should be included for > the ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE, which abstracts out the > problem and a corresponding solution that is implemented in the driver. > This should also help us reduce current redundancy. > The issue is what a user wants to see. A user who wants to configure the kernel specifically for a given CPU (think embedded systems), they would want to hand pick the errata for the particular CPU. So, moving the help text to an implicitly selected Kconfig symbol. I would rather keep this as it is to keep it user friendly. This doesn't affect the code size anyways. The other option is to remove all the CPU specific Kconfig symbols and update the "title" to reflect both the CPU/erratum numbers. Kind regards Suzuki From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 93AA3C433EF for ; Wed, 22 Sep 2021 08:13:53 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5E4F46124A for ; Wed, 22 Sep 2021 08:13:53 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 5E4F46124A Authentication-Results: mail.kernel.org; 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Wed, 22 Sep 2021 08:11:45 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mSxLx-007PrX-0R for linux-arm-kernel@lists.infradead.org; Wed, 22 Sep 2021 08:11:42 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CB52011B3; Wed, 22 Sep 2021 01:11:39 -0700 (PDT) Received: from [10.57.95.67] (unknown [10.57.95.67]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id CB4F93F719; Wed, 22 Sep 2021 01:11:37 -0700 (PDT) Subject: Re: [PATCH v2 10/17] arm64: Enable workaround for TRBE overwrite in FILL mode To: Anshuman Khandual , linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, maz@kernel.org, catalin.marinas@arm.com, mark.rutland@arm.com, james.morse@arm.com, leo.yan@linaro.org, mike.leach@linaro.org, mathieu.poirier@linaro.org, will@kernel.org, lcherian@marvell.com, coresight@lists.linaro.org References: <20210921134121.2423546-1-suzuki.poulose@arm.com> <20210921134121.2423546-11-suzuki.poulose@arm.com> <8b23470b-da5c-c624-dc98-d30ab7c1be5d@arm.com> From: Suzuki K Poulose Message-ID: <4bc00aff-0562-bafd-b31a-d7f9af6651fa@arm.com> Date: Wed, 22 Sep 2021 09:11:36 +0100 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:78.0) Gecko/20100101 Thunderbird/78.14.0 MIME-Version: 1.0 In-Reply-To: <8b23470b-da5c-c624-dc98-d30ab7c1be5d@arm.com> Content-Language: en-GB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210922_011141_208210_DF1015A7 X-CRM114-Status: GOOD ( 25.98 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 22/09/2021 08:23, Anshuman Khandual wrote: > > > On 9/21/21 7:11 PM, Suzuki K Poulose wrote: >> Now that we have the work around implmented in the TRBE >> driver, add the Kconfig entries and document the errata. >> >> Cc: Mark Rutland >> Cc: Will Deacon >> Cc: Catalin Marinas >> Cc: Anshuman Khandual >> Cc: Mathieu Poirier >> Cc: Mike Leach >> Cc: Leo Yan >> Signed-off-by: Suzuki K Poulose >> --- >> Documentation/arm64/silicon-errata.rst | 4 +++ >> arch/arm64/Kconfig | 39 ++++++++++++++++++++++++++ >> 2 files changed, 43 insertions(+) >> >> diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst >> index d410a47ffa57..2f99229d993c 100644 >> --- a/Documentation/arm64/silicon-errata.rst >> +++ b/Documentation/arm64/silicon-errata.rst >> @@ -92,12 +92,16 @@ stable kernels. >> +----------------+-----------------+-----------------+-----------------------------+ >> | ARM | Cortex-A77 | #1508412 | ARM64_ERRATUM_1508412 | >> +----------------+-----------------+-----------------+-----------------------------+ >> +| ARM | Cortex-A710 | #2119858 | ARM64_ERRATUM_2119858 | >> ++----------------+-----------------+-----------------+-----------------------------+ >> | ARM | Neoverse-N1 | #1188873,1418040| ARM64_ERRATUM_1418040 | >> +----------------+-----------------+-----------------+-----------------------------+ >> | ARM | Neoverse-N1 | #1349291 | N/A | >> +----------------+-----------------+-----------------+-----------------------------+ >> | ARM | Neoverse-N1 | #1542419 | ARM64_ERRATUM_1542419 | >> +----------------+-----------------+-----------------+-----------------------------+ >> +| ARM | Neoverse-N2 | #2139208 | ARM64_ERRATUM_2139208 | >> ++----------------+-----------------+-----------------+-----------------------------+ >> | ARM | MMU-500 | #841119,826419 | N/A | >> +----------------+-----------------+-----------------+-----------------------------+ >> +----------------+-----------------+-----------------+-----------------------------+ >> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig >> index 077f2ec4eeb2..eac4030322df 100644 >> --- a/arch/arm64/Kconfig >> +++ b/arch/arm64/Kconfig >> @@ -666,6 +666,45 @@ config ARM64_ERRATUM_1508412 >> >> If unsure, say Y. >> >> +config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE >> + bool >> + >> +config ARM64_ERRATUM_2119858 >> + bool "Cortex-A710: 2119858: workaround TRBE overwriting trace data in FILL mode" >> + default y >> + depends on CORESIGHT_TRBE >> + select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE >> + help >> + This option adds the workaround for ARM Cortex-A710 erratum 2119858. >> + >> + Affected Cortex-A710 cores could overwrite upto 3 cache lines of trace >> + data at the base of the buffer (ponited by TRBASER_EL1) in FILL mode in >> + the event of a WRAP event. >> + >> + Work around the issue by always making sure we move the TRBPTR_EL1 by >> + 256bytes before enabling the buffer and filling the first 256bytes of >> + the buffer with ETM ignore packets upon disabling. >> + >> + If unsure, say Y. >> + >> +config ARM64_ERRATUM_2139208 >> + bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode" >> + default y >> + depends on CORESIGHT_TRBE >> + select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE >> + help >> + This option adds the workaround for ARM Neoverse-N2 erratum 2139208. >> + >> + Affected Neoverse-N2 cores could overwrite upto 3 cache lines of trace >> + data at the base of the buffer (ponited by TRBASER_EL1) in FILL mode in > > s/ponited/pointed > >> + the event of a WRAP event. >> + >> + Work around the issue by always making sure we move the TRBPTR_EL1 by >> + 256bytes before enabling the buffer and filling the first 256bytes of >> + the buffer with ETM ignore packets upon disabling. >> + >> + If unsure, say Y. >> + >> config CAVIUM_ERRATUM_22375 >> bool "Cavium erratum 22375, 24313" >> default y >> > > The real errata problem description for both these erratums are exactly > the same. Rather a more generalized description should be included for > the ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE, which abstracts out the > problem and a corresponding solution that is implemented in the driver. > This should also help us reduce current redundancy. > The issue is what a user wants to see. A user who wants to configure the kernel specifically for a given CPU (think embedded systems), they would want to hand pick the errata for the particular CPU. So, moving the help text to an implicitly selected Kconfig symbol. I would rather keep this as it is to keep it user friendly. This doesn't affect the code size anyways. The other option is to remove all the CPU specific Kconfig symbols and update the "title" to reflect both the CPU/erratum numbers. Kind regards Suzuki _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel