From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.6 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A, SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0DD0C47087 for ; Fri, 28 May 2021 12:20:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A468C611BD for ; Fri, 28 May 2021 12:20:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230311AbhE1MWZ (ORCPT ); Fri, 28 May 2021 08:22:25 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:43578 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229552AbhE1MWX (ORCPT ); Fri, 28 May 2021 08:22:23 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 14SCKfmN113803; Fri, 28 May 2021 07:20:41 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1622204441; bh=hSdtd7Nnuj7pADYTIP5NDzdYete/9105ZRrFC0OjwZE=; h=Subject:To:CC:References:From:Date:In-Reply-To; b=Obh7syRKFtpMuRUJlVEvxKh0GBYhU7IVQkhBvUvUpOPM7RaUrL5CAA/kuzVkNeUhp U6yg3madsJ/muELsNvUuL386XF6ablALgh5vyQyESNGY+t/DyxULsUs7U66Wr8bSrN 9FClMNzgKkDapO3DwCOie5yYrU/RvbwBNCsvlg1U= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 14SCKfTb024679 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 28 May 2021 07:20:41 -0500 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Fri, 28 May 2021 07:20:41 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Fri, 28 May 2021 07:20:41 -0500 Received: from [10.250.35.153] (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 14SCKe8P025150; Fri, 28 May 2021 07:20:40 -0500 Subject: Re: [PATCH 1/2] arm64: dts: ti: k3-am65-main: Add ICSSG MDIO nodes To: Jan Kiszka , Nishanth Menon CC: Grygorii Strashko , Vignesh Raghavendra , Kishon Vijay Abraham I , Lokesh Vutla , Grzegorz Jaszczyk , , References: <20210514224759.9987-1-s-anna@ti.com> <20210514224759.9987-2-s-anna@ti.com> <00fbd9c1-ed43-822c-06bf-9642b5c03568@siemens.com> From: Suman Anna Message-ID: <4c429512-77c5-59f7-ac1d-9f6a51c693ab@ti.com> Date: Fri, 28 May 2021 07:20:40 -0500 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <00fbd9c1-ed43-822c-06bf-9642b5c03568@siemens.com> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 5/28/21 12:22 AM, Jan Kiszka wrote: > On 28.05.21 07:09, Jan Kiszka wrote: >> On 15.05.21 00:47, Suman Anna wrote: >>> From: Roger Quadros >>> >>> The ICSSGs on K3 AM65x SoCs contain an MDIO controller that can >>> be used to control external PHYs associated with the Industrial >>> Ethernet peripherals within each ICSSG instance. The MDIO module >>> used within the ICSSG is similar to the MDIO Controller used >>> in TI Davinci SoCs. A bus frequency of 1 MHz is chosen for the >>> MDIO operations. >>> >>> The nodes are added and enabled in the common k3-am65-main.dtsi >>> file by default, and disabled in the existing AM65 board dts >>> files. These nodes need pinctrl lines, and so should be enabled >>> only on boards where they are actually wired and pinned out for >>> ICSSG Ethernet. Any new board dts file should disable these if >>> they are not sure. >>> >>> Signed-off-by: Roger Quadros >>> [s-anna@ti.com: move the disabled status to board dts files] >>> Signed-off-by: Suman Anna >>> --- >>> .../boot/dts/ti/k3-am65-iot2050-common.dtsi | 12 ++++++++ >>> arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 30 +++++++++++++++++++ >>> .../arm64/boot/dts/ti/k3-am654-base-board.dts | 12 ++++++++ >>> 3 files changed, 54 insertions(+) >>> >>> diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi >>> index de763ca9251c..63140eaba524 100644 >>> --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi >>> +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi >>> @@ -653,3 +653,15 @@ &pcie1_rc { >>> &pcie1_ep { >>> status = "disabled"; >>> }; >>> + >>> +&icssg0_mdio { >>> + status = "disabled"; >>> +}; >>> + >>> +&icssg1_mdio { >>> + status = "disabled"; >>> +}; >>> + >>> +&icssg2_mdio { >>> + status = "disabled"; >>> +}; >> >> We will need this here for PRU networking. What would be the impact of >> leaving it enabled already at this stage? >> > > Ah, now reading our backlog completely - there will be more coming in to > this file than not disabling icssg mdio (and that only for mdio0). So: Yeah, these will be enabled when the corresponding pinctrl pins are added, so will come alongside the icssg ethernet nodes in the future. > > Acked-by: Jan Kiszka > > Jan > > PS: How far are we away from icssg-prueth? The last missing pieces from PRUSS foundation point of view are the PRUSS consumer API series, which need next versions to be posted upstream. I would say still couple of merge windows. regards Suman From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.6 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9350DC4708C for ; Fri, 28 May 2021 12:27:27 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4EAA9610FA for ; Fri, 28 May 2021 12:27:27 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4EAA9610FA Authentication-Results: mail.kernel.org; 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Fri, 28 May 2021 07:20:41 -0500 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Fri, 28 May 2021 07:20:41 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Fri, 28 May 2021 07:20:41 -0500 Received: from [10.250.35.153] (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 14SCKe8P025150; Fri, 28 May 2021 07:20:40 -0500 Subject: Re: [PATCH 1/2] arm64: dts: ti: k3-am65-main: Add ICSSG MDIO nodes To: Jan Kiszka , Nishanth Menon CC: Grygorii Strashko , Vignesh Raghavendra , Kishon Vijay Abraham I , Lokesh Vutla , Grzegorz Jaszczyk , , References: <20210514224759.9987-1-s-anna@ti.com> <20210514224759.9987-2-s-anna@ti.com> <00fbd9c1-ed43-822c-06bf-9642b5c03568@siemens.com> From: Suman Anna Message-ID: <4c429512-77c5-59f7-ac1d-9f6a51c693ab@ti.com> Date: Fri, 28 May 2021 07:20:40 -0500 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <00fbd9c1-ed43-822c-06bf-9642b5c03568@siemens.com> Content-Language: en-US X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210528_052043_448372_35F537C6 X-CRM114-Status: GOOD ( 18.50 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 5/28/21 12:22 AM, Jan Kiszka wrote: > On 28.05.21 07:09, Jan Kiszka wrote: >> On 15.05.21 00:47, Suman Anna wrote: >>> From: Roger Quadros >>> >>> The ICSSGs on K3 AM65x SoCs contain an MDIO controller that can >>> be used to control external PHYs associated with the Industrial >>> Ethernet peripherals within each ICSSG instance. The MDIO module >>> used within the ICSSG is similar to the MDIO Controller used >>> in TI Davinci SoCs. A bus frequency of 1 MHz is chosen for the >>> MDIO operations. >>> >>> The nodes are added and enabled in the common k3-am65-main.dtsi >>> file by default, and disabled in the existing AM65 board dts >>> files. These nodes need pinctrl lines, and so should be enabled >>> only on boards where they are actually wired and pinned out for >>> ICSSG Ethernet. Any new board dts file should disable these if >>> they are not sure. >>> >>> Signed-off-by: Roger Quadros >>> [s-anna@ti.com: move the disabled status to board dts files] >>> Signed-off-by: Suman Anna >>> --- >>> .../boot/dts/ti/k3-am65-iot2050-common.dtsi | 12 ++++++++ >>> arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 30 +++++++++++++++++++ >>> .../arm64/boot/dts/ti/k3-am654-base-board.dts | 12 ++++++++ >>> 3 files changed, 54 insertions(+) >>> >>> diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi >>> index de763ca9251c..63140eaba524 100644 >>> --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi >>> +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi >>> @@ -653,3 +653,15 @@ &pcie1_rc { >>> &pcie1_ep { >>> status = "disabled"; >>> }; >>> + >>> +&icssg0_mdio { >>> + status = "disabled"; >>> +}; >>> + >>> +&icssg1_mdio { >>> + status = "disabled"; >>> +}; >>> + >>> +&icssg2_mdio { >>> + status = "disabled"; >>> +}; >> >> We will need this here for PRU networking. What would be the impact of >> leaving it enabled already at this stage? >> > > Ah, now reading our backlog completely - there will be more coming in to > this file than not disabling icssg mdio (and that only for mdio0). So: Yeah, these will be enabled when the corresponding pinctrl pins are added, so will come alongside the icssg ethernet nodes in the future. > > Acked-by: Jan Kiszka > > Jan > > PS: How far are we away from icssg-prueth? The last missing pieces from PRUSS foundation point of view are the PRUSS consumer API series, which need next versions to be posted upstream. I would say still couple of merge windows. regards Suman _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel