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Wed, 19 Aug 2020 01:47:01 +0000 From: "Almahallawy, Khaled" To: "Navare, Manasi D" Subject: Re: [PATCH v2 2/2] drm/i915/dp: TPS4 PHY test pattern compliance support Thread-Topic: [PATCH v2 2/2] drm/i915/dp: TPS4 PHY test pattern compliance support Thread-Index: AQHWYIlZJYRPjqtGJ0ehh+C5crW4yqk+jCoAgABIBQA= Date: Wed, 19 Aug 2020 01:47:01 +0000 Message-ID: <4c7022eba9c664e0c9597acfc4ba363434546be0.camel@intel.com> References: <20200723003627.31198-1-khaled.almahallawy@intel.com> <20200723003627.31198-2-khaled.almahallawy@intel.com> <20200818212908.GA4908@labuser-Z97X-UD5H> In-Reply-To: <20200818212908.GA4908@labuser-Z97X-UD5H> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=none action=none header.from=intel.com; x-originating-ip: [134.134.137.73] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 92899f58-d54e-4838-bead-08d843e1c4a9 x-ms-traffictypediagnostic: MW3PR11MB4620: x-ld-processed: 46c98d88-e344-4ed4-8496-4ed7712e255d,ExtAddr x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:6430; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Tue, 2020-08-18 at 14:29 -0700, Navare, Manasi wrote: > On Wed, Jul 22, 2020 at 05:36:27PM -0700, Khaled Almahallawy wrote: > > Adding support for TPS4 (CP2520 Pattern 3) PHY pattern source > > tests. > > > > v2: uniform bit names TP4a/b/c (Manasi) > > > > Signed-off-by: Khaled Almahallawy > > Looks good to me, > > Reviewed-by: Manasi Navare > > Khaled, could you also give a tested by here? > > Manasi Passed all TPS4 tests on DP Compliance scope with DPoC1.4a test specification Tested-by: Khaled Almahallawy > > > --- > > drivers/gpu/drm/i915/display/intel_dp.c | 14 ++++++++++++-- > > drivers/gpu/drm/i915/i915_reg.h | 4 ++++ > > 2 files changed, 16 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > > b/drivers/gpu/drm/i915/display/intel_dp.c > > index d6295eb20b63..4b74b2ec5665 100644 > > --- a/drivers/gpu/drm/i915/display/intel_dp.c > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > > @@ -5371,7 +5371,7 @@ static void > > intel_dp_phy_pattern_update(struct intel_dp *intel_dp) > > &intel_dp->compliance.test_data.phytest; > > struct intel_crtc *crtc = to_intel_crtc(dig_port- > > >base.base.crtc); > > enum pipe pipe = crtc->pipe; > > - u32 pattern_val; > > + u32 pattern_val, dp_tp_ctl; > > > > switch (data->phy_pattern) { > > case DP_PHY_TEST_PATTERN_NONE: > > @@ -5411,7 +5411,7 @@ static void > > intel_dp_phy_pattern_update(struct intel_dp *intel_dp) > > DDI_DP_COMP_CTL_ENABLE | > > DDI_DP_COMP_CTL_CUSTOM80); > > break; > > - case DP_PHY_TEST_PATTERN_CP2520: > > + case DP_PHY_TEST_PATTERN_CP2520_PAT1: > > /* > > * FIXME: Ideally pattern should come from DPCD 0x24A. > > As > > * current firmware of DPR-100 could not set it, so > > hardcoding > > @@ -5423,6 +5423,16 @@ static void > > intel_dp_phy_pattern_update(struct intel_dp *intel_dp) > > DDI_DP_COMP_CTL_ENABLE | > > DDI_DP_COMP_CTL_HBR2 | > > pattern_val); > > break; > > + case DP_PHY_TEST_PATTERN_CP2520_PAT3: > > + DRM_DEBUG_KMS("Set TPS4 Phy Test Pattern\n"); > > + intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), > > 0x0); > > + dp_tp_ctl = intel_de_read(dev_priv, > > TGL_DP_TP_CTL(pipe)); > > + dp_tp_ctl &= ~DP_TP_CTL_TRAIN_PAT4_SEL_MASK; > > + dp_tp_ctl |= DP_TP_CTL_TRAIN_PAT4_SEL_TP4a; > > + dp_tp_ctl &= ~DP_TP_CTL_LINK_TRAIN_MASK; > > + dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT4; > > + intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), > > dp_tp_ctl); > > + break; > > default: > > WARN(1, "Invalid Phy Test Pattern\n"); > > } > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > > b/drivers/gpu/drm/i915/i915_reg.h > > index a0d31f3bf634..c586595b9e76 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -9982,6 +9982,10 @@ enum skl_power_gate { > > #define DP_TP_CTL_MODE_SST (0 << 27) > > #define DP_TP_CTL_MODE_MST (1 << 27) > > #define DP_TP_CTL_FORCE_ACT (1 << 25) > > +#define DP_TP_CTL_TRAIN_PAT4_SEL_MASK (3 << 19) > > +#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4a (0 << 19) > > +#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4b (1 << 19) > > +#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4c (2 << 19) > > #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1 << 18) > > #define DP_TP_CTL_FDI_AUTOTRAIN (1 << 15) > > #define DP_TP_CTL_LINK_TRAIN_MASK (7 << 8) > > -- > > 2.17.1 > > _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 57632C433DF for ; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Tue, 2020-08-18 at 14:29 -0700, Navare, Manasi wrote: > On Wed, Jul 22, 2020 at 05:36:27PM -0700, Khaled Almahallawy wrote: > > Adding support for TPS4 (CP2520 Pattern 3) PHY pattern source > > tests. > > > > v2: uniform bit names TP4a/b/c (Manasi) > > > > Signed-off-by: Khaled Almahallawy > > Looks good to me, > > Reviewed-by: Manasi Navare > > Khaled, could you also give a tested by here? > > Manasi Passed all TPS4 tests on DP Compliance scope with DPoC1.4a test specification Tested-by: Khaled Almahallawy > > > --- > > drivers/gpu/drm/i915/display/intel_dp.c | 14 ++++++++++++-- > > drivers/gpu/drm/i915/i915_reg.h | 4 ++++ > > 2 files changed, 16 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > > b/drivers/gpu/drm/i915/display/intel_dp.c > > index d6295eb20b63..4b74b2ec5665 100644 > > --- a/drivers/gpu/drm/i915/display/intel_dp.c > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > > @@ -5371,7 +5371,7 @@ static void > > intel_dp_phy_pattern_update(struct intel_dp *intel_dp) > > &intel_dp->compliance.test_data.phytest; > > struct intel_crtc *crtc = to_intel_crtc(dig_port- > > >base.base.crtc); > > enum pipe pipe = crtc->pipe; > > - u32 pattern_val; > > + u32 pattern_val, dp_tp_ctl; > > > > switch (data->phy_pattern) { > > case DP_PHY_TEST_PATTERN_NONE: > > @@ -5411,7 +5411,7 @@ static void > > intel_dp_phy_pattern_update(struct intel_dp *intel_dp) > > DDI_DP_COMP_CTL_ENABLE | > > DDI_DP_COMP_CTL_CUSTOM80); > > break; > > - case DP_PHY_TEST_PATTERN_CP2520: > > + case DP_PHY_TEST_PATTERN_CP2520_PAT1: > > /* > > * FIXME: Ideally pattern should come from DPCD 0x24A. > > As > > * current firmware of DPR-100 could not set it, so > > hardcoding > > @@ -5423,6 +5423,16 @@ static void > > intel_dp_phy_pattern_update(struct intel_dp *intel_dp) > > DDI_DP_COMP_CTL_ENABLE | > > DDI_DP_COMP_CTL_HBR2 | > > pattern_val); > > break; > > + case DP_PHY_TEST_PATTERN_CP2520_PAT3: > > + DRM_DEBUG_KMS("Set TPS4 Phy Test Pattern\n"); > > + intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), > > 0x0); > > + dp_tp_ctl = intel_de_read(dev_priv, > > TGL_DP_TP_CTL(pipe)); > > + dp_tp_ctl &= ~DP_TP_CTL_TRAIN_PAT4_SEL_MASK; > > + dp_tp_ctl |= DP_TP_CTL_TRAIN_PAT4_SEL_TP4a; > > + dp_tp_ctl &= ~DP_TP_CTL_LINK_TRAIN_MASK; > > + dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT4; > > + intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), > > dp_tp_ctl); > > + break; > > default: > > WARN(1, "Invalid Phy Test Pattern\n"); > > } > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > > b/drivers/gpu/drm/i915/i915_reg.h > > index a0d31f3bf634..c586595b9e76 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -9982,6 +9982,10 @@ enum skl_power_gate { > > #define DP_TP_CTL_MODE_SST (0 << 27) > > #define DP_TP_CTL_MODE_MST (1 << 27) > > #define DP_TP_CTL_FORCE_ACT (1 << 25) > > +#define DP_TP_CTL_TRAIN_PAT4_SEL_MASK (3 << 19) > > +#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4a (0 << 19) > > +#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4b (1 << 19) > > +#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4c (2 << 19) > > #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1 << 18) > > #define DP_TP_CTL_FDI_AUTOTRAIN (1 << 15) > > #define DP_TP_CTL_LINK_TRAIN_MASK (7 << 8) > > -- > > 2.17.1 > > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx