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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id d6sm611060pjh.24.2021.01.11.16.13.31 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 11 Jan 2021 16:13:32 -0800 (PST) Subject: Re: [PATCH 16/18] target/arm: add ARMv8.4-SEL2 extension To: remi.denis.courmont@huawei.com, qemu-arm@nongnu.org References: <3337797.iIbC2pHGDl@basile.remlab.net> <20201218103759.19929-16-remi.denis.courmont@huawei.com> From: Richard Henderson Message-ID: <4e32ca89-51aa-85d1-0a8f-e9aa7e037be4@linaro.org> Date: Mon, 11 Jan 2021 14:13:29 -1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20201218103759.19929-16-remi.denis.courmont@huawei.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 12/18/20 12:37 AM, remi.denis.courmont@huawei.com wrote: > @@ -3297,7 +3301,7 @@ typedef ARMCPU ArchCPU; > * We put flags which are shared between 32 and 64 bit mode at the top > * of the word, and flags which apply to only one mode at the bottom. > * > - * 31 20 18 14 9 0 > + * 31 20 19 14 9 0 > * +--------------+-----+-----+----------+--------------+ > * | | | TBFLAG_A32 | | > * | | +-----+----------+ TBFLAG_AM32 | > @@ -3346,6 +3350,7 @@ FIELD(TBFLAG_A32, HSTR_ACTIVE, 16, 1) > * the same thing as the current security state of the processor! > */ > FIELD(TBFLAG_A32, NS, 17, 1) > +FIELD(TBFLAG_A32, EEL2, 18, 1) Note that via other in-flight patch sets we have run out of bits here. I've rearranged them in https://patchew.org/QEMU/20210111190113.303726-1-richard.henderson@linaro.org/ This should be nothing but a minor confict to fix up. r~