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Fri, 12 Aug 2022 14:39:48 +0000 (GMT) Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 336CA4C064; Fri, 12 Aug 2022 14:39:48 +0000 (GMT) Received: from [9.101.4.17] (unknown [9.101.4.17]) by d06av22.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 12 Aug 2022 14:39:48 +0000 (GMT) Message-ID: <4eef0123-3a83-4e64-4e58-c4edabeecf2d@linux.ibm.com> Date: Fri, 12 Aug 2022 16:39:47 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.12.0 Subject: Re: [PATCH for-7.2 v4 02/11] ppc/pnv: add phb-id/chip-id PnvPHB4RootBus properties Content-Language: en-US To: Daniel Henrique Barboza , qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, clg@kaod.org References: <20220811163950.578927-1-danielhb413@gmail.com> <20220811163950.578927-3-danielhb413@gmail.com> From: Frederic Barrat In-Reply-To: <20220811163950.578927-3-danielhb413@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-TM-AS-GCONF: 00 X-Proofpoint-GUID: B2zMWpjMXdnu1JXwmJYRpdy_8jvmJg31 X-Proofpoint-ORIG-GUID: dkx-FqZRQkBoAa2eBVJNGfC6X_sjZFJP X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-12_09,2022-08-11_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 lowpriorityscore=0 suspectscore=0 phishscore=0 priorityscore=1501 malwarescore=0 adultscore=0 clxscore=1015 spamscore=0 mlxscore=0 mlxlogscore=973 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2207270000 definitions=main-2208120040 Received-SPF: pass client-ip=148.163.158.5; envelope-from=fbarrat@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 11/08/2022 18:39, Daniel Henrique Barboza wrote: > The same rationale provided in the PHB3 bus case applies here. > > Note: we could have merged both buses in a single object, like we did > with the root ports, and spare some boilerplate. The reason we opted to > preserve both buses objects is twofold: > > - there's not user side advantage in doing so. Unifying the root ports > presents a clear user QOL change when we enable user created devices back. > The buses objects, aside from having a different QOM name, is transparent > to the user; > > - we leave a door opened in case we want to increase the root port limit > for phb4/5 later on without having to deal with phb3 code. > > Reviewed-by: Cédric Le Goater > Signed-off-by: Daniel Henrique Barboza > --- Reviewed-by: Frederic Barrat Fred > hw/pci-host/pnv_phb4.c | 51 ++++++++++++++++++++++++++++++++++ > include/hw/pci-host/pnv_phb4.h | 10 +++++++ > 2 files changed, 61 insertions(+) > > diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c > index b98c394713..824e1a73fb 100644 > --- a/hw/pci-host/pnv_phb4.c > +++ b/hw/pci-host/pnv_phb4.c > @@ -1551,6 +1551,12 @@ void pnv_phb4_bus_init(DeviceState *dev, PnvPHB4 *phb) > pnv_phb4_set_irq, pnv_phb4_map_irq, phb, > &phb->pci_mmio, &phb->pci_io, > 0, 4, TYPE_PNV_PHB4_ROOT_BUS); > + > + object_property_set_int(OBJECT(pci->bus), "phb-id", phb->phb_id, > + &error_abort); > + object_property_set_int(OBJECT(pci->bus), "chip-id", phb->chip_id, > + &error_abort); > + > pci_setup_iommu(pci->bus, pnv_phb4_dma_iommu, phb); > pci->bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE; > } > @@ -1708,10 +1714,55 @@ static const TypeInfo pnv_phb5_type_info = { > .instance_size = sizeof(PnvPHB4), > }; > > +static void pnv_phb4_root_bus_get_prop(Object *obj, Visitor *v, > + const char *name, > + void *opaque, Error **errp) > +{ > + PnvPHB4RootBus *bus = PNV_PHB4_ROOT_BUS(obj); > + uint64_t value = 0; > + > + if (strcmp(name, "phb-id") == 0) { > + value = bus->phb_id; > + } else { > + value = bus->chip_id; > + } > + > + visit_type_size(v, name, &value, errp); > +} > + > +static void pnv_phb4_root_bus_set_prop(Object *obj, Visitor *v, > + const char *name, > + void *opaque, Error **errp) > + > +{ > + PnvPHB4RootBus *bus = PNV_PHB4_ROOT_BUS(obj); > + uint64_t value; > + > + if (!visit_type_size(v, name, &value, errp)) { > + return; > + } > + > + if (strcmp(name, "phb-id") == 0) { > + bus->phb_id = value; > + } else { > + bus->chip_id = value; > + } > +} > + > static void pnv_phb4_root_bus_class_init(ObjectClass *klass, void *data) > { > BusClass *k = BUS_CLASS(klass); > > + object_class_property_add(klass, "phb-id", "int", > + pnv_phb4_root_bus_get_prop, > + pnv_phb4_root_bus_set_prop, > + NULL, NULL); > + > + object_class_property_add(klass, "chip-id", "int", > + pnv_phb4_root_bus_get_prop, > + pnv_phb4_root_bus_set_prop, > + NULL, NULL); > + > /* > * PHB4 has only a single root complex. Enforce the limit on the > * parent bus > diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h > index 20aa4819d3..50d4faa001 100644 > --- a/include/hw/pci-host/pnv_phb4.h > +++ b/include/hw/pci-host/pnv_phb4.h > @@ -45,7 +45,17 @@ typedef struct PnvPhb4DMASpace { > QLIST_ENTRY(PnvPhb4DMASpace) list; > } PnvPhb4DMASpace; > > +/* > + * PHB4 PCIe Root Bus > + */ > #define TYPE_PNV_PHB4_ROOT_BUS "pnv-phb4-root" > +struct PnvPHB4RootBus { > + PCIBus parent; > + > + uint32_t chip_id; > + uint32_t phb_id; > +}; > +OBJECT_DECLARE_SIMPLE_TYPE(PnvPHB4RootBus, PNV_PHB4_ROOT_BUS) > > /* > * PHB4 PCIe Host Bridge for PowerNV machines (POWER9)