From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 60160C433F5 for ; Mon, 28 Mar 2022 10:41:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240325AbiC1KnT (ORCPT ); Mon, 28 Mar 2022 06:43:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47604 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240319AbiC1KnQ (ORCPT ); Mon, 28 Mar 2022 06:43:16 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id C896854FA5 for ; Mon, 28 Mar 2022 03:41:35 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7E45ED6E; Mon, 28 Mar 2022 03:41:35 -0700 (PDT) Received: from [10.57.40.97] (unknown [10.57.40.97]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 429C23F66F; Mon, 28 Mar 2022 03:41:34 -0700 (PDT) Message-ID: <4ef77445-b58d-a71a-0ddc-70e308ea99c8@arm.com> Date: Mon, 28 Mar 2022 11:41:48 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Subject: Re: [PATCH v3 00/15] Make ETM register accesses consistent with sysreg.h Content-Language: en-US To: Mathieu Poirier Cc: suzuki.poulose@arm.com, coresight@lists.linaro.org, mike.leach@linaro.org, anshuman.khandual@arm.com, leo.yan@linaro.com, Leo Yan , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20220304171913.2292458-1-james.clark@arm.com> <20220323162257.GC3248686@p14s> From: James Clark In-Reply-To: <20220323162257.GC3248686@p14s> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 23/03/2022 16:22, Mathieu Poirier wrote: > On Fri, Mar 04, 2022 at 05:18:57PM +0000, James Clark wrote: >> Changes since v2: >> * Implement Mike's suggestion of not having _SHIFT and using the existing >> FIELD_GET and FIELD_PREP methods. >> * Dropped the change to add the new REG_VAL macro because of the above. >> * FIELD_PREP could be used in some trivial cases, but in some cases the >> shift is still required but can be calculated with __bf_shf >> * Improved the commit messages. >> * The change is still binary equivalent, but requires an extra step >> mentioned at the end of this cover letter. >> >> Applies to coresight/next 3619ee28488 >> Also available at https://gitlab.arm.com/linux-arm/linux-jc/-/tree/james-cs-register-refactor-v3 >> >> To check for binary equivalence follow the same steps in the cover letter >> of v2, but apply the following change to coresight-priv.h. This is because >> the existing version of the macros wrap the expression in a new scope {} >> that flips something in the compiler: >> >> #undef FIELD_GET >> #define FIELD_GET(_mask, _reg) (((_reg) & (_mask)) >> __bf_shf(_mask)) >> #undef FIELD_PREP >> #define FIELD_PREP(_mask, _val) (((_val) << __bf_shf(_mask)) & (_mask)) >> >> Thanks >> James >> >> James Clark (15): >> coresight: etm4x: Cleanup TRCIDR0 register accesses >> coresight: etm4x: Cleanup TRCIDR2 register accesses >> coresight: etm4x: Cleanup TRCIDR3 register accesses >> coresight: etm4x: Cleanup TRCIDR4 register accesses >> coresight: etm4x: Cleanup TRCIDR5 register accesses >> coresight: etm4x: Cleanup TRCCONFIGR register accesses >> coresight: etm4x: Cleanup TRCEVENTCTL1R register accesses >> coresight: etm4x: Cleanup TRCSTALLCTLR register accesses >> coresight: etm4x: Cleanup TRCVICTLR register accesses >> coresight: etm3x: Cleanup ETMTECR1 register accesses >> coresight: etm4x: Cleanup TRCACATRn register accesses >> coresight: etm4x: Cleanup TRCSSCCRn and TRCSSCSRn register accesses >> coresight: etm4x: Cleanup TRCSSPCICRn register accesses >> coresight: etm4x: Cleanup TRCBBCTLR register accesses >> coresight: etm4x: Cleanup TRCRSCTLRn register accesses >> >> .../coresight/coresight-etm3x-core.c | 2 +- >> .../coresight/coresight-etm3x-sysfs.c | 2 +- >> .../coresight/coresight-etm4x-core.c | 136 +++++-------- >> .../coresight/coresight-etm4x-sysfs.c | 180 +++++++++--------- >> drivers/hwtracing/coresight/coresight-etm4x.h | 122 ++++++++++-- >> 5 files changed, 244 insertions(+), 198 deletions(-) > > I am done reviewing this set. I will wait until rc1 or rc2 before moving > forward. If there are other comments needing a respin then I will wait for the > next revision. Otherwise I will apply this one after correcting the extra lines > at the end of patch 15. > Thanks for the review! > Thanks, > Mathieu > >> >> -- >> 2.28.0 >> From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6410BC433F5 for ; Mon, 28 Mar 2022 10:42:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:From:References:Cc:To: Subject:MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=h+MHw8CYty04to2NifPjS4C1eg54gbV7/Mbj5qAjY2c=; b=b7FNj8/SVkQ5tD ImnkSlp68JpXc+pN3FfkXcr63hpjKfRRxyRhh8gN/hPiad7DYBtgRsErmeaxDIfZpSaUnCLQZwU2p QHkVYfKGrrjEsexHC8h+jBqrzUL5YrqPX/oBWBeYFuQTIdUnDugmwYa7J7B8YBAGab/Y2ZhLEci90 5k+Dp5pbc6prsKTqx6y/x/3/SNFBSMIssq8URfsCp5taPPSRMMXVLItGCnlu4eJRHttcZyE7JU9Cv 4E2JUiHGljZfymkIhO3aJRyp3lAW8DnsrrP/MUXQR0EtJpPQ/PoYxeLrYRpNR0yfAi6AhVBnYbt1r SZa/xcxA/cRvM/PEEiLA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nYmoe-008DrR-0M; Mon, 28 Mar 2022 10:41:40 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nYmoa-008Dqe-Pr for linux-arm-kernel@lists.infradead.org; Mon, 28 Mar 2022 10:41:38 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7E45ED6E; Mon, 28 Mar 2022 03:41:35 -0700 (PDT) Received: from [10.57.40.97] (unknown [10.57.40.97]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 429C23F66F; Mon, 28 Mar 2022 03:41:34 -0700 (PDT) Message-ID: <4ef77445-b58d-a71a-0ddc-70e308ea99c8@arm.com> Date: Mon, 28 Mar 2022 11:41:48 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Subject: Re: [PATCH v3 00/15] Make ETM register accesses consistent with sysreg.h Content-Language: en-US To: Mathieu Poirier Cc: suzuki.poulose@arm.com, coresight@lists.linaro.org, mike.leach@linaro.org, anshuman.khandual@arm.com, leo.yan@linaro.com, Leo Yan , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20220304171913.2292458-1-james.clark@arm.com> <20220323162257.GC3248686@p14s> From: James Clark In-Reply-To: <20220323162257.GC3248686@p14s> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220328_034136_973832_0DCDC4F1 X-CRM114-Status: GOOD ( 19.18 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 23/03/2022 16:22, Mathieu Poirier wrote: > On Fri, Mar 04, 2022 at 05:18:57PM +0000, James Clark wrote: >> Changes since v2: >> * Implement Mike's suggestion of not having _SHIFT and using the existing >> FIELD_GET and FIELD_PREP methods. >> * Dropped the change to add the new REG_VAL macro because of the above. >> * FIELD_PREP could be used in some trivial cases, but in some cases the >> shift is still required but can be calculated with __bf_shf >> * Improved the commit messages. >> * The change is still binary equivalent, but requires an extra step >> mentioned at the end of this cover letter. >> >> Applies to coresight/next 3619ee28488 >> Also available at https://gitlab.arm.com/linux-arm/linux-jc/-/tree/james-cs-register-refactor-v3 >> >> To check for binary equivalence follow the same steps in the cover letter >> of v2, but apply the following change to coresight-priv.h. This is because >> the existing version of the macros wrap the expression in a new scope {} >> that flips something in the compiler: >> >> #undef FIELD_GET >> #define FIELD_GET(_mask, _reg) (((_reg) & (_mask)) >> __bf_shf(_mask)) >> #undef FIELD_PREP >> #define FIELD_PREP(_mask, _val) (((_val) << __bf_shf(_mask)) & (_mask)) >> >> Thanks >> James >> >> James Clark (15): >> coresight: etm4x: Cleanup TRCIDR0 register accesses >> coresight: etm4x: Cleanup TRCIDR2 register accesses >> coresight: etm4x: Cleanup TRCIDR3 register accesses >> coresight: etm4x: Cleanup TRCIDR4 register accesses >> coresight: etm4x: Cleanup TRCIDR5 register accesses >> coresight: etm4x: Cleanup TRCCONFIGR register accesses >> coresight: etm4x: Cleanup TRCEVENTCTL1R register accesses >> coresight: etm4x: Cleanup TRCSTALLCTLR register accesses >> coresight: etm4x: Cleanup TRCVICTLR register accesses >> coresight: etm3x: Cleanup ETMTECR1 register accesses >> coresight: etm4x: Cleanup TRCACATRn register accesses >> coresight: etm4x: Cleanup TRCSSCCRn and TRCSSCSRn register accesses >> coresight: etm4x: Cleanup TRCSSPCICRn register accesses >> coresight: etm4x: Cleanup TRCBBCTLR register accesses >> coresight: etm4x: Cleanup TRCRSCTLRn register accesses >> >> .../coresight/coresight-etm3x-core.c | 2 +- >> .../coresight/coresight-etm3x-sysfs.c | 2 +- >> .../coresight/coresight-etm4x-core.c | 136 +++++-------- >> .../coresight/coresight-etm4x-sysfs.c | 180 +++++++++--------- >> drivers/hwtracing/coresight/coresight-etm4x.h | 122 ++++++++++-- >> 5 files changed, 244 insertions(+), 198 deletions(-) > > I am done reviewing this set. I will wait until rc1 or rc2 before moving > forward. If there are other comments needing a respin then I will wait for the > next revision. Otherwise I will apply this one after correcting the extra lines > at the end of patch 15. > Thanks for the review! > Thanks, > Mathieu > >> >> -- >> 2.28.0 >> _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel