From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=57174 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Pi1wT-0005Qc-W7 for qemu-devel@nongnu.org; Wed, 26 Jan 2011 04:45:43 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Pi1wK-0006m1-6A for qemu-devel@nongnu.org; Wed, 26 Jan 2011 04:45:33 -0500 Received: from mail.valinux.co.jp ([210.128.90.3]:43636) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Pi1wJ-0006lX-LC for qemu-devel@nongnu.org; Wed, 26 Jan 2011 04:45:24 -0500 From: Isaku Yamahata Date: Wed, 26 Jan 2011 18:45:20 +0900 Message-Id: <4f2e0ca7292b01fec0c38ce6bfb97f07784ea35b.1296034717.git.yamahata@valinux.co.jp> In-Reply-To: References: In-Reply-To: References: Subject: [Qemu-devel] [PATCH 3/3] pci/pcie: make pci_find_device() ARI aware. List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: yamahata@valinux.co.jp, mst@redhat.com make pci_find_device() ARI aware. Signed-off-by: Isaku Yamahata --- hw/pci.c | 6 ++++++ hw/pcie.c | 33 +++++++++++++++++++++++++++++---- hw/pcie.h | 2 +- 3 files changed, 36 insertions(+), 5 deletions(-) diff --git a/hw/pci.c b/hw/pci.c index ac16029..daba310 100644 --- a/hw/pci.c +++ b/hw/pci.c @@ -1601,12 +1601,18 @@ PCIBus *pci_find_bus(PCIBus *bus, int bus_num) PCIDevice *pci_find_device(PCIBus *bus, int bus_num, int devfn) { + PCIDevice *d; assert(devfn < PCI_DEVFN_MAX); bus = pci_find_bus(bus, bus_num); if (!bus) return NULL; + d = bus->parent_dev; + /* ARI: See the comment above the pcie_check_slot() for details */ + if (d && !pcie_check_slot(d, devfn)) { + return NULL; + } return bus->devices[devfn]; } diff --git a/hw/pcie.c b/hw/pcie.c index 6a113a9..ae4b531 100644 --- a/hw/pcie.c +++ b/hw/pcie.c @@ -424,13 +424,38 @@ void pcie_cap_ari_reset(PCIDevice *dev) pci_long_test_and_clear_mask(devctl2, PCI_EXP_DEVCTL2_ARI); } -bool pcie_cap_is_ari_enabled(const PCIDevice *dev) +/* + * 6.13 Alternative routing-ID Interpretation(ARI) + * 7.8.16 Device control 2 register + * ARI forwarding Enable + * + * With PCI Express Endpoints, there's a single device behind + * each downstream port bus, and bits 3:7 of the function number get + * encoded in the slot number (the Express spec calls it the Device + * Number). This allows > 8 functions, but + * these extended functions are only accessible when the + * Alternative routing-ID Interpretation (ARI) + * capability is enabled in the root/downstream port. With that capability + * disabled the port enforces the Device Number field being 0. + */ +bool pcie_check_slot(const PCIDevice *dev, int devfn) { + uint8_t type; + if (!pci_is_express(dev)) { - return false; + return true; } - if (!dev->exp.exp_cap) { - return false; + + type = pcie_cap_get_type(dev); + if (!(type == PCI_EXP_TYPE_ROOT_PORT || + type == PCI_EXP_TYPE_DOWNSTREAM)) { + return true; + } + + if (!PCI_SLOT(devfn)) { + /* With ARI, this means function < 8. + functions < 8 are always accesible. */ + return true; } return pci_get_long(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2) & diff --git a/hw/pcie.h b/hw/pcie.h index bc909e2..0c84662 100644 --- a/hw/pcie.h +++ b/hw/pcie.h @@ -119,7 +119,7 @@ void pcie_cap_flr_write_config(PCIDevice *dev, void pcie_cap_ari_init(PCIDevice *dev); void pcie_cap_ari_reset(PCIDevice *dev); -bool pcie_cap_is_ari_enabled(const PCIDevice *dev); +bool pcie_check_slot(const PCIDevice *dev, int devfn); /* PCI express extended capability helper functions */ uint16_t pcie_find_capability(PCIDevice *dev, uint16_t cap_id); -- 1.7.1.1