From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.3 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3B424C4332E for ; Fri, 5 Mar 2021 10:10:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 06F8865018 for ; Fri, 5 Mar 2021 10:10:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230047AbhCEKK3 (ORCPT ); Fri, 5 Mar 2021 05:10:29 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:54532 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229940AbhCEKKO (ORCPT ); Fri, 5 Mar 2021 05:10:14 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 125A9wKE110650; Fri, 5 Mar 2021 04:09:59 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1614938999; bh=YBLvYThaKVg7tURgnRZwl586okBWQyFp0lWLZANmnaA=; h=Subject:To:CC:References:From:Date:In-Reply-To; b=V2D85JCcwkwMHsADSiw9UBzYUTHANxXu1uOys/sDHPxHjxdtbO/9ypDK43E2NQQkW mKvBf7Gq4XWknqNTg8rRH7MIFWjVf/bRLVEpwK0Q5vmhuOJkfCGUBEluTEGhCquksO my4CEY3Mrjz8XTQ9hhLhatGF2wybFswF/HHk5qCU= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 125A9wMl106232 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 5 Mar 2021 04:09:58 -0600 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Fri, 5 Mar 2021 04:09:58 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Fri, 5 Mar 2021 04:09:58 -0600 Received: from [10.250.100.73] (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 125A9uvd115311; Fri, 5 Mar 2021 04:09:57 -0600 Subject: Re: [PATCH 1/3] clocksource/drivers/timer-ti-dm: Fix posted mode status check order To: Tony Lindgren CC: Daniel Lezcano , Thomas Gleixner , Keerthy , , , References: <20210304072135.52712-1-tony@atomide.com> <20210304072135.52712-2-tony@atomide.com> From: Grygorii Strashko Message-ID: <4f6212f7-824b-450e-b605-fcc8dc50a8fb@ti.com> Date: Fri, 5 Mar 2021 12:09:24 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8"; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 05/03/2021 09:53, Tony Lindgren wrote: > * Grygorii Strashko [210304 20:58]: >> On 04/03/2021 09:21, Tony Lindgren wrote: >>> When the timer is configured in posted mode, we need to check the write- >>> posted status register (TWPS) before writing to the register. > ... > >>> --- a/drivers/clocksource/timer-ti-dm-systimer.c >>> +++ b/drivers/clocksource/timer-ti-dm-systimer.c >>> @@ -449,13 +449,13 @@ static int dmtimer_set_next_event(unsigned long cycles, >>> struct dmtimer_systimer *t = &clkevt->t; >>> void __iomem *pend = t->base + t->pend; >>> - writel_relaxed(0xffffffff - cycles, t->base + t->counter); >>> while (readl_relaxed(pend) & WP_TCRR) >>> cpu_relax(); >>> + writel_relaxed(0xffffffff - cycles, t->base + t->counter); >>> - writel_relaxed(OMAP_TIMER_CTRL_ST, t->base + t->ctrl); >>> while (readl_relaxed(pend) & WP_TCLR) >>> cpu_relax(); >>> + writel_relaxed(OMAP_TIMER_CTRL_ST, t->base + t->ctrl); >> >> It seems static [and inline] helper here could be better solution. no? > > Well we wanted to get rid of the confusing macros. And in this case I > suspect we can eventually do just one read of the pending register for > the registers used mask rather than check the status separately multiple > times. But that needs to be carefully tested and is not a fix :) Might work. -- Best regards, grygorii From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.3 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BE7E1C433E0 for ; Fri, 5 Mar 2021 10:12:30 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 38CDF64FF0 for ; Fri, 5 Mar 2021 10:12:30 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 38CDF64FF0 Authentication-Results: mail.kernel.org; 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Fri, 5 Mar 2021 04:09:58 -0600 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Fri, 5 Mar 2021 04:09:58 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Fri, 5 Mar 2021 04:09:58 -0600 Received: from [10.250.100.73] (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 125A9uvd115311; Fri, 5 Mar 2021 04:09:57 -0600 Subject: Re: [PATCH 1/3] clocksource/drivers/timer-ti-dm: Fix posted mode status check order To: Tony Lindgren CC: Daniel Lezcano , Thomas Gleixner , Keerthy , , , References: <20210304072135.52712-1-tony@atomide.com> <20210304072135.52712-2-tony@atomide.com> From: Grygorii Strashko Message-ID: <4f6212f7-824b-450e-b605-fcc8dc50a8fb@ti.com> Date: Fri, 5 Mar 2021 12:09:24 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210305_101010_652351_288094C4 X-CRM114-Status: GOOD ( 15.23 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 05/03/2021 09:53, Tony Lindgren wrote: > * Grygorii Strashko [210304 20:58]: >> On 04/03/2021 09:21, Tony Lindgren wrote: >>> When the timer is configured in posted mode, we need to check the write- >>> posted status register (TWPS) before writing to the register. > ... > >>> --- a/drivers/clocksource/timer-ti-dm-systimer.c >>> +++ b/drivers/clocksource/timer-ti-dm-systimer.c >>> @@ -449,13 +449,13 @@ static int dmtimer_set_next_event(unsigned long cycles, >>> struct dmtimer_systimer *t = &clkevt->t; >>> void __iomem *pend = t->base + t->pend; >>> - writel_relaxed(0xffffffff - cycles, t->base + t->counter); >>> while (readl_relaxed(pend) & WP_TCRR) >>> cpu_relax(); >>> + writel_relaxed(0xffffffff - cycles, t->base + t->counter); >>> - writel_relaxed(OMAP_TIMER_CTRL_ST, t->base + t->ctrl); >>> while (readl_relaxed(pend) & WP_TCLR) >>> cpu_relax(); >>> + writel_relaxed(OMAP_TIMER_CTRL_ST, t->base + t->ctrl); >> >> It seems static [and inline] helper here could be better solution. no? > > Well we wanted to get rid of the confusing macros. And in this case I > suspect we can eventually do just one read of the pending register for > the registers used mask rather than check the status separately multiple > times. But that needs to be carefully tested and is not a fix :) Might work. -- Best regards, grygorii _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel