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([2607:fb90:5fe1:b497:51bb:ba21:d1a7:eac2]) by smtp.gmail.com with ESMTPSA id z39-20020a056870d6a700b000eb639a5652sm740461oap.37.2022.05.06.11.14.08 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 06 May 2022 11:14:09 -0700 (PDT) Message-ID: <4f679852-3cef-3ad1-7f47-987dd0f6739a@linaro.org> Date: Fri, 6 May 2022 13:14:05 -0500 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.8.0 Subject: Re: [PATCH 1/4] target/arm: Postpone interpretation of stage 2 descriptor attribute bits Content-Language: en-US To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20220505183950.2781801-1-peter.maydell@linaro.org> <20220505183950.2781801-2-peter.maydell@linaro.org> From: Richard Henderson In-Reply-To: <20220505183950.2781801-2-peter.maydell@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2001:4860:4864:20::32; envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x32.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 5/5/22 13:39, Peter Maydell wrote: > In the original Arm v8 two-stage translation, both stage 1 and stage > 2 specify memory attributes (memory type, cacheability, > shareability); these are then combined to produce the overall memory > attributes for the whole stage 1+2 access. In QEMU we implement this > by having get_phys_addr() fill in an ARMCacheAttrs struct, and we > convert both the stage 1 and stage 2 attribute bit formats to the > same encoding (an 8-bit attribute value matching the MAIR_EL1 fields, > plus a 2-bit shareability value). > > The new FEAT_S2FWB feature allows the guest to enable a different > interpretation of the attribute bits in the stage 2 descriptors. > These bits can now be used to control details of how the stage 1 and > 2 attributes should be combined (for instance they can say "always > use the stage 1 attributes" or "ignore the stage 1 attributes and > always be Device memory"). This means we need to pass the raw bit > information for stage 2 down to the function which combines the stage > 1 and stage 2 information. > > Add a field to ARMCacheAttrs that indicates whether the attrs field > should be interpreted as MAIR format, or as the raw stage 2 attribute > bits from the descriptor, and store the appropriate values when > filling in cacheattrs. > > We only need to interpret the attrs field in a few places: > * in do_ats_write(), where we know to expect a MAIR value > (there is no ATS instruction to do a stage-2-only walk) > * in S1_ptw_translate(), where we want to know whether the > combined S1 + S2 attributes indicate Device memory that > should provoke a fault > * in combine_cacheattrs(), which does the S1 + S2 combining > Update those places accordingly. > > Signed-off-by: Peter Maydell > --- > target/arm/internals.h | 7 ++++++- > target/arm/helper.c | 42 ++++++++++++++++++++++++++++++++++++------ > 2 files changed, 42 insertions(+), 7 deletions(-) Reviewed-by: Richard Henderson r~