From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EC002C433EF for ; Sat, 9 Apr 2022 03:55:24 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 3A78E83DDD; Sat, 9 Apr 2022 05:55:22 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=rock-chips.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 7E90383DE1; Sat, 9 Apr 2022 05:55:19 +0200 (CEST) Received: from mail-m17664.qiye.163.com (mail-m17664.qiye.163.com [59.111.176.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id C6F0783DD8 for ; Sat, 9 Apr 2022 05:55:15 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=kever.yang@rock-chips.com Received: from [192.168.0.115] (unknown [112.49.233.126]) by mail-m17664.qiye.163.com (Hmail) with ESMTPA id 3E6E714020B; Sat, 9 Apr 2022 11:55:03 +0800 (CST) Message-ID: <4fcf51b5-ec79-42d8-f13a-70997d92d5dc@rock-chips.com> Date: Sat, 9 Apr 2022 11:55:02 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.7.0 Subject: Re: [PATCH v9 12/16] rockchip: rk3066: add core support Content-Language: en-US To: Johan Jonker Cc: sjg@chromium.org, philipp.tomsich@vrull.eu, lukma@denx.de, seanga2@gmail.com, u-boot@lists.denx.de References: <20220404141926.6085-1-jbx6244@gmail.com> <20220404141926.6085-13-jbx6244@gmail.com> From: Kever Yang In-Reply-To: <20220404141926.6085-13-jbx6244@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-HM-Spam-Status: e1kfGhgUHx5ZQUtXWQgPGg8OCBgUHx5ZQUlOS1dZCBgUCR5ZQVlLVUtZV1 kWDxoPAgseWUFZKDYvK1lXWShZQUhPN1dZLVlBSVdZDwkaFQgSH1lBWUNOSEpWTk0aGh0aH09KGB 5JVRMBExYaEhckFA4PWVdZFhoPEhUdFFlBWU9LSFVKSktISkxVS1kG X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6OTo6Thw*Mz5MFUw0SzVRNBE8 Pz8aCk5VSlVKTU9CT0xNTktITUhOVTMWGhIXVRAeDR4JVQIaFRw7CRQYEFYYExILCFUYFBZFWVdZ EgtZQVlKSklVT0JVSUhIVUpJTVlXWQgBWUFKS0lNTjcG X-HM-Tid: 0a800c760743da2fkuws3e6e714020b X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean Hi Johan, Please squash patch 10~12 into one patch. Thanks, - Kever On 2022/4/4 22:19, Johan Jonker wrote: > Add the core architecture code for the rk3066. > > Signed-off-by: Johan Jonker > --- > arch/arm/mach-rockchip/Kconfig | 23 ++++++++ > arch/arm/mach-rockchip/Makefile | 1 + > arch/arm/mach-rockchip/rk3066/Kconfig | 30 ++++++++++ > arch/arm/mach-rockchip/rk3066/Makefile | 5 ++ > arch/arm/mach-rockchip/rk3066/clk_rk3066.c | 33 +++++++++++ > arch/arm/mach-rockchip/rk3066/rk3066.c | 49 +++++++++++++++++ > arch/arm/mach-rockchip/rk3066/syscon_rk3066.c | 55 +++++++++++++++++++ > 7 files changed, 196 insertions(+) > create mode 100644 arch/arm/mach-rockchip/rk3066/Kconfig > create mode 100644 arch/arm/mach-rockchip/rk3066/Makefile > create mode 100644 arch/arm/mach-rockchip/rk3066/clk_rk3066.c > create mode 100644 arch/arm/mach-rockchip/rk3066/rk3066.c > create mode 100644 arch/arm/mach-rockchip/rk3066/syscon_rk3066.c > > diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig > index 811964973a..18aff5480b 100644 > --- a/arch/arm/mach-rockchip/Kconfig > +++ b/arch/arm/mach-rockchip/Kconfig > @@ -35,6 +35,28 @@ config ROCKCHIP_RK3036 > and video codec support. Peripherals include Gigabit Ethernet, > USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs. > > +config ROCKCHIP_RK3066 > + bool "Support Rockchip RK3066" > + select CPU_V7A > + select SPL_BOARD_INIT if SPL > + select SUPPORT_SPL > + select SUPPORT_TPL > + select SPL > + select TPL > + select TPL_ROCKCHIP_BACK_TO_BROM > + select TPL_ROCKCHIP_EARLYRETURN_TO_BROM > + imply ROCKCHIP_COMMON_BOARD > + imply SPL_ROCKCHIP_COMMON_BOARD > + imply SPL_SERIAL > + imply TPL_ROCKCHIP_COMMON_BOARD > + imply TPL_SERIAL > + help > + The Rockchip RK3066 is a ARM-based SoC with a dual-core Cortex-A9 > + including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two > + video interfaces, several memory options and video codec support. > + Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S, > + UART, SPI, I2C and PWMs. > + > config ROCKCHIP_RK3128 > bool "Support Rockchip RK3128" > select CPU_V7A > @@ -405,6 +427,7 @@ config LNX_KRNL_IMG_TEXT_OFFSET_BASE > > source "arch/arm/mach-rockchip/px30/Kconfig" > source "arch/arm/mach-rockchip/rk3036/Kconfig" > +source "arch/arm/mach-rockchip/rk3066/Kconfig" > source "arch/arm/mach-rockchip/rk3128/Kconfig" > source "arch/arm/mach-rockchip/rk3188/Kconfig" > source "arch/arm/mach-rockchip/rk322x/Kconfig" > diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile > index 00aef0ecee..6c1c7b8a10 100644 > --- a/arch/arm/mach-rockchip/Makefile > +++ b/arch/arm/mach-rockchip/Makefile > @@ -34,6 +34,7 @@ obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram.o > > obj-$(CONFIG_ROCKCHIP_PX30) += px30/ > obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/ > +obj-$(CONFIG_ROCKCHIP_RK3066) += rk3066/ > obj-$(CONFIG_ROCKCHIP_RK3128) += rk3128/ > obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188/ > obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x/ > diff --git a/arch/arm/mach-rockchip/rk3066/Kconfig b/arch/arm/mach-rockchip/rk3066/Kconfig > new file mode 100644 > index 0000000000..335f49bc55 > --- /dev/null > +++ b/arch/arm/mach-rockchip/rk3066/Kconfig > @@ -0,0 +1,30 @@ > +if ROCKCHIP_RK3066 > + > +config ROCKCHIP_BOOT_MODE_REG > + default 0x20004040 > + > +config SYS_SOC > + default "rk3066" > + > +config SYS_MALLOC_F_LEN > + default 0x0800 > + > +config SPL_LIBCOMMON_SUPPORT > + default y > + > +config SPL_LIBGENERIC_SUPPORT > + default y > + > +config SPL_SERIAL > + default y > + > +config TPL_LIBCOMMON_SUPPORT > + default y > + > +config TPL_LIBGENERIC_SUPPORT > + default y > + > +config TPL_SERIAL > + default y > + > +endif > diff --git a/arch/arm/mach-rockchip/rk3066/Makefile b/arch/arm/mach-rockchip/rk3066/Makefile > new file mode 100644 > index 0000000000..9e2a9d4b0a > --- /dev/null > +++ b/arch/arm/mach-rockchip/rk3066/Makefile > @@ -0,0 +1,5 @@ > +# SPDX-License-Identifier: GPL-2.0+ > + > +obj-y += clk_rk3066.o > +obj-y += rk3066.o > +obj-y += syscon_rk3066.o > diff --git a/arch/arm/mach-rockchip/rk3066/clk_rk3066.c b/arch/arm/mach-rockchip/rk3066/clk_rk3066.c > new file mode 100644 > index 0000000000..c47526dca5 > --- /dev/null > +++ b/arch/arm/mach-rockchip/rk3066/clk_rk3066.c > @@ -0,0 +1,33 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright (C) 2015 Google, Inc > + * Written by Simon Glass > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > + > +int rockchip_get_clk(struct udevice **devp) > +{ > + return uclass_get_device_by_driver(UCLASS_CLK, > + DM_DRIVER_GET(rockchip_rk3066a_cru), devp); > +} > + > +void *rockchip_get_cru(void) > +{ > + struct rk3066_clk_priv *priv; > + struct udevice *dev; > + int ret; > + > + ret = rockchip_get_clk(&dev); > + if (ret) > + return ERR_PTR(ret); > + > + priv = dev_get_priv(dev); > + > + return priv->cru; > +} > diff --git a/arch/arm/mach-rockchip/rk3066/rk3066.c b/arch/arm/mach-rockchip/rk3066/rk3066.c > new file mode 100644 > index 0000000000..78c7d894f9 > --- /dev/null > +++ b/arch/arm/mach-rockchip/rk3066/rk3066.c > @@ -0,0 +1,49 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * (C) Copyright 2016 Rockchip Electronics Co., Ltd > + */ > + > +#include > +#include > +#include > +#include > + > +#define GRF_BASE 0x20008000 > + > +const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { > + [BROM_BOOTSOURCE_EMMC] = "/mmc@1021c000", > + [BROM_BOOTSOURCE_SD] = "/mmc@10214000", > +}; > + > +void board_debug_uart_init(void) > +{ > + struct rk3066_grf * const grf = (void *)GRF_BASE; > + > + /* Enable early UART on the RK3066 */ > + rk_clrsetreg(&grf->gpio1b_iomux, > + GPIO1B1_MASK | GPIO1B0_MASK, > + GPIO1B1_UART2_SOUT << GPIO1B1_SHIFT | > + GPIO1B0_UART2_SIN << GPIO1B0_SHIFT); > +} > + > +void spl_board_init(void) > +{ > + if (!IS_ENABLED(CONFIG_SPL_BUILD)) > + return; > + > + if (IS_ENABLED(CONFIG_SPL_DM_MMC)) { > + struct rk3066_grf * const grf = (void *)GRF_BASE; > + > + rk_clrsetreg(&grf->gpio3b_iomux, > + GPIO3B0_MASK | GPIO3B1_MASK | GPIO3B2_MASK | > + GPIO3B3_MASK | GPIO3B4_MASK | GPIO3B5_MASK | > + GPIO3B6_MASK, > + GPIO3B0_SDMMC0_CLKOUT << GPIO3B0_SHIFT | > + GPIO3B1_SDMMC0_CMD << GPIO3B1_SHIFT | > + GPIO3B2_SDMMC0_DATA0 << GPIO3B2_SHIFT | > + GPIO3B3_SDMMC0_DATA1 << GPIO3B3_SHIFT | > + GPIO3B4_SDMMC0_DATA2 << GPIO3B4_SHIFT | > + GPIO3B5_SDMMC0_DATA3 << GPIO3B5_SHIFT | > + GPIO3B6_SDMMC0_DECTN << GPIO3B6_SHIFT); > + } > +} > diff --git a/arch/arm/mach-rockchip/rk3066/syscon_rk3066.c b/arch/arm/mach-rockchip/rk3066/syscon_rk3066.c > new file mode 100644 > index 0000000000..a598f6400d > --- /dev/null > +++ b/arch/arm/mach-rockchip/rk3066/syscon_rk3066.c > @@ -0,0 +1,55 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright (C) 2015 Google, Inc > + * Written by Simon Glass > + */ > + > +#include > +#include > +#include > +#include > +#include > + > +static const struct udevice_id rk3066_syscon_ids[] = { > + { .compatible = "rockchip,rk3066-noc", .data = ROCKCHIP_SYSCON_NOC }, > + { .compatible = "rockchip,rk3066-grf", .data = ROCKCHIP_SYSCON_GRF }, > + { .compatible = "rockchip,rk3066-pmu", .data = ROCKCHIP_SYSCON_PMU }, > + { } > +}; > + > +U_BOOT_DRIVER(syscon_rk3066) = { > + .name = "rk3066_syscon", > + .id = UCLASS_SYSCON, > + .of_match = rk3066_syscon_ids, > +}; > + > +#if CONFIG_IS_ENABLED(OF_PLATDATA) > +static int rk3066_syscon_bind_of_plat(struct udevice *dev) > +{ > + dev->driver_data = dev->driver->of_match->data; > + debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data); > + > + return 0; > +} > + > +U_BOOT_DRIVER(rockchip_rk3066_noc) = { > + .name = "rockchip_rk3066_noc", > + .id = UCLASS_SYSCON, > + .of_match = rk3066_syscon_ids, > + .bind = rk3066_syscon_bind_of_plat, > +}; > + > +U_BOOT_DRIVER(rockchip_rk3066_grf) = { > + .name = "rockchip_rk3066_grf", > + .id = UCLASS_SYSCON, > + .of_match = rk3066_syscon_ids + 1, > + .bind = rk3066_syscon_bind_of_plat, > +}; > + > +U_BOOT_DRIVER(rockchip_rk3066_pmu) = { > + .name = "rockchip_rk3066_pmu", > + .id = UCLASS_SYSCON, > + .of_match = rk3066_syscon_ids + 2, > + .bind = rk3066_syscon_bind_of_plat, > +}; > +#endif