From mboxrd@z Thu Jan 1 00:00:00 1970 From: Fabian Cenedese Date: Fri, 28 Jan 2011 11:02:31 +0100 Subject: [U-Boot] [PATCH 5/8 v3] P1021: add P1021MDS board support In-Reply-To: <1296190690-21146-3-git-send-email-Haiying.Wang@freescale.c om> References: <1296190690-21146-1-git-send-email-Haiying.Wang@freescale.com> <1296190690-21146-1-git-send-email-Haiying.Wang@freescale.com> Message-ID: <5.2.0.9.1.20110128105955.03543be8@localhost> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de At 23:58 27.01.2011 -0500, Haiying.Wang at freescale.com wrote: >From: Haiying Wang > >Support P1021MDS board to boot from NAND flash (No NOR flash on this >board). And because P1021 only has 256K L2 SRAM, which can not used for final >uboot image, this patch also enables the TPL BOOT on P1021MDS so that DDR can >be initialized in L2 SRAM through SPD code. So there are three stage uboot >images: >* nand_spl, pad from 4KB size to 16KB, load tpl_boot from offset 16KB in NAND. >* tpl_boot, 112KB size. The env variables are copied to offset 128KB > in L2 SRAM, so that ddr spd code can get the interleaving mode setting in env. > It loads final uboot image from offset 128KB in NAND. >* final uboot image, size is variable depends on the functions enabled. I'm not questioning the patch, I'm just trying to understand. >+#define CONFIG_MP /* Multiprocessor support */ >+ >+#define CONFIG_PCI /* Disable PCI/PCIE */ Shouldn't that be "Enable" PCI? bye Fabi