From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stephen Warren Date: Tue, 24 Jul 2012 13:16:54 -0600 Subject: [U-Boot] [PATCH 0/17] tegra: Add display driver and LCD support for Seaboard In-Reply-To: References: <1326588449-1794-1-git-send-email-sjg@chromium.org> <20120717161141.GA16901@avionic-0098.mockup.avionic-design.de> Message-ID: <500EF4A6.1020308@wwwdotorg.org> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 07/18/2012 12:51 AM, Simon Glass wrote: > +Tom, Stephen > > On Tue, Jul 17, 2012 at 5:11 PM, Thierry Reding > wrote: >> On Sat, Jul 14, 2012 at 10:03:31AM +0200, Simon Glass wrote: >>> Hi Christian, >>> >>> On Thu, Apr 19, 2012 at 2:41 PM, Christian Kroehnert >>> wrote: ... >>>> In the display.c source file I implemented a bug fix, because I get garbled >>>> images on the LCD without this fix. >>> >>> I see this code: >>> >>> u32 m_value; >>> >>> m_value = readl(0x54202e04); >>> m_value &= ~0x2; >>> writel(m_value, 0x54202e04); >>> >>> What register are you actually writing here? I can't find it in my >>> manual, but maybe I just haven't seen that address. >> >> At the time I did look for that register as well but couldn't find >> anything. But I believe that we saw the garbled display issue that >> has been mentioned in another thread. If I remember correctly this >> particular register write was the fix for it. >> >> But I wasn't very much involved at the time, so maybe Christian can >> clarify. However I was going to test your newest version of the LCD >> patch series on our hardware and see if the issue is still there. > > Does anyone know what this register is for? I am reluctant to add this > code to the patch without at least a comment. That address is an alias for DC_WIN_A_BYTE_SWAP_0 (offset 0x701), which is documented in the TRM. It seems unlikely this was solve the issue at hand, if I remember it correctly.