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Date: Tue, 31 Jul 2012 11:11:49 -0500
From: Scott Wood <scottwood@freescale.com>
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To: Matthieu CASTET <matthieu.castet@parrot.com>
Subject: Re: [PATCH RESEND] mtd: nand: allow NAND_NO_SUBPAGE_WRITE to be set
 from driver
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On 07/31/2012 02:33 AM, Matthieu CASTET wrote:
> Hi,
> 
> for ONFI flash (like this micron one) the information should be extracted form
> the ONFI table (programs_per_page IIRC)
> 
> This should be better than relying on the SOC driver for setting this flags.

This is for cases where the constraint is the controller, not the chip.

> Does the gpmi driver set this flag because it do not support partial write ?
> In this case why it doesn't set  chip->ecc.steps to 1 ?

Why is it better to lie about ECC geometry than to just say "subpage
writes aren't supported"?  Does/will the ECC geometry get used by upper
layers in evaluating the number of corrected bitflips?

-Scott