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Date: Wed, 1 Aug 2012 11:15:01 -0500
From: Scott Wood <scottwood@freescale.com>
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To: Matthieu CASTET <matthieu.castet@parrot.com>
Subject: Re: [PATCH RESEND] mtd: nand: allow NAND_NO_SUBPAGE_WRITE to be set
 from driver
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On 08/01/2012 08:05 AM, Matthieu CASTET wrote:
> Hi Scott,
>=20
> Scott Wood a =C3=A9crit :
>> On 07/31/2012 02:33 AM, Matthieu CASTET wrote:
>>> Hi,
>>>
>>> for ONFI flash (like this micron one) the information should be extra=
cted form
>>> the ONFI table (programs_per_page IIRC)
>>>
>>> This should be better than relying on the SOC driver for setting this=
 flags.
>>
>> This is for cases where the constraint is the controller, not the chip=
.
>>
>>> Does the gpmi driver set this flag because it do not support partial =
write ?
>>> In this case why it doesn't set  chip->ecc.steps to 1 ?
>>
>> Why is it better to lie about ECC geometry than to just say "subpage
>> writes aren't supported"?  Does/will the ECC geometry get used by uppe=
r
>> layers in evaluating the number of corrected bitflips?
> If it is not because of ecc geometry, why the controller doesn't suppor=
t subpage
> writes ?

I can't answer for GPMI, but in the case of Freescale eLBC/IFC, the
controller only does ECC when you do a full page transaction -- but the
ECC is still done in steps, which is relevant for bitflip thresholds.

-Scott