* [U-Boot] [PATCH 3/9] arm: socfpga: mcvevk: Adding handoff for SDRAM ctrlcfg.extratime1
@ 2016-09-15 7:27 Chin Liang See
2016-09-19 14:24 ` Marek Vasut
0 siblings, 1 reply; 3+ messages in thread
From: Chin Liang See @ 2016-09-15 7:27 UTC (permalink / raw)
To: u-boot
Adding new handoff for SDRAM ctrcfg.extratime1 which is
required for stabil LPDDR2 operation
Signed-off-by: Chin Liang See <clsee@altera.com>
---
board/denx/mcvevk/qts/sdram_config.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/board/denx/mcvevk/qts/sdram_config.h b/board/denx/mcvevk/qts/sdram_config.h
index 30c4d7d..0328850 100644
--- a/board/denx/mcvevk/qts/sdram_config.h
+++ b/board/denx/mcvevk/qts/sdram_config.h
@@ -49,6 +49,9 @@
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 5
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 2
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 2
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 2
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0
--
2.2.2
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [U-Boot] [PATCH 3/9] arm: socfpga: mcvevk: Adding handoff for SDRAM ctrlcfg.extratime1
2016-09-19 14:24 ` Marek Vasut
@ 2016-09-19 10:13 ` Chin Liang See
0 siblings, 0 replies; 3+ messages in thread
From: Chin Liang See @ 2016-09-19 10:13 UTC (permalink / raw)
To: u-boot
On Mon, 2016-09-19 at 16:24 +0200, Marek Vasut wrote:
> On 09/15/2016 09:27 AM, Chin Liang See wrote:
> > Adding new handoff for SDRAM ctrcfg.extratime1 which is
> > required for stabil LPDDR2 operation
>
> Same comment as 2/9
Yup, this patch is not required.
Thanks
Chin Liang
>
> > Signed-off-by: Chin Liang See <clsee@altera.com>
> > ---
> > board/denx/mcvevk/qts/sdram_config.h | 3 +++
> > 1 file changed, 3 insertions(+)
> >
> > diff --git a/board/denx/mcvevk/qts/sdram_config.h
> > b/board/denx/mcvevk/qts/sdram_config.h
> > index 30c4d7d..0328850 100644
> > --- a/board/denx/mcvevk/qts/sdram_config.h
> > +++ b/board/denx/mcvevk/qts/sdram_config.h
> > @@ -49,6 +49,9 @@
> > #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP
> > 5
> > #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT
> > 3
> > #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT
> > 512
> > +#define
> > CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 2
> > +#define
> > CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 2
> > +#define
> > CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_C
> > HIP 2
> > #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC
> > 0
> > #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE
> > 0
> > #define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST
> > 0x0
> >
>
>
^ permalink raw reply [flat|nested] 3+ messages in thread
* [U-Boot] [PATCH 3/9] arm: socfpga: mcvevk: Adding handoff for SDRAM ctrlcfg.extratime1
2016-09-15 7:27 [U-Boot] [PATCH 3/9] arm: socfpga: mcvevk: Adding handoff for SDRAM ctrlcfg.extratime1 Chin Liang See
@ 2016-09-19 14:24 ` Marek Vasut
2016-09-19 10:13 ` Chin Liang See
0 siblings, 1 reply; 3+ messages in thread
From: Marek Vasut @ 2016-09-19 14:24 UTC (permalink / raw)
To: u-boot
On 09/15/2016 09:27 AM, Chin Liang See wrote:
> Adding new handoff for SDRAM ctrcfg.extratime1 which is
> required for stabil LPDDR2 operation
Same comment as 2/9
> Signed-off-by: Chin Liang See <clsee@altera.com>
> ---
> board/denx/mcvevk/qts/sdram_config.h | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/board/denx/mcvevk/qts/sdram_config.h b/board/denx/mcvevk/qts/sdram_config.h
> index 30c4d7d..0328850 100644
> --- a/board/denx/mcvevk/qts/sdram_config.h
> +++ b/board/denx/mcvevk/qts/sdram_config.h
> @@ -49,6 +49,9 @@
> #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 5
> #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
> #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
> +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 2
> +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 2
> +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 2
> #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
> #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
> #define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0
>
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 3+ messages in thread
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2016-09-15 7:27 [U-Boot] [PATCH 3/9] arm: socfpga: mcvevk: Adding handoff for SDRAM ctrlcfg.extratime1 Chin Liang See
2016-09-19 14:24 ` Marek Vasut
2016-09-19 10:13 ` Chin Liang See
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