From mboxrd@z Thu Jan 1 00:00:00 1970 From: =?ISO-8859-15?Q?Andreas_F=E4rber?= Subject: Re: [Qemu-devel] [RFC v2 4/6] hw/kvm/arm_gic: Implement support for KVM in-kernel ARM GIC Date: Wed, 10 Oct 2012 19:23:53 +0200 Message-ID: <5075AF29.30509@suse.de> References: <1349881659-8403-1-git-send-email-peter.maydell@linaro.org> <1349881659-8403-5-git-send-email-peter.maydell@linaro.org> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: QUOTED-PRINTABLE Cc: qemu-devel@nongnu.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, patches@linaro.org To: Peter Maydell Return-path: Received: from cantor2.suse.de ([195.135.220.15]:48830 "EHLO mx2.suse.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751351Ab2JJRX6 (ORCPT ); Wed, 10 Oct 2012 13:23:58 -0400 In-Reply-To: <1349881659-8403-5-git-send-email-peter.maydell@linaro.org> Sender: kvm-owner@vger.kernel.org List-ID: Am 10.10.2012 17:07, schrieb Peter Maydell: > Implement support for using the KVM in-kernel GIC for ARM. >=20 > Signed-off-by: Peter Maydell > --- > hw/a15mpcore.c | 8 ++- > hw/arm/Makefile.objs | 1 + > hw/kvm/arm_gic.c | 162 ++++++++++++++++++++++++++++++++++++++++= ++++++++++ > 3 files changed, 170 insertions(+), 1 deletion(-) > create mode 100644 hw/kvm/arm_gic.c >=20 > diff --git a/hw/a15mpcore.c b/hw/a15mpcore.c > index fc0a02a..a37fc61 100644 > --- a/hw/a15mpcore.c > +++ b/hw/a15mpcore.c > @@ -19,6 +19,7 @@ > */ > =20 > #include "sysbus.h" > +#include "kvm.h" > =20 > /* A15MP private memory region. */ > =20 > @@ -41,7 +42,12 @@ static int a15mp_priv_init(SysBusDevice *dev) > A15MPPrivState *s =3D FROM_SYSBUS(A15MPPrivState, dev); > SysBusDevice *busdev; > =20 > - s->gic =3D qdev_create(NULL, "arm_gic"); > + if (kvm_irqchip_in_kernel()) { > + s->gic =3D qdev_create(NULL, "kvm-arm_gic"); > + } else { > + s->gic =3D qdev_create(NULL, "arm_gic"); > + } You could follow x86 more closely by just selecting apic_type. (Then if we drop/change qdev_create() at some point it's one change less.) > + > qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu); > qdev_prop_set_uint32(s->gic, "num-irq", s->num_irq); > qdev_prop_set_uint32(s->gic, "revision", 2); [...] > diff --git a/hw/kvm/arm_gic.c b/hw/kvm/arm_gic.c > new file mode 100644 > index 0000000..3ec538d > --- /dev/null > +++ b/hw/kvm/arm_gic.c > @@ -0,0 +1,162 @@ > +/* > + * ARM Generic Interrupt Controller using KVM in-kernel support > + * > + * Copyright (c) 2012 Linaro Limited > + * Written by Peter Maydell > + * > + * This program is free software; you can redistribute it and/or mod= ify > + * it under the terms of the GNU General Public License as published= by > + * the Free Software Foundation, either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License= along > + * with this program; if not, see . > + */ > + > +#include "hw/sysbus.h" > +#include "kvm.h" > +#include "hw/arm_gic_internal.h" > + > +#define TYPE_KVM_ARM_GIC "kvm-arm_gic" "kvm-arm-gic"? > +#define KVM_ARM_GIC(obj) \ > + OBJECT_CHECK(gic_state, (obj), TYPE_KVM_ARM_GIC) > +#define KVM_ARM_GIC_CLASS(klass) \ > + OBJECT_CLASS_CHECK(KVMARMGICClass, (klass), TYPE_KVM_ARM_GIC) > +#define KVM_ARM_GIC_GET_CLASS(obj) \ > + OBJECT_GET_CLASS(KVMARMGICClass, (obj), TYPE_KVM_ARM_GIC) > + > +typedef struct KVMARMGICClass { > + ARMGICCommonClass parent_class; > + int (*parent_init)(SysBusDevice *dev); > + void (*parent_reset)(DeviceState *dev); > +} KVMARMGICClass; > + > +static void kvm_arm_gic_set_irq(void *opaque, int irq, int level) > +{ > + /* Meaning of the 'irq' parameter: > + * [0..N-1] : external interrupts > + * [N..N+31] : PPI (internal) interrupts for CPU 0 > + * [N+32..N+63] : PPI (internal interrupts for CPU 1 > + * ... > + * Convert this to the kernel's desired encoding, which > + * has separate fields in the irq number for type, > + * CPU number and interrupt number. > + */ > + gic_state *s =3D (gic_state *)opaque; You don't happen to have time to clean up gic_state -> GICState before spreading its use? ;) [...] > +static TypeInfo arm_gic_info =3D { static const > + .name =3D TYPE_KVM_ARM_GIC, > + .parent =3D TYPE_ARM_GIC_COMMON, > + .instance_size =3D sizeof(gic_state), > + .class_init =3D kvm_arm_gic_class_init, > + .class_size =3D sizeof(KVMARMGICClass), > +}; > + > +static void arm_gic_register_types(void) kvm_arm_gic_register_types? > +{ > + type_register_static(&arm_gic_info); > +} > + > +type_init(arm_gic_register_types) >=20 Andreas --=20 SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N=FCrnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imend=F6rffer; HRB 16746 AG N=FCrn= berg From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:42337) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TM00m-0004wq-Vb for qemu-devel@nongnu.org; Wed, 10 Oct 2012 13:24:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TM00l-0004aR-4a for qemu-devel@nongnu.org; Wed, 10 Oct 2012 13:24:00 -0400 Received: from cantor2.suse.de ([195.135.220.15]:48827 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TM00k-0004Zu-Qm for qemu-devel@nongnu.org; Wed, 10 Oct 2012 13:23:59 -0400 Message-ID: <5075AF29.30509@suse.de> Date: Wed, 10 Oct 2012 19:23:53 +0200 From: =?ISO-8859-15?Q?Andreas_F=E4rber?= MIME-Version: 1.0 References: <1349881659-8403-1-git-send-email-peter.maydell@linaro.org> <1349881659-8403-5-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1349881659-8403-5-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [RFC v2 4/6] hw/kvm/arm_gic: Implement support for KVM in-kernel ARM GIC List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: patches@linaro.org, qemu-devel@nongnu.org, kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu Am 10.10.2012 17:07, schrieb Peter Maydell: > Implement support for using the KVM in-kernel GIC for ARM. >=20 > Signed-off-by: Peter Maydell > --- > hw/a15mpcore.c | 8 ++- > hw/arm/Makefile.objs | 1 + > hw/kvm/arm_gic.c | 162 ++++++++++++++++++++++++++++++++++++++++++= ++++++++ > 3 files changed, 170 insertions(+), 1 deletion(-) > create mode 100644 hw/kvm/arm_gic.c >=20 > diff --git a/hw/a15mpcore.c b/hw/a15mpcore.c > index fc0a02a..a37fc61 100644 > --- a/hw/a15mpcore.c > +++ b/hw/a15mpcore.c > @@ -19,6 +19,7 @@ > */ > =20 > #include "sysbus.h" > +#include "kvm.h" > =20 > /* A15MP private memory region. */ > =20 > @@ -41,7 +42,12 @@ static int a15mp_priv_init(SysBusDevice *dev) > A15MPPrivState *s =3D FROM_SYSBUS(A15MPPrivState, dev); > SysBusDevice *busdev; > =20 > - s->gic =3D qdev_create(NULL, "arm_gic"); > + if (kvm_irqchip_in_kernel()) { > + s->gic =3D qdev_create(NULL, "kvm-arm_gic"); > + } else { > + s->gic =3D qdev_create(NULL, "arm_gic"); > + } You could follow x86 more closely by just selecting apic_type. (Then if we drop/change qdev_create() at some point it's one change less.) > + > qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu); > qdev_prop_set_uint32(s->gic, "num-irq", s->num_irq); > qdev_prop_set_uint32(s->gic, "revision", 2); [...] > diff --git a/hw/kvm/arm_gic.c b/hw/kvm/arm_gic.c > new file mode 100644 > index 0000000..3ec538d > --- /dev/null > +++ b/hw/kvm/arm_gic.c > @@ -0,0 +1,162 @@ > +/* > + * ARM Generic Interrupt Controller using KVM in-kernel support > + * > + * Copyright (c) 2012 Linaro Limited > + * Written by Peter Maydell > + * > + * This program is free software; you can redistribute it and/or modif= y > + * it under the terms of the GNU General Public License as published b= y > + * the Free Software Foundation, either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License a= long > + * with this program; if not, see . > + */ > + > +#include "hw/sysbus.h" > +#include "kvm.h" > +#include "hw/arm_gic_internal.h" > + > +#define TYPE_KVM_ARM_GIC "kvm-arm_gic" "kvm-arm-gic"? > +#define KVM_ARM_GIC(obj) \ > + OBJECT_CHECK(gic_state, (obj), TYPE_KVM_ARM_GIC) > +#define KVM_ARM_GIC_CLASS(klass) \ > + OBJECT_CLASS_CHECK(KVMARMGICClass, (klass), TYPE_KVM_ARM_GIC) > +#define KVM_ARM_GIC_GET_CLASS(obj) \ > + OBJECT_GET_CLASS(KVMARMGICClass, (obj), TYPE_KVM_ARM_GIC) > + > +typedef struct KVMARMGICClass { > + ARMGICCommonClass parent_class; > + int (*parent_init)(SysBusDevice *dev); > + void (*parent_reset)(DeviceState *dev); > +} KVMARMGICClass; > + > +static void kvm_arm_gic_set_irq(void *opaque, int irq, int level) > +{ > + /* Meaning of the 'irq' parameter: > + * [0..N-1] : external interrupts > + * [N..N+31] : PPI (internal) interrupts for CPU 0 > + * [N+32..N+63] : PPI (internal interrupts for CPU 1 > + * ... > + * Convert this to the kernel's desired encoding, which > + * has separate fields in the irq number for type, > + * CPU number and interrupt number. > + */ > + gic_state *s =3D (gic_state *)opaque; You don't happen to have time to clean up gic_state -> GICState before spreading its use? ;) [...] > +static TypeInfo arm_gic_info =3D { static const > + .name =3D TYPE_KVM_ARM_GIC, > + .parent =3D TYPE_ARM_GIC_COMMON, > + .instance_size =3D sizeof(gic_state), > + .class_init =3D kvm_arm_gic_class_init, > + .class_size =3D sizeof(KVMARMGICClass), > +}; > + > +static void arm_gic_register_types(void) kvm_arm_gic_register_types? > +{ > + type_register_static(&arm_gic_info); > +} > + > +type_init(arm_gic_register_types) >=20 Andreas --=20 SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N=FCrnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imend=F6rffer; HRB 16746 AG N=FCrnbe= rg