From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1422857Ab2JaNYL (ORCPT ); Wed, 31 Oct 2012 09:24:11 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:58975 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S935543Ab2JaNYG (ORCPT ); Wed, 31 Oct 2012 09:24:06 -0400 Message-ID: <50912667.9030909@ti.com> Date: Wed, 31 Oct 2012 09:23:51 -0400 From: Murali Karicheri User-Agent: Mozilla/5.0 (X11; Linux i686; rv:16.0) Gecko/20121026 Thunderbird/16.0.2 MIME-Version: 1.0 To: Linus Walleij CC: , , , , , , , , , , , , , Subject: Re: [PATCH v3 01/11] clk: davinci - add main PLL clock driver References: <1351181518-11882-1-git-send-email-m-karicheri2@ti.com> <1351181518-11882-2-git-send-email-m-karicheri2@ti.com> In-Reply-To: Content-Type: text/plain; charset="ISO-8859-1"; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 10/28/2012 03:18 PM, Linus Walleij wrote: > On Thu, Oct 25, 2012 at 6:11 PM, Murali Karicheri wrote: > >> This is the driver for the main PLL clock hardware found on DM SoCs. >> This driver borrowed code from arch/arm/mach-davinci/clock.c and >> implemented the driver as per common clock provider API. The main PLL >> hardware typically has a multiplier, a pre-divider and a post-divider. >> Some of the SoCs has the divider fixed meaning they can not be >> configured through a register. HAS_PREDIV and HAS_POSTDIV flags are used >> to tell the driver if a hardware has these dividers present or not. >> Driver is configured through the struct clk_pll_data that has the >> SoC specific clock data. >> >> Signed-off-by: Murali Karicheri > This looks good to me. > Acked-by: Linus Walleij > > Yours, > Linus Walleij > > Linus, Thanks. I will add your Acked-by in the next revision of the patch. Murali From mboxrd@z Thu Jan 1 00:00:00 1970 From: m-karicheri2@ti.com (Murali Karicheri) Date: Wed, 31 Oct 2012 09:23:51 -0400 Subject: [PATCH v3 01/11] clk: davinci - add main PLL clock driver In-Reply-To: References: <1351181518-11882-1-git-send-email-m-karicheri2@ti.com> <1351181518-11882-2-git-send-email-m-karicheri2@ti.com> Message-ID: <50912667.9030909@ti.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 10/28/2012 03:18 PM, Linus Walleij wrote: > On Thu, Oct 25, 2012 at 6:11 PM, Murali Karicheri wrote: > >> This is the driver for the main PLL clock hardware found on DM SoCs. >> This driver borrowed code from arch/arm/mach-davinci/clock.c and >> implemented the driver as per common clock provider API. The main PLL >> hardware typically has a multiplier, a pre-divider and a post-divider. >> Some of the SoCs has the divider fixed meaning they can not be >> configured through a register. HAS_PREDIV and HAS_POSTDIV flags are used >> to tell the driver if a hardware has these dividers present or not. >> Driver is configured through the struct clk_pll_data that has the >> SoC specific clock data. >> >> Signed-off-by: Murali Karicheri > This looks good to me. > Acked-by: Linus Walleij > > Yours, > Linus Walleij > > Linus, Thanks. I will add your Acked-by in the next revision of the patch. Murali