From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.5 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A, SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B187CC433E1 for ; Wed, 26 Aug 2020 18:10:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8C74D2083B for ; Wed, 26 Aug 2020 18:10:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726609AbgHZSKE (ORCPT ); Wed, 26 Aug 2020 14:10:04 -0400 Received: from foss.arm.com ([217.140.110.172]:49658 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726442AbgHZSKD (ORCPT ); Wed, 26 Aug 2020 14:10:03 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 762C5101E; Wed, 26 Aug 2020 11:10:01 -0700 (PDT) Received: from [172.16.1.113] (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8293A3F71F; Wed, 26 Aug 2020 11:09:58 -0700 (PDT) Subject: Re: [PATCH] arm(64)/kvm: improve the documentation about HVC calls To: Pingfan Liu Cc: kvmarm@lists.cs.columbia.edu, Russell King , Marc Zyngier , Julien Thierry , Suzuki K Poulose , linux-doc@vger.kernel.org, linux-arm-kernel@lists.infradead.org References: <1597241133-3630-1-git-send-email-kernelfans@gmail.com> From: James Morse Message-ID: <50ccd1aa-797f-bc97-d675-8d6732d9ae06@arm.com> Date: Wed, 26 Aug 2020 19:09:56 +0100 User-Agent: Mozilla/5.0 (X11; Linux aarch64; rv:68.0) Gecko/20100101 Thunderbird/68.11.0 MIME-Version: 1.0 In-Reply-To: <1597241133-3630-1-git-send-email-kernelfans@gmail.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-GB Content-Transfer-Encoding: 7bit Sender: linux-doc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-doc@vger.kernel.org Hi Pingfan, On 12/08/2020 15:05, Pingfan Liu wrote: > Both arm and arm64 kernel entry point have the following prerequisite: > MMU = off, D-cache = off, I-cache = dont care. > > HVC_SOFT_RESTART call should meet this prerequisite before jumping to the > new kernel. I think you have this the wrong way up. This should describe what HVC_SOFT_RESTART does. We want to remove some extra work kexec does on arm64, and both implementations of HVC_SOFT_RESTART on arm64 already do what we need. The change here should be to document that the D/I bits are cleared after a HVC_SOFT_RESTART on arm64. > Furthermore, on arm64, el2_setup doesn't set I+C bits and keeps EL2 MMU > off, and KVM resets them when its unload. These are achieved by > HVC_RESET_VECTORS call. > > Improve the document. > diff --git a/Documentation/virt/kvm/arm/hyp-abi.rst b/Documentation/virt/kvm/arm/hyp-abi.rst > index d9eba93..a95bc30 100644 > --- a/Documentation/virt/kvm/arm/hyp-abi.rst > +++ b/Documentation/virt/kvm/arm/hyp-abi.rst > @@ -40,9 +40,9 @@ these functions (see arch/arm{,64}/include/asm/virt.h): > > * :: > > - r0/x0 = HVC_RESET_VECTORS > + x0 = HVC_RESET_VECTORS (arm64 only) > > - Turn HYP/EL2 MMU off, and reset HVBAR/VBAR_EL2 to the initials > + Disable HYP/EL2 MMU and D-cache, and reset HVBAR/VBAR_EL2 to the initials > stubs' exception vector value. This effectively disables an existing > hypervisor. I don't think we should remove this. KVM on 32bit was the only implementer, but if there ever is another, this is how it should work. > @@ -54,7 +54,7 @@ these functions (see arch/arm{,64}/include/asm/virt.h): > x3 = x1's value when entering the next payload (arm64) > x4 = x2's value when entering the next payload (arm64) > > - Mask all exceptions, disable the MMU, move the arguments into place > + Mask all exceptions, disable the MMU and D-cache, move the arguments into place > (arm64 only), and jump to the restart address while at HYP/EL2. This > hypercall is not expected to return to its caller. (I don't think disable the D-cache is what the bit does, it forces the attributes that are used for a data access). Please just describe this as the on arm64 the D and I bits are cleared. (it might be true on 32bit, I can't work the assembly out). Thanks, James From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.5 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A, SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 301DEC433DF for ; Wed, 26 Aug 2020 18:10:06 +0000 (UTC) Received: from mm01.cs.columbia.edu (mm01.cs.columbia.edu [128.59.11.253]) by mail.kernel.org (Postfix) with ESMTP id A31B3207DF for ; Wed, 26 Aug 2020 18:10:05 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A31B3207DF Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=kvmarm-bounces@lists.cs.columbia.edu Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 06D354BD23; Wed, 26 Aug 2020 14:10:05 -0400 (EDT) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id RhjZrudnW6Ut; Wed, 26 Aug 2020 14:10:03 -0400 (EDT) Received: from mm01.cs.columbia.edu (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id E0E3B4BB85; Wed, 26 Aug 2020 14:10:03 -0400 (EDT) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 52AA54BB3F for ; Wed, 26 Aug 2020 14:10:03 -0400 (EDT) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id liHaBwFbmSaa for ; Wed, 26 Aug 2020 14:10:02 -0400 (EDT) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 3842F4BB25 for ; Wed, 26 Aug 2020 14:10:02 -0400 (EDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 762C5101E; Wed, 26 Aug 2020 11:10:01 -0700 (PDT) Received: from [172.16.1.113] (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8293A3F71F; Wed, 26 Aug 2020 11:09:58 -0700 (PDT) Subject: Re: [PATCH] arm(64)/kvm: improve the documentation about HVC calls To: Pingfan Liu References: <1597241133-3630-1-git-send-email-kernelfans@gmail.com> From: James Morse Message-ID: <50ccd1aa-797f-bc97-d675-8d6732d9ae06@arm.com> Date: Wed, 26 Aug 2020 19:09:56 +0100 User-Agent: Mozilla/5.0 (X11; Linux aarch64; rv:68.0) Gecko/20100101 Thunderbird/68.11.0 MIME-Version: 1.0 In-Reply-To: <1597241133-3630-1-git-send-email-kernelfans@gmail.com> Content-Language: en-GB Cc: Marc Zyngier , linux-doc@vger.kernel.org, Russell King , linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu Hi Pingfan, On 12/08/2020 15:05, Pingfan Liu wrote: > Both arm and arm64 kernel entry point have the following prerequisite: > MMU = off, D-cache = off, I-cache = dont care. > > HVC_SOFT_RESTART call should meet this prerequisite before jumping to the > new kernel. I think you have this the wrong way up. This should describe what HVC_SOFT_RESTART does. We want to remove some extra work kexec does on arm64, and both implementations of HVC_SOFT_RESTART on arm64 already do what we need. The change here should be to document that the D/I bits are cleared after a HVC_SOFT_RESTART on arm64. > Furthermore, on arm64, el2_setup doesn't set I+C bits and keeps EL2 MMU > off, and KVM resets them when its unload. These are achieved by > HVC_RESET_VECTORS call. > > Improve the document. > diff --git a/Documentation/virt/kvm/arm/hyp-abi.rst b/Documentation/virt/kvm/arm/hyp-abi.rst > index d9eba93..a95bc30 100644 > --- a/Documentation/virt/kvm/arm/hyp-abi.rst > +++ b/Documentation/virt/kvm/arm/hyp-abi.rst > @@ -40,9 +40,9 @@ these functions (see arch/arm{,64}/include/asm/virt.h): > > * :: > > - r0/x0 = HVC_RESET_VECTORS > + x0 = HVC_RESET_VECTORS (arm64 only) > > - Turn HYP/EL2 MMU off, and reset HVBAR/VBAR_EL2 to the initials > + Disable HYP/EL2 MMU and D-cache, and reset HVBAR/VBAR_EL2 to the initials > stubs' exception vector value. This effectively disables an existing > hypervisor. I don't think we should remove this. KVM on 32bit was the only implementer, but if there ever is another, this is how it should work. > @@ -54,7 +54,7 @@ these functions (see arch/arm{,64}/include/asm/virt.h): > x3 = x1's value when entering the next payload (arm64) > x4 = x2's value when entering the next payload (arm64) > > - Mask all exceptions, disable the MMU, move the arguments into place > + Mask all exceptions, disable the MMU and D-cache, move the arguments into place > (arm64 only), and jump to the restart address while at HYP/EL2. This > hypercall is not expected to return to its caller. (I don't think disable the D-cache is what the bit does, it forces the attributes that are used for a data access). Please just describe this as the on arm64 the D and I bits are cleared. (it might be true on 32bit, I can't work the assembly out). Thanks, James _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9B6EDC433DF for ; Wed, 26 Aug 2020 18:11:57 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5BD6B2080C for ; Wed, 26 Aug 2020 18:11:57 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="MG8ktmME" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5BD6B2080C Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:Message-ID:From: References:To:Subject:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=+icVsMD5YcRLAl4DgsH9IOiSN54EjhK35ClYgD0KYlk=; b=MG8ktmMEl2EWzDcG9H0L0Xvr5 CkTZ/oiQ/6eJwYUQLsCHQRci/k9JKEM2L+WP7pVIkPV2mvLL7/vCSKBDtRXOepdioX+HXyp6/rMNC OihJeOqr5qXMmpz1pxRloS8P9znARQbWoEUoqrOgHTO5h/8L7pK8MevAVJ4kHDOKAOI0KasAMJWom ke+JlzecoFZMKxjgOrT51BN4qY/ZCY5vXcx8KQaKmX0ckOPxsHCyce1QPeVlZrkyKjXdumrwFTScn 8YTZtDTm7g/OA4cWiVIiOxWjjb6HrYzV6AXkqgJVU8QppzlXaxKVeZWuvD/nvGIjZkMPfHX/uV+6M rs2Rz8qTQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kAzsB-0000fW-Hh; Wed, 26 Aug 2020 18:10:11 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kAzs8-0000eo-Bv for linux-arm-kernel@lists.infradead.org; Wed, 26 Aug 2020 18:10:09 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 762C5101E; Wed, 26 Aug 2020 11:10:01 -0700 (PDT) Received: from [172.16.1.113] (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8293A3F71F; Wed, 26 Aug 2020 11:09:58 -0700 (PDT) Subject: Re: [PATCH] arm(64)/kvm: improve the documentation about HVC calls To: Pingfan Liu References: <1597241133-3630-1-git-send-email-kernelfans@gmail.com> From: James Morse Message-ID: <50ccd1aa-797f-bc97-d675-8d6732d9ae06@arm.com> Date: Wed, 26 Aug 2020 19:09:56 +0100 User-Agent: Mozilla/5.0 (X11; Linux aarch64; rv:68.0) Gecko/20100101 Thunderbird/68.11.0 MIME-Version: 1.0 In-Reply-To: <1597241133-3630-1-git-send-email-kernelfans@gmail.com> Content-Language: en-GB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200826_141008_471241_D23A3077 X-CRM114-Status: GOOD ( 22.61 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Suzuki K Poulose , Marc Zyngier , linux-doc@vger.kernel.org, Russell King , linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, Julien Thierry Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Pingfan, On 12/08/2020 15:05, Pingfan Liu wrote: > Both arm and arm64 kernel entry point have the following prerequisite: > MMU = off, D-cache = off, I-cache = dont care. > > HVC_SOFT_RESTART call should meet this prerequisite before jumping to the > new kernel. I think you have this the wrong way up. This should describe what HVC_SOFT_RESTART does. We want to remove some extra work kexec does on arm64, and both implementations of HVC_SOFT_RESTART on arm64 already do what we need. The change here should be to document that the D/I bits are cleared after a HVC_SOFT_RESTART on arm64. > Furthermore, on arm64, el2_setup doesn't set I+C bits and keeps EL2 MMU > off, and KVM resets them when its unload. These are achieved by > HVC_RESET_VECTORS call. > > Improve the document. > diff --git a/Documentation/virt/kvm/arm/hyp-abi.rst b/Documentation/virt/kvm/arm/hyp-abi.rst > index d9eba93..a95bc30 100644 > --- a/Documentation/virt/kvm/arm/hyp-abi.rst > +++ b/Documentation/virt/kvm/arm/hyp-abi.rst > @@ -40,9 +40,9 @@ these functions (see arch/arm{,64}/include/asm/virt.h): > > * :: > > - r0/x0 = HVC_RESET_VECTORS > + x0 = HVC_RESET_VECTORS (arm64 only) > > - Turn HYP/EL2 MMU off, and reset HVBAR/VBAR_EL2 to the initials > + Disable HYP/EL2 MMU and D-cache, and reset HVBAR/VBAR_EL2 to the initials > stubs' exception vector value. This effectively disables an existing > hypervisor. I don't think we should remove this. KVM on 32bit was the only implementer, but if there ever is another, this is how it should work. > @@ -54,7 +54,7 @@ these functions (see arch/arm{,64}/include/asm/virt.h): > x3 = x1's value when entering the next payload (arm64) > x4 = x2's value when entering the next payload (arm64) > > - Mask all exceptions, disable the MMU, move the arguments into place > + Mask all exceptions, disable the MMU and D-cache, move the arguments into place > (arm64 only), and jump to the restart address while at HYP/EL2. This > hypercall is not expected to return to its caller. (I don't think disable the D-cache is what the bit does, it forces the attributes that are used for a data access). Please just describe this as the on arm64 the D and I bits are cleared. (it might be true on 32bit, I can't work the assembly out). Thanks, James _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel