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Fri, 14 Jan 2022 12:59:02 +0000 Received: from PH0PR11MB5658.namprd11.prod.outlook.com ([fe80::e504:eb88:49e1:fec5]) by PH0PR11MB5658.namprd11.prod.outlook.com ([fe80::e504:eb88:49e1:fec5%7]) with mapi id 15.20.4888.012; Fri, 14 Jan 2022 12:59:02 +0000 Subject: Re: [PATCH 3/3] intel-iommu: PASID support To: Jason Wang , Peter Xu References: <20220105041945.13459-1-jasowang@redhat.com> <20220105041945.13459-5-jasowang@redhat.com> <8beffd3d-5eff-6462-ce23-faf44c6653f1@redhat.com> From: Liu Yi L Message-ID: <51098548-51f0-04c8-2169-9ce3d43678a6@intel.com> Date: Fri, 14 Jan 2022 20:58:40 +0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Firefox/78.0 Thunderbird/78.14.0 In-Reply-To: Content-Type: text/plain; charset="utf-8"; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-ClientProxiedBy: HK2PR04CA0079.apcprd04.prod.outlook.com (2603:1096:202:15::23) To PH0PR11MB5658.namprd11.prod.outlook.com (2603:10b6:510:e2::23) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 65625a8d-844d-4074-2651-08d9d75da322 X-MS-TrafficTypeDiagnostic: DM6PR11MB3146:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:10000; 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envelope-from=yi.l.liu@intel.com; helo=mga05.intel.com X-Spam_score_int: -49 X-Spam_score: -5.0 X-Spam_bar: ----- X-Spam_report: (-5.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.595, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: yi.y.sun@linux.intel.com, qemu-devel , mst Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 2022/1/14 15:22, Jason Wang wrote: > On Fri, Jan 14, 2022 at 3:13 PM Peter Xu wrote: >> >> On Fri, Jan 14, 2022 at 01:58:07PM +0800, Jason Wang wrote: >>>>> Right, but I think you meant to do this only when scalable mode is disabled. >>>> >>>> Yes IMHO it will definitely suite for !scalable case since that's exactly what >>>> we did before. What I'm also wondering is even if scalable is enabled but no >>>> "real" pasid is used, so if all the translations go through the default pasid >>>> that stored in the device context entry, then maybe we can ignore checking it. >>>> The latter is the "hacky" part mentioned above. >>> >>> The problem I see is that we can't know what PASID is used as default >>> without reading the context entry? >> >> Can the default NO_PASID being used in mixture of !NO_PASID use case on the >> same device? If that's possible, then I agree.. > > My understanding is that it is possible. > >> >> My previous idea should be based on the fact that if NO_PASID is used on one >> device, then all translations will be based on NO_PASID, but now I'm not sure >> of it. > > Actually, what I meant is: > > device 1 using transactions without PASID with RID2PASID 1 > device 2 using transactions without PASID with RID2PASID 2 Interesting series, Jason. haven't read through all your code yet. Just a quick comment. The RID2PASID1 and RID2PASID2 may be the same one. Vt-d spec has defined a RPS bit in ecap register. If it is reported as 0, that means the RID_PASID (previously it is called RID2PASID :-)) field of scalable mode context entry is not supported, a PASID value of 0 will be used for transactions wihout PASID. So in the code, you may check the RPS bit to see if the RID_PASID value are the same for all devices. Regards, Yi Liu > Then we can't assume a default pasid here. > >> >>> >>>> >>>> The other thing to mention is, if we postpone the iotlb lookup to be after >>>> context entry, then logically we can have per-device iotlb, that means we can >>>> replace IntelIOMMUState.iotlb with VTDAddressSpace.iotlb in the future, too, >>>> which can also be more efficient. >>> >>> Right but we still need to limit the total slots and ATS is a better >>> way to deal with the IOTLB bottleneck actually. >> >> I think it depends on how the iotlb ghash is implemented. Logically I think if >> we can split the cache to per-device it'll be slightly better because we don't >> need to iterate over iotlbs of other devices when lookup anymore; meanwhile >> each iotlb takes less space too (no devfn needed anymore). > > So we've already used sid in the IOTLB hash, I wonder how much we can > gain form this. > > Thanks > >> >> Thanks, >> >> -- >> Peter Xu >> > -- Regards, Yi Liu