From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stephen Boyd Subject: Re: [PATCH 3/3] ARM: Work around faulty ISAR0 register in some Krait CPUs Date: Mon, 18 Mar 2013 10:03:49 -0700 Message-ID: <514748F5.70504@codeaurora.org> References: <1363138321-27849-1-git-send-email-sboyd@codeaurora.org> <1363138321-27849-4-git-send-email-sboyd@codeaurora.org> <20130317142854.GC19071@mudshark.cambridge.arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-path: Received: from wolverine01.qualcomm.com ([199.106.114.254]:16608 "EHLO wolverine01.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752781Ab3CRRDt (ORCPT ); Mon, 18 Mar 2013 13:03:49 -0400 In-Reply-To: <20130317142854.GC19071@mudshark.cambridge.arm.com> Sender: linux-arm-msm-owner@vger.kernel.org List-Id: linux-arm-msm@vger.kernel.org To: Will Deacon Cc: "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "linux-arm-msm@vger.kernel.org" , Stepan Moskovchenko On 03/17/13 07:28, Will Deacon wrote: > On Wed, Mar 13, 2013 at 01:32:01AM +0000, Stephen Boyd wrote: >> Some early versions of the Krait CPU design incorrectly indicate >> that they only support the UDIV and SDIV instructions in Thumb >> mode when they actually support them in ARM and Thumb mode. It >> seems that these CPUs follow the DDI0406B ARM ARM which has two >> possible values for the divide instructions field, instead of the >> DDI0406C document which has three possible values. >> >> Work around this problem by checking the MIDR against Krait CPUs >> with this faulty ISAR0 register and force the detection code >> to indicate support in both modes. >> >> Cc: Will Deacon >> Cc: Stepan Moskovchenko >> Signed-off-by: Stephen Boyd >> --- >> arch/arm/kernel/setup.c | 8 ++++++++ >> 1 file changed, 8 insertions(+) > After all this, you might as well just pass the relevant HWCAPs for your > krait entry in proc-v7.S rather than have an exception in the CPU-agnostic > code. Ok. Care to ack the previous patch I sent then? -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754158Ab3CRRDv (ORCPT ); Mon, 18 Mar 2013 13:03:51 -0400 Received: from wolverine01.qualcomm.com ([199.106.114.254]:16608 "EHLO wolverine01.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752781Ab3CRRDt (ORCPT ); Mon, 18 Mar 2013 13:03:49 -0400 X-IronPort-AV: E=Sophos;i="4.84,865,1355126400"; d="scan'208";a="30368545" Message-ID: <514748F5.70504@codeaurora.org> Date: Mon, 18 Mar 2013 10:03:49 -0700 From: Stephen Boyd User-Agent: Mozilla/5.0 (X11; Linux i686 on x86_64; rv:17.0) Gecko/20130307 Thunderbird/17.0.4 MIME-Version: 1.0 To: Will Deacon CC: "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "linux-arm-msm@vger.kernel.org" , Stepan Moskovchenko Subject: Re: [PATCH 3/3] ARM: Work around faulty ISAR0 register in some Krait CPUs References: <1363138321-27849-1-git-send-email-sboyd@codeaurora.org> <1363138321-27849-4-git-send-email-sboyd@codeaurora.org> <20130317142854.GC19071@mudshark.cambridge.arm.com> In-Reply-To: <20130317142854.GC19071@mudshark.cambridge.arm.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 03/17/13 07:28, Will Deacon wrote: > On Wed, Mar 13, 2013 at 01:32:01AM +0000, Stephen Boyd wrote: >> Some early versions of the Krait CPU design incorrectly indicate >> that they only support the UDIV and SDIV instructions in Thumb >> mode when they actually support them in ARM and Thumb mode. It >> seems that these CPUs follow the DDI0406B ARM ARM which has two >> possible values for the divide instructions field, instead of the >> DDI0406C document which has three possible values. >> >> Work around this problem by checking the MIDR against Krait CPUs >> with this faulty ISAR0 register and force the detection code >> to indicate support in both modes. >> >> Cc: Will Deacon >> Cc: Stepan Moskovchenko >> Signed-off-by: Stephen Boyd >> --- >> arch/arm/kernel/setup.c | 8 ++++++++ >> 1 file changed, 8 insertions(+) > After all this, you might as well just pass the relevant HWCAPs for your > krait entry in proc-v7.S rather than have an exception in the CPU-agnostic > code. Ok. Care to ack the previous patch I sent then? -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation From mboxrd@z Thu Jan 1 00:00:00 1970 From: sboyd@codeaurora.org (Stephen Boyd) Date: Mon, 18 Mar 2013 10:03:49 -0700 Subject: [PATCH 3/3] ARM: Work around faulty ISAR0 register in some Krait CPUs In-Reply-To: <20130317142854.GC19071@mudshark.cambridge.arm.com> References: <1363138321-27849-1-git-send-email-sboyd@codeaurora.org> <1363138321-27849-4-git-send-email-sboyd@codeaurora.org> <20130317142854.GC19071@mudshark.cambridge.arm.com> Message-ID: <514748F5.70504@codeaurora.org> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 03/17/13 07:28, Will Deacon wrote: > On Wed, Mar 13, 2013 at 01:32:01AM +0000, Stephen Boyd wrote: >> Some early versions of the Krait CPU design incorrectly indicate >> that they only support the UDIV and SDIV instructions in Thumb >> mode when they actually support them in ARM and Thumb mode. It >> seems that these CPUs follow the DDI0406B ARM ARM which has two >> possible values for the divide instructions field, instead of the >> DDI0406C document which has three possible values. >> >> Work around this problem by checking the MIDR against Krait CPUs >> with this faulty ISAR0 register and force the detection code >> to indicate support in both modes. >> >> Cc: Will Deacon >> Cc: Stepan Moskovchenko >> Signed-off-by: Stephen Boyd >> --- >> arch/arm/kernel/setup.c | 8 ++++++++ >> 1 file changed, 8 insertions(+) > After all this, you might as well just pass the relevant HWCAPs for your > krait entry in proc-v7.S rather than have an exception in the CPU-agnostic > code. Ok. Care to ack the previous patch I sent then? -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation