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([2001:b07:6468:f312:7848:99b4:482a:e888]) by smtp.gmail.com with ESMTPSA id r18sm28608611wro.13.2020.03.24.04.19.06 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 24 Mar 2020 04:19:06 -0700 (PDT) Subject: Re: [PATCH v3 33/37] KVM: nVMX: Skip MMU sync on nested VMX transition when possible To: Sean Christopherson Cc: Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Joerg Roedel , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Ben Gardon , Junaid Shahid , Liran Alon , Boris Ostrovsky , John Haxby , Miaohe Lin , Tom Lendacky References: <20200320212833.3507-1-sean.j.christopherson@intel.com> <20200320212833.3507-34-sean.j.christopherson@intel.com> From: Paolo Bonzini Message-ID: <51707375-51a6-637e-ebc5-f63f1c81f6b1@redhat.com> Date: Tue, 24 Mar 2020 12:19:05 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.5.0 MIME-Version: 1.0 In-Reply-To: <20200320212833.3507-34-sean.j.christopherson@intel.com> Content-Type: text/plain; charset=windows-1252 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 20/03/20 22:28, Sean Christopherson wrote: > Skip the MMU sync when reusing a cached root if EPT is enabled or L1 > enabled VPID for L2. > > If EPT is enabled, guest-physical mappings aren't flushed even if VPID > is disabled, i.e. L1 can't expect stale TLB entries to be flushed if it > has enabled EPT and L0 isn't shadowing PTEs (for L1 or L2) if L1 has > EPT disabled. > > If VPID is enabled (and EPT is disabled), then L1 can't expect stale TLB > entries to be flushed (for itself or L2). > > Signed-off-by: Sean Christopherson Great, just a small rephrasing here and there: /* * Returns true if the MMU needs to be sync'd on nested VM-Enter/VM-Exit. * tl;dr: the MMU needs a sync if L0 is using shadow paging and L1 didn't * enable VPID for L2 (implying it expects a TLB flush on VMX transitions). * Here's why. * * If EPT is enabled by L0 a sync is never needed: * - if it is disabled by L1, then L0 is not shadowing L1 or L2 PTEs, there * cannot be unsync'd SPTEs for either L1 or L2. * * - if it is also enabled by L1, then L0 doesn't need to sync on VM-Enter * VM-Enter as VM-Enter isn't required to invalidate guest-physical mappings * (irrespective of VPID), i.e. L1 can't rely on the (virtual) CPU to flush * stale guest-physical mappings for L2 from the TLB. And as above, L0 isn't * shadowing L1 PTEs so there are no unsync'd SPTEs to sync on VM-Exit. * * If EPT is disabled by L0: * - if VPID is enabled by L1 (for L2), the situation is similar to when L1 * enables EPT: L0 doesn't need to sync as VM-Enter and VM-Exit aren't * required to invalidate linear mappings (EPT is disabled so there are * no combined or guest-physical mappings), i.e. L1 can't rely on the * (virtual) CPU to flush stale linear mappings for either L2 or itself (L1). * * - however if VPID is disabled by L1, then a sync is needed as L1 expects all * linear mappings (EPT is disabled so there are no combined or guest-physical * mappings) to be invalidated on both VM-Enter and VM-Exit. * * Note, this logic is subtly different than nested_has_guest_tlb_tag(), which * additionally checks that L2 has been assigned a VPID (when EPT is disabled). * Whether or not L2 has been assigned a VPID by L0 is irrelevant with respect * to L1's expectations, e.g. L0 needs to invalidate hardware TLB entries if L2 * doesn't have a unique VPID to prevent reusing L1's entries (assuming L1 has * been assigned a VPID), but L0 doesn't need to do a MMU sync because L1 * doesn't expect stale (virtual) TLB entries to be flushed, i.e. L1 doesn't * know that L0 will flush the TLB and so L1 will do INVVPID as needed to flush * stale TLB entries, at which point L0 will sync L2's MMU. */ Paolo