From mboxrd@z Thu Jan 1 00:00:00 1970 From: Icenowy Zheng Subject: Re: [PATCH v3 01/11] dt-bindings: add binding for the Allwinner DE2 CCU Date: Tue, 4 Apr 2017 00:18:08 +0800 Message-ID: <517f0d78-7b43-7e5b-5ad0-c51743639172@aosc.io> References: <20170329194613.55548-1-icenowy@aosc.io> <20170329194613.55548-2-icenowy@aosc.io> <20170403153323.kmq3ku7h3sj7fp4g@rob-hp-laptop> Reply-To: icenowy-h8G6r0blFSE@public.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: quoted-printable Return-path: Sender: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org In-Reply-To: <20170403153323.kmq3ku7h3sj7fp4g@rob-hp-laptop> List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: Rob Herring Cc: Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org, linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org, Icenowy Zheng List-Id: devicetree@vger.kernel.org =E5=9C=A8 2017=E5=B9=B404=E6=9C=8803=E6=97=A5 23:33, Rob Herring =E5=86=99= =E9=81=93: > On Thu, Mar 30, 2017 at 03:46:03AM +0800, Icenowy Zheng wrote: >> From: Icenowy Zheng >> >> Allwinner "Display Engine 2.0" contains some clock controls in it. >> >> In order to add them as clock drivers, we need a device tree binding. >> Add the binding here. >> >> Signed-off-by: Icenowy Zheng >> --- >> Changes in v3: >> - Fill the address space length of DE2 CCU to 0x100000, just reach the s= tart of mixer0. > > Why? You waste virtual memory space making this bigger than it needs to > be. Not an issue so much for 64-bit. > >> >> .../devicetree/bindings/clock/sun8i-de2.txt | 31 +++++++++++++++= +++++++ >> 1 file changed, 31 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/clock/sun8i-de2.tx= t >> >> diff --git a/Documentation/devicetree/bindings/clock/sun8i-de2.txt b/Doc= umentation/devicetree/bindings/clock/sun8i-de2.txt >> new file mode 100644 >> index 000000000000..34cf79c05f13 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/clock/sun8i-de2.txt >> @@ -0,0 +1,31 @@ >> +Allwinner Display Engine 2.0 Clock Control Binding >> +-------------------------------------------------- >> + >> +Required properties : >> +- compatible: must contain one of the following compatibles: >> + - "allwinner,sun8i-a83t-de2-clk" >> + - "allwinner,sun50i-a64-de2-clk" >> + - "allwinner,sun50i-h5-de2-clk" >> + >> +- reg: Must contain the registers base address and length >> +- clocks: phandle to the clocks feeding the display engine subsystem. >> + Three are needed: >> + - "mod": the display engine module clock >> + - "bus": the bus clock for the whole display engine subsystem >> +- clock-names: Must contain the clock names described just above >> +- resets: phandle to the reset control for the display engine subsystem= . >> +- #clock-cells : must contain 1 >> +- #reset-cells : must contain 1 >> + >> +Example: >> +de2_clocks: clock@01000000 { > > Drop the leading 0s. dtc in linux-next will now warn on this with W=3D1 > compile. Looks like sunxi has a lot of them. Please fix so we don't keep > repeating this same copy-n-paste. Thanks ;-) I will try to kill them all ;-) > >> + compatible =3D "allwinner,sun50i-a64-de2-clk"; >> + reg =3D <0x01000000 0x100000>; >> + clocks =3D <&ccu CLK_DE>, >> + <&ccu CLK_BUS_DE>; >> + clock-names =3D "mod", >> + "bus"; >> + resets =3D <&ccu RST_BUS_DE>; >> + #clock-cells =3D <1>; >> + #reset-cells =3D <1>; >> +}; >> -- >> 2.12.0 >> --=20 You received this message because you are subscribed to the Google Groups "= linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an e= mail to linux-sunxi+unsubscribe-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0@public.gmane.org For more options, visit https://groups.google.com/d/optout. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Subject: Re: [PATCH v3 01/11] dt-bindings: add binding for the Allwinner DE2 CCU To: Rob Herring References: <20170329194613.55548-1-icenowy@aosc.io> <20170329194613.55548-2-icenowy@aosc.io> <20170403153323.kmq3ku7h3sj7fp4g@rob-hp-laptop> From: Icenowy Zheng Message-ID: <517f0d78-7b43-7e5b-5ad0-c51743639172@aosc.io> Date: Tue, 4 Apr 2017 00:18:08 +0800 MIME-Version: 1.0 In-Reply-To: <20170403153323.kmq3ku7h3sj7fp4g@rob-hp-laptop> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Jernej Skrabec , linux-sunxi@googlegroups.com, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Chen-Yu Tsai , Icenowy Zheng , Maxime Ripard , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="utf-8"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+mturquette=baylibre.com@lists.infradead.org List-ID: CgrlnKggMjAxN+W5tDA05pyIMDPml6UgMjM6MzMsIFJvYiBIZXJyaW5nIOWGmemBkzoKPiBPbiBU aHUsIE1hciAzMCwgMjAxNyBhdCAwMzo0NjowM0FNICswODAwLCBJY2Vub3d5IFpoZW5nIHdyb3Rl Ogo+PiBGcm9tOiBJY2Vub3d5IFpoZW5nIDxpY2Vub3d5QGFvc2MueHl6Pgo+Pgo+PiBBbGx3aW5u ZXIgIkRpc3BsYXkgRW5naW5lIDIuMCIgY29udGFpbnMgc29tZSBjbG9jayBjb250cm9scyBpbiBp dC4KPj4KPj4gSW4gb3JkZXIgdG8gYWRkIHRoZW0gYXMgY2xvY2sgZHJpdmVycywgd2UgbmVlZCBh IGRldmljZSB0cmVlIGJpbmRpbmcuCj4+IEFkZCB0aGUgYmluZGluZyBoZXJlLgo+Pgo+PiBTaWdu ZWQtb2ZmLWJ5OiBJY2Vub3d5IFpoZW5nIDxpY2Vub3d5QGFvc2MueHl6Pgo+PiAtLS0KPj4gQ2hh bmdlcyBpbiB2MzoKPj4gLSBGaWxsIHRoZSBhZGRyZXNzIHNwYWNlIGxlbmd0aCBvZiBERTIgQ0NV IHRvIDB4MTAwMDAwLCBqdXN0IHJlYWNoIHRoZSBzdGFydCBvZiBtaXhlcjAuCj4KPiBXaHk/IFlv dSB3YXN0ZSB2aXJ0dWFsIG1lbW9yeSBzcGFjZSBtYWtpbmcgdGhpcyBiaWdnZXIgdGhhbiBpdCBu ZWVkcyB0bwo+IGJlLiBOb3QgYW4gaXNzdWUgc28gbXVjaCBmb3IgNjQtYml0Lgo+Cj4+Cj4+ICAu Li4vZGV2aWNldHJlZS9iaW5kaW5ncy9jbG9jay9zdW44aS1kZTIudHh0ICAgICAgICB8IDMxICsr KysrKysrKysrKysrKysrKysrKysKPj4gIDEgZmlsZSBjaGFuZ2VkLCAzMSBpbnNlcnRpb25zKCsp Cj4+ICBjcmVhdGUgbW9kZSAxMDA2NDQgRG9jdW1lbnRhdGlvbi9kZXZpY2V0cmVlL2JpbmRpbmdz L2Nsb2NrL3N1bjhpLWRlMi50eHQKPj4KPj4gZGlmZiAtLWdpdCBhL0RvY3VtZW50YXRpb24vZGV2 aWNldHJlZS9iaW5kaW5ncy9jbG9jay9zdW44aS1kZTIudHh0IGIvRG9jdW1lbnRhdGlvbi9kZXZp Y2V0cmVlL2JpbmRpbmdzL2Nsb2NrL3N1bjhpLWRlMi50eHQKPj4gbmV3IGZpbGUgbW9kZSAxMDA2 NDQKPj4gaW5kZXggMDAwMDAwMDAwMDAwLi4zNGNmNzljMDVmMTMKPj4gLS0tIC9kZXYvbnVsbAo+ PiArKysgYi9Eb2N1bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGluZ3MvY2xvY2svc3VuOGktZGUy LnR4dAo+PiBAQCAtMCwwICsxLDMxIEBACj4+ICtBbGx3aW5uZXIgRGlzcGxheSBFbmdpbmUgMi4w IENsb2NrIENvbnRyb2wgQmluZGluZwo+PiArLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0t LS0tLS0tLS0tLS0tLS0tLS0tLS0KPj4gKwo+PiArUmVxdWlyZWQgcHJvcGVydGllcyA6Cj4+ICst IGNvbXBhdGlibGU6IG11c3QgY29udGFpbiBvbmUgb2YgdGhlIGZvbGxvd2luZyBjb21wYXRpYmxl czoKPj4gKwkJLSAiYWxsd2lubmVyLHN1bjhpLWE4M3QtZGUyLWNsayIKPj4gKwkJLSAiYWxsd2lu bmVyLHN1bjUwaS1hNjQtZGUyLWNsayIKPj4gKwkJLSAiYWxsd2lubmVyLHN1bjUwaS1oNS1kZTIt Y2xrIgo+PiArCj4+ICstIHJlZzogTXVzdCBjb250YWluIHRoZSByZWdpc3RlcnMgYmFzZSBhZGRy ZXNzIGFuZCBsZW5ndGgKPj4gKy0gY2xvY2tzOiBwaGFuZGxlIHRvIHRoZSBjbG9ja3MgZmVlZGlu ZyB0aGUgZGlzcGxheSBlbmdpbmUgc3Vic3lzdGVtLgo+PiArCSAgVGhyZWUgYXJlIG5lZWRlZDoK Pj4gKyAgLSAibW9kIjogdGhlIGRpc3BsYXkgZW5naW5lIG1vZHVsZSBjbG9jawo+PiArICAtICJi dXMiOiB0aGUgYnVzIGNsb2NrIGZvciB0aGUgd2hvbGUgZGlzcGxheSBlbmdpbmUgc3Vic3lzdGVt Cj4+ICstIGNsb2NrLW5hbWVzOiBNdXN0IGNvbnRhaW4gdGhlIGNsb2NrIG5hbWVzIGRlc2NyaWJl ZCBqdXN0IGFib3ZlCj4+ICstIHJlc2V0czogcGhhbmRsZSB0byB0aGUgcmVzZXQgY29udHJvbCBm b3IgdGhlIGRpc3BsYXkgZW5naW5lIHN1YnN5c3RlbS4KPj4gKy0gI2Nsb2NrLWNlbGxzIDogbXVz dCBjb250YWluIDEKPj4gKy0gI3Jlc2V0LWNlbGxzIDogbXVzdCBjb250YWluIDEKPj4gKwo+PiAr RXhhbXBsZToKPj4gK2RlMl9jbG9ja3M6IGNsb2NrQDAxMDAwMDAwIHsKPgo+IERyb3AgdGhlIGxl YWRpbmcgMHMuIGR0YyBpbiBsaW51eC1uZXh0IHdpbGwgbm93IHdhcm4gb24gdGhpcyB3aXRoIFc9 MQo+IGNvbXBpbGUuIExvb2tzIGxpa2Ugc3VueGkgaGFzIGEgbG90IG9mIHRoZW0uIFBsZWFzZSBm aXggc28gd2UgZG9uJ3Qga2VlcAo+IHJlcGVhdGluZyB0aGlzIHNhbWUgY29weS1uLXBhc3RlLgoK VGhhbmtzIDstKQoKSSB3aWxsIHRyeSB0byBraWxsIHRoZW0gYWxsIDstKQoKPgo+PiArCWNvbXBh dGlibGUgPSAiYWxsd2lubmVyLHN1bjUwaS1hNjQtZGUyLWNsayI7Cj4+ICsJcmVnID0gPDB4MDEw MDAwMDAgMHgxMDAwMDA+Owo+PiArCWNsb2NrcyA9IDwmY2N1IENMS19ERT4sCj4+ICsJCSA8JmNj dSBDTEtfQlVTX0RFPjsKPj4gKwljbG9jay1uYW1lcyA9ICJtb2QiLAo+PiArCQkgICAgICAiYnVz IjsKPj4gKwlyZXNldHMgPSA8JmNjdSBSU1RfQlVTX0RFPjsKPj4gKwkjY2xvY2stY2VsbHMgPSA8 MT47Cj4+ICsJI3Jlc2V0LWNlbGxzID0gPDE+Owo+PiArfTsKPj4gLS0KPj4gMi4xMi4wCj4+Cgpf X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpsaW51eC1hcm0t a2VybmVsIG1haWxpbmcgbGlzdApsaW51eC1hcm0ta2VybmVsQGxpc3RzLmluZnJhZGVhZC5vcmcK aHR0cDovL2xpc3RzLmluZnJhZGVhZC5vcmcvbWFpbG1hbi9saXN0aW5mby9saW51eC1hcm0ta2Vy bmVsCg== From mboxrd@z Thu Jan 1 00:00:00 1970 From: icenowy@aosc.io (Icenowy Zheng) Date: Tue, 4 Apr 2017 00:18:08 +0800 Subject: [PATCH v3 01/11] dt-bindings: add binding for the Allwinner DE2 CCU In-Reply-To: <20170403153323.kmq3ku7h3sj7fp4g@rob-hp-laptop> References: <20170329194613.55548-1-icenowy@aosc.io> <20170329194613.55548-2-icenowy@aosc.io> <20170403153323.kmq3ku7h3sj7fp4g@rob-hp-laptop> Message-ID: <517f0d78-7b43-7e5b-5ad0-c51743639172@aosc.io> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org ? 2017?04?03? 23:33, Rob Herring ??: > On Thu, Mar 30, 2017 at 03:46:03AM +0800, Icenowy Zheng wrote: >> From: Icenowy Zheng >> >> Allwinner "Display Engine 2.0" contains some clock controls in it. >> >> In order to add them as clock drivers, we need a device tree binding. >> Add the binding here. >> >> Signed-off-by: Icenowy Zheng >> --- >> Changes in v3: >> - Fill the address space length of DE2 CCU to 0x100000, just reach the start of mixer0. > > Why? You waste virtual memory space making this bigger than it needs to > be. Not an issue so much for 64-bit. > >> >> .../devicetree/bindings/clock/sun8i-de2.txt | 31 ++++++++++++++++++++++ >> 1 file changed, 31 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/clock/sun8i-de2.txt >> >> diff --git a/Documentation/devicetree/bindings/clock/sun8i-de2.txt b/Documentation/devicetree/bindings/clock/sun8i-de2.txt >> new file mode 100644 >> index 000000000000..34cf79c05f13 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/clock/sun8i-de2.txt >> @@ -0,0 +1,31 @@ >> +Allwinner Display Engine 2.0 Clock Control Binding >> +-------------------------------------------------- >> + >> +Required properties : >> +- compatible: must contain one of the following compatibles: >> + - "allwinner,sun8i-a83t-de2-clk" >> + - "allwinner,sun50i-a64-de2-clk" >> + - "allwinner,sun50i-h5-de2-clk" >> + >> +- reg: Must contain the registers base address and length >> +- clocks: phandle to the clocks feeding the display engine subsystem. >> + Three are needed: >> + - "mod": the display engine module clock >> + - "bus": the bus clock for the whole display engine subsystem >> +- clock-names: Must contain the clock names described just above >> +- resets: phandle to the reset control for the display engine subsystem. >> +- #clock-cells : must contain 1 >> +- #reset-cells : must contain 1 >> + >> +Example: >> +de2_clocks: clock at 01000000 { > > Drop the leading 0s. dtc in linux-next will now warn on this with W=1 > compile. Looks like sunxi has a lot of them. Please fix so we don't keep > repeating this same copy-n-paste. Thanks ;-) I will try to kill them all ;-) > >> + compatible = "allwinner,sun50i-a64-de2-clk"; >> + reg = <0x01000000 0x100000>; >> + clocks = <&ccu CLK_DE>, >> + <&ccu CLK_BUS_DE>; >> + clock-names = "mod", >> + "bus"; >> + resets = <&ccu RST_BUS_DE>; >> + #clock-cells = <1>; >> + #reset-cells = <1>; >> +}; >> -- >> 2.12.0 >>