From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stephen Warren Subject: Re: [PATCH 0/2] PLL m,n,p init from SoC files Date: Wed, 05 Jun 2013 10:25:24 -0600 Message-ID: <51AF6674.3020701@wwwdotorg.org> References: <1370440301-3562-1-git-send-email-pdeschrijver@nvidia.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1370440301-3562-1-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> Sender: linux-tegra-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Peter De Schrijver Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org, Prashant Gaikwad , Thierry Reding , linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: linux-tegra@vger.kernel.org On 06/05/2013 07:51 AM, Peter De Schrijver wrote: > The m,n,p fields don't have the same bit offset and width across all PLLs. > This patchset allows SoC specific files to indicate the offset and width. > It also provides the data for Tegra114. The series, Tested-by: Stephen Warren Acked-by: Stephen Warren From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756607Ab3FEQZ3 (ORCPT ); Wed, 5 Jun 2013 12:25:29 -0400 Received: from avon.wwwdotorg.org ([70.85.31.133]:51536 "EHLO avon.wwwdotorg.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756521Ab3FEQZ1 (ORCPT ); Wed, 5 Jun 2013 12:25:27 -0400 Message-ID: <51AF6674.3020701@wwwdotorg.org> Date: Wed, 05 Jun 2013 10:25:24 -0600 From: Stephen Warren User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130510 Thunderbird/17.0.6 MIME-Version: 1.0 To: Peter De Schrijver CC: linux-arm-kernel@lists.infradead.org, mturquette@linaro.org, Prashant Gaikwad , Thierry Reding , linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 0/2] PLL m,n,p init from SoC files References: <1370440301-3562-1-git-send-email-pdeschrijver@nvidia.com> In-Reply-To: <1370440301-3562-1-git-send-email-pdeschrijver@nvidia.com> X-Enigmail-Version: 1.4.6 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 06/05/2013 07:51 AM, Peter De Schrijver wrote: > The m,n,p fields don't have the same bit offset and width across all PLLs. > This patchset allows SoC specific files to indicate the offset and width. > It also provides the data for Tegra114. The series, Tested-by: Stephen Warren Acked-by: Stephen Warren From mboxrd@z Thu Jan 1 00:00:00 1970 From: swarren@wwwdotorg.org (Stephen Warren) Date: Wed, 05 Jun 2013 10:25:24 -0600 Subject: [PATCH 0/2] PLL m,n,p init from SoC files In-Reply-To: <1370440301-3562-1-git-send-email-pdeschrijver@nvidia.com> References: <1370440301-3562-1-git-send-email-pdeschrijver@nvidia.com> Message-ID: <51AF6674.3020701@wwwdotorg.org> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 06/05/2013 07:51 AM, Peter De Schrijver wrote: > The m,n,p fields don't have the same bit offset and width across all PLLs. > This patchset allows SoC specific files to indicate the offset and width. > It also provides the data for Tegra114. The series, Tested-by: Stephen Warren Acked-by: Stephen Warren