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([2001:b07:6468:f312:e1d2:138e:4eff:42cb]) by smtp.gmail.com with ESMTPSA id m65sm7644751wmf.17.2020.06.19.16.07.49 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 19 Jun 2020 16:07:49 -0700 (PDT) Subject: Re: [PATCH v2 00/11] KVM: Support guest MAXPHYADDR < host MAXPHYADDR To: Tom Lendacky , Mohammed Gamal , kvm@vger.kernel.org Cc: linux-kernel@vger.kernel.org, vkuznets@redhat.com, sean.j.christopherson@intel.com, wanpengli@tencent.com, jmattson@google.com, joro@8bytes.org, babu.moger@amd.com References: <20200619153925.79106-1-mgamal@redhat.com> <5a52fd65-e1b2-ca87-e923-1d5ac167cfb9@amd.com> From: Paolo Bonzini Message-ID: <52295811-f78a-46c5-ff9e-23709ba95a3d@redhat.com> Date: Sat, 20 Jun 2020 01:07:49 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.6.0 MIME-Version: 1.0 In-Reply-To: <5a52fd65-e1b2-ca87-e923-1d5ac167cfb9@amd.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 19/06/20 23:52, Tom Lendacky wrote: >> A more subtle issue is when the host MAXPHYADDR is larger than that >> of the guest. Page faults caused by reserved bits on the guest won't >> cause an EPT violation/NPF and hence we also check guest MAXPHYADDR >> and add PFERR_RSVD_MASK error code to the page fault if needed. > > I'm probably missing something here, but I'm confused by this > statement. Is this for a case where a page has been marked not > present and the guest has also set what it believes are reserved > bits? Then when the page is accessed, the guest sees a page fault > without the error code for reserved bits? No, for non-present page there is no issue because there are no reserved bits in that case. If the page is present and no reserved bits are set according to the host, however, there are two cases to consider: - if the page is not accessible to the guest according to the permissions in the page table, it will cause a #PF. We need to trap it and change the error code into P|RSVD if the guest physical address has any guest-reserved bits. - if the page is accessible to the guest according to the permissions in the page table, it will cause a #NPF. Again, we need to trap it, check the guest physical address and inject a P|RSVD #PF if the guest physical address has any guest-reserved bits. The AMD specific issue happens in the second case. By the time the NPF vmexit occurs, the accessed and/or dirty bits have been set and this should not have happened before the RSVD page fault that we want to inject. On Intel processors, instead, EPT violations trigger before accessed and dirty bits are set. I cannot find an explicit mention of the intended behavior in either the Intel SDM or the AMD APM. Paolo