From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.2 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 63E3EC432BE for ; Fri, 30 Jul 2021 03:13:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4DE2160E9B for ; Fri, 30 Jul 2021 03:13:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235162AbhG3DNJ (ORCPT ); Thu, 29 Jul 2021 23:13:09 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:53512 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S229971AbhG3DNH (ORCPT ); Thu, 29 Jul 2021 23:13:07 -0400 X-UUID: 4432765b1f634dd1b33951c6d6f56a91-20210730 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:From:Subject:Message-ID; bh=LejJWnZ2JOLo/DhJM3s97omYPuDb/lLAN8IlUBxwa7k=; b=h1+sYkduhXDBwaUJTp2EDoRCqHiU2fZAqAVrU6beVzXSojWToT8zMSE3q3X6js8O/L8optyeXYkCm5sJkapGC1zWUKb5vR4RS1FMmvLLH5AuclJHiJHCa24O1FC7LmwHJ1fdH3VtM7FrGKqin7I2av57DRVK2did+BPU5QyGZes=; X-UUID: 4432765b1f634dd1b33951c6d6f56a91-20210730 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1586064953; Fri, 30 Jul 2021 11:13:01 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 30 Jul 2021 11:12:54 +0800 Received: from mtksdccf07 (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 30 Jul 2021 11:12:53 +0800 Message-ID: <526dc9077c696015d1f1065cb6e7f2c7c446ad61.camel@mediatek.com> Subject: Re: [v3 3/5] soc: mediatek: pm-domains: Add support for mt8195 From: Chun-Jie Chen To: Chen-Yu Tsai CC: Enric Balletbo i Serra , Matthias Brugger , Nicolas Boichat , "Rob Herring" , , LKML , , , srv_heupstream , Project_Global_Chrome_Upstream_Group Date: Fri, 30 Jul 2021 11:12:53 +0800 In-Reply-To: References: <20210705054111.4473-1-chun-jie.chen@mediatek.com> <20210705054111.4473-4-chun-jie.chen@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 X-MTK: N Content-Transfer-Encoding: base64 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org T24gVHVlLCAyMDIxLTA3LTIwIGF0IDE2OjUxICswODAwLCBDaGVuLVl1IFRzYWkgd3JvdGU6DQo+ IEhpLA0KPiBPbiBNb24sIEp1bCA1LCAyMDIxIGF0IDE6NDIgUE0gQ2h1bi1KaWUgQ2hlbiA8DQo+ IGNodW4tamllLmNoZW5AbWVkaWF0ZWsuY29tPiB3cm90ZToNCj4gPiANCj4gPiBBZGQgZG9tYWlu IGNvbnRyb2wgZGF0YSBpbmNsdWRpbmcgYnVzIHByb3RlY3Rpb24gZGF0YSBzaXplDQo+ID4gY2hh bmdlIGR1ZSB0byBtb3JlIHByb3RlY3Rpb24gc3RlcHMgaW4gbXQ4MTk1Lg0KPiA+IA0KPiA+IFNp Z25lZC1vZmYtYnk6IENodW4tSmllIENoZW4gPGNodW4tamllLmNoZW5AbWVkaWF0ZWsuY29tPg0K PiA+IC0tLQ0KPiA+ICBkcml2ZXJzL3NvYy9tZWRpYXRlay9tdDgxOTUtcG0tZG9tYWlucy5oIHwg NzM4DQo+ID4gKysrKysrKysrKysrKysrKysrKysrKysNCj4gPiAgZHJpdmVycy9zb2MvbWVkaWF0 ZWsvbXRrLXBtLWRvbWFpbnMuYyAgICB8ICAgNSArDQo+ID4gIGRyaXZlcnMvc29jL21lZGlhdGVr L210ay1wbS1kb21haW5zLmggICAgfCAgIDIgKy0NCj4gPiAgaW5jbHVkZS9saW51eC9zb2MvbWVk aWF0ZWsvaW5mcmFjZmcuaCAgICB8IDEwMyArKysrDQo+ID4gIDQgZmlsZXMgY2hhbmdlZCwgODQ3 IGluc2VydGlvbnMoKyksIDEgZGVsZXRpb24oLSkNCj4gPiAgY3JlYXRlIG1vZGUgMTAwNjQ0IGRy aXZlcnMvc29jL21lZGlhdGVrL210ODE5NS1wbS1kb21haW5zLmgNCj4gPiANCj4gPiBkaWZmIC0t Z2l0IGEvZHJpdmVycy9zb2MvbWVkaWF0ZWsvbXQ4MTk1LXBtLWRvbWFpbnMuaA0KPiA+IGIvZHJp dmVycy9zb2MvbWVkaWF0ZWsvbXQ4MTk1LXBtLWRvbWFpbnMuaA0KPiA+IG5ldyBmaWxlIG1vZGUg MTAwNjQ0DQo+ID4gaW5kZXggMDAwMDAwMDAwMDAwLi41NGJiN2FmOGU5YTMNCj4gPiAtLS0gL2Rl di9udWxsDQo+ID4gKysrIGIvZHJpdmVycy9zb2MvbWVkaWF0ZWsvbXQ4MTk1LXBtLWRvbWFpbnMu aA0KPiA+IEBAIC0wLDAgKzEsNzM4IEBADQo+ID4gKy8qIFNQRFgtTGljZW5zZS1JZGVudGlmaWVy OiBHUEwtMi4wLW9ubHkgKi8NCj4gPiArLyoNCj4gPiArICogQ29weXJpZ2h0IChjKSAyMDIxIE1l ZGlhVGVrIEluYy4NCj4gPiArICogQXV0aG9yOiBDaHVuLUppZSBDaGVuIDxjaHVuLWppZS5jaGVu QG1lZGlhdGVrLmNvbT4NCj4gPiArICovDQo+ID4gKw0KPiA+ICsjaWZuZGVmIF9fU09DX01FRElB VEVLX01UODE5NV9QTV9ET01BSU5TX0gNCj4gPiArI2RlZmluZSBfX1NPQ19NRURJQVRFS19NVDgx OTVfUE1fRE9NQUlOU19IDQo+ID4gKw0KPiA+ICsjaW5jbHVkZSAibXRrLXBtLWRvbWFpbnMuaCIN Cj4gPiArI2luY2x1ZGUgPGR0LWJpbmRpbmdzL3Bvd2VyL210ODE5NS1wb3dlci5oPg0KPiA+ICsN Cj4gPiArLyoNCj4gPiArICogTVQ4MTk1IHBvd2VyIGRvbWFpbiBzdXBwb3J0DQo+ID4gKyAqLw0K PiA+ICsNCj4gPiArc3RhdGljIGNvbnN0IHN0cnVjdCBzY3BzeXNfZG9tYWluX2RhdGEgc2Nwc3lz X2RvbWFpbl9kYXRhX210ODE5NVtdDQo+ID4gPSB7DQo+IA0KPiBUaGUgU0NQU1lTIGJsb2NrIGlz IG5vdCBkb2N1bWVudGVkIGluIHRoZSBkYXRhc2hlZXRzIGF2YWlsYWJsZS4NCj4gSG93ZXZlcg0K PiBJIGRpZCBsb29rIGF0IGFsbCB0aGUgcmVnaXN0ZXIgYW5kIGJpdCBvZmZzZXRzIGFuZCBjb25m aXJtZWQgbm90aGluZw0KPiBvdmVybGFwcGVkLg0KPiANCj4gPiBkaWZmIC0tZ2l0IGEvZHJpdmVy cy9zb2MvbWVkaWF0ZWsvbXRrLXBtLWRvbWFpbnMuYw0KPiA+IGIvZHJpdmVycy9zb2MvbWVkaWF0 ZWsvbXRrLXBtLWRvbWFpbnMuYw0KPiA+IGluZGV4IDI2ODlmMDJkN2E0MS4uMTI1NTJjOTk5NmFj IDEwMDY0NA0KPiA+IC0tLSBhL2RyaXZlcnMvc29jL21lZGlhdGVrL210ay1wbS1kb21haW5zLmMN Cj4gPiArKysgYi9kcml2ZXJzL3NvYy9tZWRpYXRlay9tdGstcG0tZG9tYWlucy5jDQo+ID4gQEAg LTIwLDYgKzIwLDcgQEANCj4gPiAgI2luY2x1ZGUgIm10ODE3My1wbS1kb21haW5zLmgiDQo+ID4g ICNpbmNsdWRlICJtdDgxODMtcG0tZG9tYWlucy5oIg0KPiA+ICAjaW5jbHVkZSAibXQ4MTkyLXBt LWRvbWFpbnMuaCINCj4gPiArI2luY2x1ZGUgIm10ODE5NS1wbS1kb21haW5zLmgiDQo+ID4gDQo+ ID4gICNkZWZpbmUgTVRLX1BPTExfREVMQVlfVVMgICAgICAgICAgICAgIDEwDQo+ID4gICNkZWZp bmUgTVRLX1BPTExfVElNRU9VVCAgICAgICAgICAgICAgIFVTRUNfUEVSX1NFQw0KPiA+IEBAIC01 NzYsNiArNTc3LDEwIEBAIHN0YXRpYyBjb25zdCBzdHJ1Y3Qgb2ZfZGV2aWNlX2lkDQo+ID4gc2Nw c3lzX29mX21hdGNoW10gPSB7DQo+ID4gICAgICAgICAgICAgICAgIC5jb21wYXRpYmxlID0gIm1l ZGlhdGVrLG10ODE5Mi1wb3dlci1jb250cm9sbGVyIiwNCj4gPiAgICAgICAgICAgICAgICAgLmRh dGEgPSAmbXQ4MTkyX3NjcHN5c19kYXRhLA0KPiA+ICAgICAgICAgfSwNCj4gPiArICAgICAgIHsN Cj4gPiArICAgICAgICAgICAgICAgLmNvbXBhdGlibGUgPSAibWVkaWF0ZWssbXQ4MTk1LXBvd2Vy LWNvbnRyb2xsZXIiLA0KPiA+ICsgICAgICAgICAgICAgICAuZGF0YSA9ICZtdDgxOTVfc2Nwc3lz X2RhdGEsDQo+ID4gKyAgICAgICB9LA0KPiA+ICAgICAgICAgeyB9DQo+ID4gIH07DQo+ID4gDQo+ ID4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvc29jL21lZGlhdGVrL210ay1wbS1kb21haW5zLmgNCj4g PiBiL2RyaXZlcnMvc29jL21lZGlhdGVrL210ay1wbS1kb21haW5zLmgNCj4gPiBpbmRleCA4Yjg2 ZWQyMmNhNTYuLmNhYWEzODEwMDA5MyAxMDA2NDQNCj4gPiAtLS0gYS9kcml2ZXJzL3NvYy9tZWRp YXRlay9tdGstcG0tZG9tYWlucy5oDQo+ID4gKysrIGIvZHJpdmVycy9zb2MvbWVkaWF0ZWsvbXRr LXBtLWRvbWFpbnMuaA0KPiA+IEBAIC0zNyw3ICszNyw3IEBADQo+ID4gICNkZWZpbmUgUFdSX1NU QVRVU19BVURJTyAgICAgICAgICAgICAgIEJJVCgyNCkNCj4gPiAgI2RlZmluZSBQV1JfU1RBVFVT X1VTQiAgICAgICAgICAgICAgICAgQklUKDI1KQ0KPiA+IA0KPiA+IC0jZGVmaW5lIFNQTV9NQVhf QlVTX1BST1RfREFUQSAgICAgICAgICA1DQo+ID4gKyNkZWZpbmUgU1BNX01BWF9CVVNfUFJPVF9E QVRBICAgICAgICAgIDYNCj4gPiANCj4gPiAgI2RlZmluZSBfQlVTX1BST1QoX21hc2ssIF9zZXQs IF9jbHIsIF9zdGEsIF91cGRhdGUsIF9pZ25vcmUpIHsgXA0KPiA+ICAgICAgICAgICAgICAgICAu YnVzX3Byb3RfbWFzayA9IChfbWFzayksICAgICAgICAgICAgICAgICAgICAgICBcDQo+ID4gZGlm ZiAtLWdpdCBhL2luY2x1ZGUvbGludXgvc29jL21lZGlhdGVrL2luZnJhY2ZnLmgNCj4gPiBiL2lu Y2x1ZGUvbGludXgvc29jL21lZGlhdGVrL2luZnJhY2ZnLmgNCj4gPiBpbmRleCA0NjE1YTIyOGRh NTEuLjNlOTBmYjliOTI2YSAxMDA2NDQNCj4gPiAtLS0gYS9pbmNsdWRlL2xpbnV4L3NvYy9tZWRp YXRlay9pbmZyYWNmZy5oDQo+ID4gKysrIGIvaW5jbHVkZS9saW51eC9zb2MvbWVkaWF0ZWsvaW5m cmFjZmcuaA0KPiA+IEBAIC0yLDYgKzIsMTA5IEBADQo+ID4gICNpZm5kZWYgX19TT0NfTUVESUFU RUtfSU5GUkFDRkdfSA0KPiA+ICAjZGVmaW5lIF9fU09DX01FRElBVEVLX0lORlJBQ0ZHX0gNCj4g PiANCj4gPiArI2RlZmluZSBNVDgxOTVfVE9QX0FYSV9QUk9UX0VOX1NUQTEgICAgICAgICAgICAg ICAgICAgICAweDIyOA0KPiA+ICsjZGVmaW5lIE1UODE5NV9UT1BfQVhJX1BST1RfRU5fMV9TVEEx ICAgICAgICAgICAgICAgICAgIDB4MjU4DQo+ID4gKyNkZWZpbmUgTVQ4MTk1X1RPUF9BWElfUFJP VF9FTl9TRVQgICAgICAgICAgICAgICAgICAgICAweDJhMA0KPiA+ICsjZGVmaW5lIE1UODE5NV9U T1BfQVhJX1BST1RfRU5fQ0xSICAgICAgICAgICAgICAgICAgICAgIDB4MmE0DQo+ID4gKyNkZWZp bmUgTVQ4MTk1X1RPUF9BWElfUFJPVF9FTl8xX1NFVCAgICAgICAgICAgICAgICAgICAgMHgyYTgN Cj4gPiArI2RlZmluZSBNVDgxOTVfVE9QX0FYSV9QUk9UX0VOXzFfQ0xSICAgICAgICAgICAgICAg ICAgICAweDJhYw0KPiA+ICsjZGVmaW5lIE1UODE5NV9UT1BfQVhJX1BST1RfRU5fTU1fU0VUICAg ICAgICAgICAgICAgICAgIDB4MmQ0DQo+ID4gKyNkZWZpbmUgTVQ4MTk1X1RPUF9BWElfUFJPVF9F Tl9NTV9DTFIgICAgICAgICAgICAgICAgICAgMHgyZDgNCj4gPiArI2RlZmluZSBNVDgxOTVfVE9Q X0FYSV9QUk9UX0VOX01NX1NUQTEgICAgICAgICAgICAgICAgICAweDJlYw0KPiA+ICsjZGVmaW5l IE1UODE5NV9UT1BfQVhJX1BST1RfRU5fMl9TRVQgICAgICAgICAgICAgICAgICAgIDB4NzE0DQo+ ID4gKyNkZWZpbmUgTVQ4MTk1X1RPUF9BWElfUFJPVF9FTl8yX0NMUiAgICAgICAgICAgICAgICAg ICAgMHg3MTgNCj4gPiArI2RlZmluZSBNVDgxOTVfVE9QX0FYSV9QUk9UX0VOXzJfU1RBMSAgICAg ICAgICAgICAgICAgICAweDcyNA0KPiA+ICsjZGVmaW5lIE1UODE5NV9UT1BfQVhJX1BST1RfRU5f VkROUl9TRVQgICAgICAgICAgICAgICAgIDB4Yjg0DQo+ID4gKyNkZWZpbmUgTVQ4MTk1X1RPUF9B WElfUFJPVF9FTl9WRE5SX0NMUiAgICAgICAgICAgICAgICAgMHhiODgNCj4gPiArI2RlZmluZSBN VDgxOTVfVE9QX0FYSV9QUk9UX0VOX1ZETlJfU1RBMSAgICAgICAgICAgICAgICAweGI5MA0KPiA+ ICsjZGVmaW5lIE1UODE5NV9UT1BfQVhJX1BST1RfRU5fVkROUl8xX1NFVCAgICAgICAgICAgICAg IDB4YmE0DQo+ID4gKyNkZWZpbmUgTVQ4MTk1X1RPUF9BWElfUFJPVF9FTl9WRE5SXzFfQ0xSICAg ICAgICAgICAgICAgMHhiYTgNCj4gPiArI2RlZmluZSBNVDgxOTVfVE9QX0FYSV9QUk9UX0VOX1ZE TlJfMV9TVEExICAgICAgICAgICAgICAweGJiMA0KPiA+ICsjZGVmaW5lIE1UODE5NV9UT1BfQVhJ X1BST1RfRU5fVkROUl8yX1NFVCAgICAgICAgICAgICAgIDB4YmI4DQo+ID4gKyNkZWZpbmUgTVQ4 MTk1X1RPUF9BWElfUFJPVF9FTl9WRE5SXzJfQ0xSICAgICAgICAgICAgICAgMHhiYmMNCj4gPiAr I2RlZmluZSBNVDgxOTVfVE9QX0FYSV9QUk9UX0VOX1ZETlJfMl9TVEExICAgICAgICAgICAgICAw eGJjNA0KPiA+ICsjZGVmaW5lIE1UODE5NV9UT1BfQVhJX1BST1RfRU5fU1VCX0lORlJBX1ZETlJf U0VUICAgICAgIDB4YmNjDQo+ID4gKyNkZWZpbmUgTVQ4MTk1X1RPUF9BWElfUFJPVF9FTl9TVUJf SU5GUkFfVkROUl9DTFIgICAgICAgMHhiZDANCj4gPiArI2RlZmluZSBNVDgxOTVfVE9QX0FYSV9Q Uk9UX0VOX1NVQl9JTkZSQV9WRE5SX1NUQTEgICAgICAweGJkOA0KPiA+ICsjZGVmaW5lIE1UODE5 NV9UT1BfQVhJX1BST1RfRU5fTU1fMl9TRVQgICAgICAgICAgICAgICAgIDB4ZGNjDQo+ID4gKyNk ZWZpbmUgTVQ4MTk1X1RPUF9BWElfUFJPVF9FTl9NTV8yX0NMUiAgICAgICAgICAgICAgICAgMHhk ZDANCj4gPiArI2RlZmluZSBNVDgxOTVfVE9QX0FYSV9QUk9UX0VOX01NXzJfU1RBMSAgICAgICAg ICAgICAgICAweGRkOA0KPiANCj4gVGhlc2UgYWxsIGxvb2sgY29ycmVjdC4NCj4gDQo+ID4gKyNk ZWZpbmUgTVQ4MTk1X1RPUF9BWElfUFJPVF9FTl9OTkEwICAgICAgICAgICAgICAgICAgICBCSVQo MSkNCj4gPiArI2RlZmluZSBNVDgxOTVfVE9QX0FYSV9QUk9UX0VOX05OQTEgICAgICAgICAgICAg ICAgICAgIEJJVCgyKQ0KPiA+ICsjZGVmaW5lIE1UODE5NV9UT1BfQVhJX1BST1RfRU5fTk5BICAg ICAgICAgICAgICAgICAgICAgR0VOTUFTSygyLA0KPiA+IDEpDQo+ID4gKyNkZWZpbmUgTVQ4MTk1 X1RPUF9BWElfUFJPVF9FTl9WRE9TWVMwICAgICAgICAgICAgICAgICBCSVQoNikNCj4gPiArI2Rl ZmluZSBNVDgxOTVfVE9QX0FYSV9QUk9UX0VOX1ZQUFNZUzAgICAgICAgICAgICAgICAgIEJJVCgx MCkNCj4gPiArI2RlZmluZSBNVDgxOTVfVE9QX0FYSV9QUk9UX0VOX01GRzEgICAgICAgICAgICAg ICAgICAgIEJJVCgxMSkNCj4gPiArI2RlZmluZQ0KPiA+IE1UODE5NV9UT1BfQVhJX1BST1RfRU5f TUZHMV8yTkQgICAgICAgICAgICAgICAgICAgICAgICBHRU5NQVNLKDIyLA0KPiA+IDIxKQ0KPiA+ ICsjZGVmaW5lIE1UODE5NV9UT1BfQVhJX1BST1RfRU5fVlBQU1lTMF8yTkQgICAgICAgICAgICAg QklUKDIzKQ0KPiA+ICsjZGVmaW5lIE1UODE5NV9UT1BfQVhJX1BST1RfRU5fMV9NRkcxICAgICAg ICAgICAgICAgICAgR0VOTUFTSygyMCwNCj4gPiAxOSkNCj4gPiArI2RlZmluZSBNVDgxOTVfVE9Q X0FYSV9QUk9UX0VOXzFfQ0FNICAgICAgICAgICAgICAgICAgIEJJVCgyMikNCj4gPiArI2RlZmlu ZSBNVDgxOTVfVE9QX0FYSV9QUk9UX0VOXzJfQ0FNICAgICAgICAgICAgICAgICAgIEJJVCgwKQ0K PiA+ICsjZGVmaW5lIE1UODE5NV9UT1BfQVhJX1BST1RfRU5fMl9NRkcxXzJORCAgICAgICAgICAg ICAgR0VOTUFTSyg2LA0KPiA+IDUpDQo+ID4gKyNkZWZpbmUgTVQ4MTk1X1RPUF9BWElfUFJPVF9F Tl8yX01GRzEgICAgICAgICAgICAgICAgICBCSVQoNykNCj4gPiArI2RlZmluZSBNVDgxOTVfVE9Q X0FYSV9QUk9UX0VOXzJfQVVESU9fQVNSQyAgICAgICAgICAgIChCSVQoOCkgfA0KPiA+IEJJVCgx NykpDQo+ID4gKyNkZWZpbmUgTVQ4MTk1X1RPUF9BWElfUFJPVF9FTl8yX0FVRElPICAgICAgICAg ICAgICAgICAoQklUKDkpIHwNCj4gPiBCSVQoMTEpKQ0KPiA+ICsjZGVmaW5lIE1UODE5NV9UT1Bf QVhJX1BST1RfRU5fMl9BRFNQICAgICAgICAgICAgICAgICAgKEJJVCgxMikgfA0KPiA+IEdFTk1B U0soMTYsIDE0KSkNCj4gPiArI2RlZmluZSBNVDgxOTVfVE9QX0FYSV9QUk9UX0VOXzJfTk5BMF8y TkQgICAgICAgICAgICAgIEJJVCgxOSkNCj4gPiArI2RlZmluZSBNVDgxOTVfVE9QX0FYSV9QUk9U X0VOXzJfTk5BMV8yTkQgICAgICAgICAgICAgIEJJVCgyMCkNCj4gPiArI2RlZmluZSBNVDgxOTVf VE9QX0FYSV9QUk9UX0VOXzJfTk5BXzJORCAgICAgICAgICAgICAgIEdFTk1BU0soMjAsDQo+ID4g MTkpDQo+ID4gKyNkZWZpbmUgTVQ4MTk1X1RPUF9BWElfUFJPVF9FTl8yX05OQTAgICAgICAgICAg ICAgICAgICBCSVQoMjEpDQo+ID4gKyNkZWZpbmUgTVQ4MTk1X1RPUF9BWElfUFJPVF9FTl8yX05O QTEgICAgICAgICAgICAgICAgICBCSVQoMjIpDQo+ID4gKyNkZWZpbmUgTVQ4MTk1X1RPUF9BWElf UFJPVF9FTl8yX05OQSAgICAgICAgICAgICAgICAgICBHRU5NQVNLKDIyLA0KPiA+IDIxKQ0KPiA+ ICsjZGVmaW5lIE1UODE5NV9UT1BfQVhJX1BST1RfRU5fTU1fQ0FNICAgICAgICAgICAgICAgICAg KEJJVCgwKSB8DQo+ID4gQklUKDIpIHwgQklUKDQpKQ0KPiA+ICsjZGVmaW5lIE1UODE5NV9UT1Bf QVhJX1BST1RfRU5fTU1fSVBFICAgICAgICAgICAgICAgICAgQklUKDEpDQo+ID4gKyNkZWZpbmUg TVQ4MTk1X1RPUF9BWElfUFJPVF9FTl9NTV9JTUcgICAgICAgICAgICAgICAgICAoQklUKDEpIHwN Cj4gPiBCSVQoMykpDQo+ID4gKyNkZWZpbmUgTVQ4MTk1X1RPUF9BWElfUFJPVF9FTl9NTV9WUFBT WVMwICAgICAgICAgICAgICAoR0VOTUFTSygyLA0KPiA+IDApIHwgR0VOTUFTSyg4LCA2KSB8ICAg ICAgICBcDQo+ID4gKyAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgICAgICBHRU5NQVNLKDEyLA0KPiA+IDEwKSB8IEdFTk1BU0soMjEsIDE5KSB8ICAgICBc DQo+ID4gKyAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgICBCSVQoMzEpKQ0KPiA+ICsjZGVmaW5lIE1UODE5NV9UT1BfQVhJX1BST1RfRU5fTU1fVkRP U1lTMCAgICAgICAgICAgICAgKEdFTk1BU0soNSwNCj4gPiAzKSB8IEJJVCg5KSB8ICAgICAgIFwN Cj4gPiArICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgIEdFTk1BU0soMTQsDQo+ID4gMTMpIHwgR0VOTUFTSygyMSwgMTcpIHwgICAgIFwNCj4gPiAr ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIEJJ VCgzMCkpDQo+ID4gKyNkZWZpbmUgTVQ4MTk1X1RPUF9BWElfUFJPVF9FTl9NTV9WUFBTWVMxICAg ICAgICAgICAgICBHRU5NQVNLKDgsDQo+ID4gNSkNCj4gPiArI2RlZmluZSBNVDgxOTVfVE9QX0FY SV9QUk9UX0VOX01NX1ZFTkMgICAgICAgICAgICAgICAgIChCSVQoOSkgfA0KPiA+IEJJVCgxMSkp DQo+ID4gKyNkZWZpbmUgTVQ4MTk1X1RPUF9BWElfUFJPVF9FTl9NTV9WRU5DX0NPUkUxICAgICAg ICAgICAoQklUKDEwKSB8DQo+ID4gQklUKDEyKSkNCj4gPiArI2RlZmluZQ0KPiA+IE1UODE5NV9U T1BfQVhJX1BST1RfRU5fTU1fVkRFQzAgICAgICAgICAgICAgICAgICAgICAgICBCSVQoMTMpDQo+ ID4gKyNkZWZpbmUNCj4gPiBNVDgxOTVfVE9QX0FYSV9QUk9UX0VOX01NX1ZERUMxICAgICAgICAg ICAgICAgICAgICAgICAgQklUKDE0KQ0KPiA+ICsjZGVmaW5lIE1UODE5NV9UT1BfQVhJX1BST1Rf RU5fTU1fVkRPU1lTMV8yTkQgICAgICAgICAgQklUKDIyKQ0KPiA+ICsjZGVmaW5lIE1UODE5NV9U T1BfQVhJX1BST1RfRU5fTU1fVlBQU1lTMV8yTkQgICAgICAgICAgQklUKDIzKQ0KPiA+ICsjZGVm aW5lIE1UODE5NV9UT1BfQVhJX1BST1RfRU5fTU1fQ0FNXzJORCAgICAgICAgICAgICAgQklUKDI0 KQ0KPiA+ICsjZGVmaW5lIE1UODE5NV9UT1BfQVhJX1BST1RfRU5fTU1fSU1HXzJORCAgICAgICAg ICAgICAgQklUKDI1KQ0KPiA+ICsjZGVmaW5lIE1UODE5NV9UT1BfQVhJX1BST1RfRU5fTU1fVkVO Q18yTkQgICAgICAgICAgICAgQklUKDI2KQ0KPiA+ICsjZGVmaW5lIE1UODE5NV9UT1BfQVhJX1BS T1RfRU5fTU1fV1BFU1lTICAgICAgICAgICAgICAgQklUKDI3KQ0KPiA+ICsjZGVmaW5lIE1UODE5 NV9UT1BfQVhJX1BST1RfRU5fTU1fVkRFQzBfMk5EICAgICAgICAgICAgQklUKDI4KQ0KPiA+ICsj ZGVmaW5lIE1UODE5NV9UT1BfQVhJX1BST1RfRU5fTU1fVkRFQzFfMk5EICAgICAgICAgICAgQklU KDI5KQ0KPiA+ICsjZGVmaW5lIE1UODE5NV9UT1BfQVhJX1BST1RfRU5fTU1fVkRPU1lTMF8yTkQg ICAgICAgICAgR0VOTUFTSygyOSwNCj4gPiAyMikNCj4gPiArI2RlZmluZSBNVDgxOTVfVE9QX0FY SV9QUk9UX0VOX01NX1ZET1NZUzEgICAgICAgICAgICAgIEdFTk1BU0soMzEsDQo+ID4gMzApDQo+ IA0KPiBUaGVyZSdzIHNpZ25pZmljYW50IG92ZXJsYXAgd2l0aGluIHRoaXMgYmxvY2suIFRoaXMg bWVhbnMgd2hlbiB0aGUNCj4gYmFzZQ0KPiBWRE9TWVMwIHBvd2VyIGRvbWFpbiBpcyBvbiwgYWxs IHRoZSBvdmVybGFwcGVkIHByb3RlY3Rpb24gYml0cyBnZXQNCj4gdHVybmVkDQo+IG9mZi4gSSdt IG5vdCBzdXJlIHRoYXQncyBjb3JyZWN0Lg0KPiANCj4gU2FtZSBnb2VzIGZvciBJTUcsIHdoaWNo IG92ZXJsYXBzIHdpdGggSVBFLg0KPiANCg0KQmVjYXVzZSB0aGUgdGltaW5nIG9mIGVuYWJsZSAm IGRpc2FibGUgcHJvdGVjdGlvbiBhcmUgZGlmZmVyZW50LCB3ZQ0KZHVwbGljYXRlIHNvbWUgY29u dHJvbCBiaXQgaW4gZGlmZmVyZW50IHBvd2VyIGRvbWFpbi4NCg0KRm9yIGV4YW1wbGU6IElNRyAm IElQRSBhcmUgcGFyZW50IGFuZCBjaGlsZCByZWxhdGlvbiwgc28gSU1HIG11c3QgcG93ZXINCm9u IGJlZm9yZSBJUEUsIElQRSBtdXN0IHBvd2VyIG9mZiBiZWZvcmUgSU1HLg0KV2Ugd2FudCB0byBj bGVhciBzb21lIGJpdHMgKHByb3RlY3Rpb24gZGlzYWJsZSkgd2hlbiBwb3dlciBvbiBJTUcgYW5k DQpzZXQgc29tZSBiaXRzIChwcm90ZWN0aW9uIGVuYWJsZSkgd2hlbiBwb3dlciBvZmYgSVBFLg0K DQo+ID4gKyNkZWZpbmUNCj4gPiBNVDgxOTVfVE9QX0FYSV9QUk9UX0VOX01NXzJfVlBQU1lTMF8y TkQgICAgICAgICAgICAgICAgKEdFTk1BU0soNywNCj4gPiAwKSB8IEdFTk1BU0soMTgsIDExKSkN Cj4gPiArI2RlZmluZSBNVDgxOTVfVE9QX0FYSV9QUk9UX0VOX01NXzJfVkVOQyAgICAgICAgICAg ICAgIEJJVCgyKQ0KPiA+ICsjZGVmaW5lIE1UODE5NV9UT1BfQVhJX1BST1RfRU5fTU1fMl9WRU5D X0NPUkUxICAgICAgICAgKEJJVCgzKSB8DQo+ID4gQklUKDE1KSkNCj4gPiArI2RlZmluZQ0KPiA+ IE1UODE5NV9UT1BfQVhJX1BST1RfRU5fTU1fMl9DQU0gICAgICAgICAgICAgICAgICAgICAgICAo QklUKDUpIHwNCj4gPiBCSVQoMTcpKQ0KPiA+ICsjZGVmaW5lIE1UODE5NV9UT1BfQVhJX1BST1Rf RU5fTU1fMl9WUFBTWVMxICAgICAgICAgICAgKEdFTk1BU0soNywNCj4gPiA2KSB8IEJJVCgxOCkp DQo+ID4gKyNkZWZpbmUgTVQ4MTk1X1RPUF9BWElfUFJPVF9FTl9NTV8yX1ZQUFNZUzAgICAgICAg ICAgICAoR0VOTUFTSyg5LA0KPiA+IDgpIHwgR0VOTUFTSygyMiwgMjEpIHwgQklUKDI0KSkNCj4g PiArI2RlZmluZSBNVDgxOTVfVE9QX0FYSV9QUk9UX0VOX01NXzJfVkRPU1lTMSAgICAgICAgICAg IEJJVCgxMCkNCj4gPiArI2RlZmluZSBNVDgxOTVfVE9QX0FYSV9QUk9UX0VOX01NXzJfVkRFQzJf Mk5EICAgICAgICAgIEJJVCgxMikNCj4gPiArI2RlZmluZSBNVDgxOTVfVE9QX0FYSV9QUk9UX0VO X01NXzJfVkRFQzBfMk5EICAgICAgICAgIEJJVCgxMykNCj4gPiArI2RlZmluZSBNVDgxOTVfVE9Q X0FYSV9QUk9UX0VOX01NXzJfV1BFU1lTXzJORCAgICAgICAgIEJJVCgxNCkNCj4gPiArI2RlZmlu ZQ0KPiA+IE1UODE5NV9UT1BfQVhJX1BST1RfRU5fTU1fMl9JTUcgICAgICAgICAgICAgICAgICAg ICAgICBCSVQoMTYpDQo+ID4gKyNkZWZpbmUNCj4gPiBNVDgxOTVfVE9QX0FYSV9QUk9UX0VOX01N XzJfSVBFICAgICAgICAgICAgICAgICAgICAgICAgQklUKDE2KQ0KPiANCj4gQW5kIGhlcmUsIElN RyBhbmQgSVBFIGFyZSB0aGUgc2FtZS4NCj4gDQo+ID4gKyNkZWZpbmUgTVQ4MTk1X1RPUF9BWElf UFJPVF9FTl9NTV8yX1ZERUMyICAgICAgICAgICAgICBCSVQoMjEpDQo+ID4gKyNkZWZpbmUgTVQ4 MTk1X1RPUF9BWElfUFJPVF9FTl9NTV8yX1ZERUMwICAgICAgICAgICAgICBCSVQoMjIpDQo+ID4g KyNkZWZpbmUgTVQ4MTk1X1RPUF9BWElfUFJPVF9FTl9NTV8yX1ZET1NZUzAgICAgICAgICAgICBC SVQoMjMpDQo+ID4gKyNkZWZpbmUgTVQ4MTk1X1RPUF9BWElfUFJPVF9FTl9NTV8yX1dQRVNZUyAg ICAgICAgICAgICBHRU5NQVNLKDI0LA0KPiA+IDIzKQ0KPiA+ICsjZGVmaW5lIE1UODE5NV9UT1Bf QVhJX1BST1RfRU5fVkROUl8xX0VQRF9UWCAgICAgICAgICAgQklUKDEpDQo+ID4gKyNkZWZpbmUg TVQ4MTk1X1RPUF9BWElfUFJPVF9FTl9WRE5SXzFfRFBfVFggICAgICAgICAgICBCSVQoMikNCj4g PiArI2RlZmluZQ0KPiA+IE1UODE5NV9UT1BfQVhJX1BST1RfRU5fVkROUl9QQ0lFX01BQ19QMCAg ICAgICAgICAgICAgICAoQklUKDExKSB8DQo+ID4gQklUKDI4KSkNCj4gPiArI2RlZmluZQ0KPiA+ IE1UODE5NV9UT1BfQVhJX1BST1RfRU5fVkROUl9QQ0lFX01BQ19QMSAgICAgICAgICAgICAgICAo QklUKDEyKSB8DQo+ID4gQklUKDI5KSkNCj4gPiArI2RlZmluZSBNVDgxOTVfVE9QX0FYSV9QUk9U X0VOX1ZETlJfMV9QQ0lFX01BQ19QMCAgICAgIEJJVCgxMykNCj4gPiArI2RlZmluZSBNVDgxOTVf VE9QX0FYSV9QUk9UX0VOX1ZETlJfMV9QQ0lFX01BQ19QMSAgICAgIEJJVCgxNCkNCj4gPiArI2Rl ZmluZSBNVDgxOTVfVE9QX0FYSV9QUk9UX0VOX1NVQl9JTkZSQV9WRE5SX01GRzEgICAgIChCSVQo MTcpIHwNCj4gPiBCSVQoMTkpKQ0KPiA+ICsjZGVmaW5lIE1UODE5NV9UT1BfQVhJX1BST1RfRU5f U1VCX0lORlJBX1ZETlJfVlBQU1lTMCAgQklUKDIwKQ0KPiA+ICsjZGVmaW5lIE1UODE5NV9UT1Bf QVhJX1BST1RfRU5fU1VCX0lORlJBX1ZETlJfVkRPU1lTMCAgQklUKDIxKQ0KPiA+ICsjZGVmaW5l IE1UODE5NV9UT1BfQVhJX1BST1RfRU5fVkROUl8yX05OQTAgICAgICAgICAgICAgQklUKDI1KQ0K PiA+ICsjZGVmaW5lIE1UODE5NV9UT1BfQVhJX1BST1RfRU5fVkROUl8yX05OQTEgICAgICAgICAg ICAgQklUKDI2KQ0KPiA+ICsjZGVmaW5lIE1UODE5NV9UT1BfQVhJX1BST1RfRU5fVkROUl8yX05O QSAgICAgICAgICAgICAgR0VOTUFTSygyNiwNCj4gPiAyNSkNCj4gPiArDQo+IA0KPiBBbGwgdGhl c2UgTVQ4MTk1X1RPUF9BWElfUFJPVF9FTl8qIGJpdCBvZmZzZXRzIGFyZW4ndCBkb2N1bWVudGVk Lg0KPiBCZXNpZGVzDQo+IHRoZSBodWdlIG92ZXJsYXAgYWJvdmUsIGl0IHNlZW1zIE5OQSBhbHNv IGluY2x1ZGVzIE5OQTAgYW5kIE5OQTEuDQo+IA0KPiANCj4gUmVnYXJkcw0KPiBDaGVuWXUNCj4g DQoNClRoZSBkZXRhaWwgb2YgTVQ4MTk1X1RPUF9BWElfUFJPVF9FTl8qIGJpdCBpcyByZWxhdGVk IHRvIHRoZSBidXMNCmRlc2lnbiwgc28gd2UgZG9uJ3QgZGVzY3JpcHQgdGhlIGRldGFpbCBpbiBk YXRhc2hlZXQuDQoNCkkgd2lsbCByZW1vdmUgdGhlIHVudXNlZCBwb3dlciBkb21haW4gYW5kIGRh dGEgKGxpa2UgTk5BKSBiZWNhdXNlIHRoZXNlDQphcmUgbm90IHVzZWQgaW4gODE5NSBjaHJvbWUg cHJvamVjdC4NCg0KQmVzdCBSZWdhcmRzLA0KQ2h1bi1KaWUNCg0KPiANCj4gPiAgI2RlZmluZSBN VDgxOTJfVE9QX0FYSV9QUk9UX0VOX1NUQTEgICAgICAgICAgICAgICAgICAgIDB4MjI4DQo+ID4g ICNkZWZpbmUgTVQ4MTkyX1RPUF9BWElfUFJPVF9FTl8xX1NUQTEgICAgICAgICAgICAgICAgICAw eDI1OA0KPiA+ICAjZGVmaW5lIE1UODE5Ml9UT1BfQVhJX1BST1RfRU5fU0VUICAgICAgICAgICAg ICAgICAgICAgMHgyYTANCj4gPiAtLQ0KPiA+IDIuMTguMA0KPiA+IF9fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fDQo+ID4gTGludXgtbWVkaWF0ZWsgbWFpbGlu ZyBsaXN0DQo+ID4gTGludXgtbWVkaWF0ZWtAbGlzdHMuaW5mcmFkZWFkLm9yZw0KPiA+IA0KaHR0 cHM6Ly91cmxkZWZlbnNlLmNvbS92My9fX2h0dHA6Ly9saXN0cy5pbmZyYWRlYWQub3JnL21haWxt YW4vbGlzdGluZm8vbGludXgtbWVkaWF0ZWtfXzshIUNUUk5LQTl3TWcwQVJidyEzakFMY1Nnb2Iy SVFrblFuUWxJUFZLZDc5UWRLbVhJMVk5WDdrYVEyS1I4QVlkeVAwVjhLbTN1X0NmcThWUE1KNC16 biQNCj4gPiAgDQo= From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4D8CEC4338F for ; Fri, 30 Jul 2021 03:13:57 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0E56260ED4 for ; Fri, 30 Jul 2021 03:13:57 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 0E56260ED4 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Date:CC:To:From:Subject:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=N64Q+URPrxBEuH5S5uTKMYs6cGBZJmcSGmfDYLlzpbc=; b=h+ZHTq1fsLAbHx ZCIyGmypBWpQxAZXDsNMnz770aM47JRzmPikEOWEzFF039Ppzo9sYTAeqbSa9mcdBu9Hcn8b34Bn8 L2jXkLEUwWxZKMOUc+AMhh47NYjVxSlrs44B5cDk+8KWp4oaXxKXMumBEpbGF0sV2y8oSGNQhj2Ch ApNZzepsIBqoIWln4QmsfYibbFybEEBSmW4VJNL9Lo2ri28eJRVouqbl9WObuIJcp4AvezQqR0UXH fmCeKm/65LFMUFm5PjDavLBpuHKlDP4tpPz6HnG0Kuv+GyBsJ/lOJO5kdI4JWpDdsT+6HAo5PtuLk 6fmJS7+nw5LynLy6oGCg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1m9Iy1-006sEX-Ij; Fri, 30 Jul 2021 03:13:45 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1m9IxI-006rjp-HD; Fri, 30 Jul 2021 03:13:02 +0000 X-UUID: ea50fadba73b404fbef1650e1c1f11d9-20210729 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:From:Subject:Message-ID; bh=LejJWnZ2JOLo/DhJM3s97omYPuDb/lLAN8IlUBxwa7k=; b=h1+sYkduhXDBwaUJTp2EDoRCqHiU2fZAqAVrU6beVzXSojWToT8zMSE3q3X6js8O/L8optyeXYkCm5sJkapGC1zWUKb5vR4RS1FMmvLLH5AuclJHiJHCa24O1FC7LmwHJ1fdH3VtM7FrGKqin7I2av57DRVK2did+BPU5QyGZes=; X-UUID: ea50fadba73b404fbef1650e1c1f11d9-20210729 Received: from mtkcas67.mediatek.inc [(172.29.193.45)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 975429444; Thu, 29 Jul 2021 20:12:57 -0700 Received: from MTKMBS07N2.mediatek.inc (172.21.101.141) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 29 Jul 2021 20:12:55 -0700 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 30 Jul 2021 11:12:54 +0800 Received: from mtksdccf07 (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 30 Jul 2021 11:12:53 +0800 Message-ID: <526dc9077c696015d1f1065cb6e7f2c7c446ad61.camel@mediatek.com> Subject: Re: [v3 3/5] soc: mediatek: pm-domains: Add support for mt8195 From: Chun-Jie Chen To: Chen-Yu Tsai CC: Enric Balletbo i Serra , Matthias Brugger , Nicolas Boichat , "Rob Herring" , , LKML , , , srv_heupstream , Project_Global_Chrome_Upstream_Group Date: Fri, 30 Jul 2021 11:12:53 +0800 In-Reply-To: References: <20210705054111.4473-1-chun-jie.chen@mediatek.com> <20210705054111.4473-4-chun-jie.chen@mediatek.com> X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210729_201300_634331_1FCAD713 X-CRM114-Status: GOOD ( 26.20 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org On Tue, 2021-07-20 at 16:51 +0800, Chen-Yu Tsai wrote: > Hi, > On Mon, Jul 5, 2021 at 1:42 PM Chun-Jie Chen < > chun-jie.chen@mediatek.com> wrote: > > > > Add domain control data including bus protection data size > > change due to more protection steps in mt8195. > > > > Signed-off-by: Chun-Jie Chen > > --- > > drivers/soc/mediatek/mt8195-pm-domains.h | 738 > > +++++++++++++++++++++++ > > drivers/soc/mediatek/mtk-pm-domains.c | 5 + > > drivers/soc/mediatek/mtk-pm-domains.h | 2 +- > > include/linux/soc/mediatek/infracfg.h | 103 ++++ > > 4 files changed, 847 insertions(+), 1 deletion(-) > > create mode 100644 drivers/soc/mediatek/mt8195-pm-domains.h > > > > diff --git a/drivers/soc/mediatek/mt8195-pm-domains.h > > b/drivers/soc/mediatek/mt8195-pm-domains.h > > new file mode 100644 > > index 000000000000..54bb7af8e9a3 > > --- /dev/null > > +++ b/drivers/soc/mediatek/mt8195-pm-domains.h > > @@ -0,0 +1,738 @@ > > +/* SPDX-License-Identifier: GPL-2.0-only */ > > +/* > > + * Copyright (c) 2021 MediaTek Inc. > > + * Author: Chun-Jie Chen > > + */ > > + > > +#ifndef __SOC_MEDIATEK_MT8195_PM_DOMAINS_H > > +#define __SOC_MEDIATEK_MT8195_PM_DOMAINS_H > > + > > +#include "mtk-pm-domains.h" > > +#include > > + > > +/* > > + * MT8195 power domain support > > + */ > > + > > +static const struct scpsys_domain_data scpsys_domain_data_mt8195[] > > = { > > The SCPSYS block is not documented in the datasheets available. > However > I did look at all the register and bit offsets and confirmed nothing > overlapped. > > > diff --git a/drivers/soc/mediatek/mtk-pm-domains.c > > b/drivers/soc/mediatek/mtk-pm-domains.c > > index 2689f02d7a41..12552c9996ac 100644 > > --- a/drivers/soc/mediatek/mtk-pm-domains.c > > +++ b/drivers/soc/mediatek/mtk-pm-domains.c > > @@ -20,6 +20,7 @@ > > #include "mt8173-pm-domains.h" > > #include "mt8183-pm-domains.h" > > #include "mt8192-pm-domains.h" > > +#include "mt8195-pm-domains.h" > > > > #define MTK_POLL_DELAY_US 10 > > #define MTK_POLL_TIMEOUT USEC_PER_SEC > > @@ -576,6 +577,10 @@ static const struct of_device_id > > scpsys_of_match[] = { > > .compatible = "mediatek,mt8192-power-controller", > > .data = &mt8192_scpsys_data, > > }, > > + { > > + .compatible = "mediatek,mt8195-power-controller", > > + .data = &mt8195_scpsys_data, > > + }, > > { } > > }; > > > > diff --git a/drivers/soc/mediatek/mtk-pm-domains.h > > b/drivers/soc/mediatek/mtk-pm-domains.h > > index 8b86ed22ca56..caaa38100093 100644 > > --- a/drivers/soc/mediatek/mtk-pm-domains.h > > +++ b/drivers/soc/mediatek/mtk-pm-domains.h > > @@ -37,7 +37,7 @@ > > #define PWR_STATUS_AUDIO BIT(24) > > #define PWR_STATUS_USB BIT(25) > > > > -#define SPM_MAX_BUS_PROT_DATA 5 > > +#define SPM_MAX_BUS_PROT_DATA 6 > > > > #define _BUS_PROT(_mask, _set, _clr, _sta, _update, _ignore) { \ > > .bus_prot_mask = (_mask), \ > > diff --git a/include/linux/soc/mediatek/infracfg.h > > b/include/linux/soc/mediatek/infracfg.h > > index 4615a228da51..3e90fb9b926a 100644 > > --- a/include/linux/soc/mediatek/infracfg.h > > +++ b/include/linux/soc/mediatek/infracfg.h > > @@ -2,6 +2,109 @@ > > #ifndef __SOC_MEDIATEK_INFRACFG_H > > #define __SOC_MEDIATEK_INFRACFG_H > > > > +#define MT8195_TOP_AXI_PROT_EN_STA1 0x228 > > +#define MT8195_TOP_AXI_PROT_EN_1_STA1 0x258 > > +#define MT8195_TOP_AXI_PROT_EN_SET 0x2a0 > > +#define MT8195_TOP_AXI_PROT_EN_CLR 0x2a4 > > +#define MT8195_TOP_AXI_PROT_EN_1_SET 0x2a8 > > +#define MT8195_TOP_AXI_PROT_EN_1_CLR 0x2ac > > +#define MT8195_TOP_AXI_PROT_EN_MM_SET 0x2d4 > > +#define MT8195_TOP_AXI_PROT_EN_MM_CLR 0x2d8 > > +#define MT8195_TOP_AXI_PROT_EN_MM_STA1 0x2ec > > +#define MT8195_TOP_AXI_PROT_EN_2_SET 0x714 > > +#define MT8195_TOP_AXI_PROT_EN_2_CLR 0x718 > > +#define MT8195_TOP_AXI_PROT_EN_2_STA1 0x724 > > +#define MT8195_TOP_AXI_PROT_EN_VDNR_SET 0xb84 > > +#define MT8195_TOP_AXI_PROT_EN_VDNR_CLR 0xb88 > > +#define MT8195_TOP_AXI_PROT_EN_VDNR_STA1 0xb90 > > +#define MT8195_TOP_AXI_PROT_EN_VDNR_1_SET 0xba4 > > +#define MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR 0xba8 > > +#define MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1 0xbb0 > > +#define MT8195_TOP_AXI_PROT_EN_VDNR_2_SET 0xbb8 > > +#define MT8195_TOP_AXI_PROT_EN_VDNR_2_CLR 0xbbc > > +#define MT8195_TOP_AXI_PROT_EN_VDNR_2_STA1 0xbc4 > > +#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET 0xbcc > > +#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR 0xbd0 > > +#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1 0xbd8 > > +#define MT8195_TOP_AXI_PROT_EN_MM_2_SET 0xdcc > > +#define MT8195_TOP_AXI_PROT_EN_MM_2_CLR 0xdd0 > > +#define MT8195_TOP_AXI_PROT_EN_MM_2_STA1 0xdd8 > > These all look correct. > > > +#define MT8195_TOP_AXI_PROT_EN_NNA0 BIT(1) > > +#define MT8195_TOP_AXI_PROT_EN_NNA1 BIT(2) > > +#define MT8195_TOP_AXI_PROT_EN_NNA GENMASK(2, > > 1) > > +#define MT8195_TOP_AXI_PROT_EN_VDOSYS0 BIT(6) > > +#define MT8195_TOP_AXI_PROT_EN_VPPSYS0 BIT(10) > > +#define MT8195_TOP_AXI_PROT_EN_MFG1 BIT(11) > > +#define > > MT8195_TOP_AXI_PROT_EN_MFG1_2ND GENMASK(22, > > 21) > > +#define MT8195_TOP_AXI_PROT_EN_VPPSYS0_2ND BIT(23) > > +#define MT8195_TOP_AXI_PROT_EN_1_MFG1 GENMASK(20, > > 19) > > +#define MT8195_TOP_AXI_PROT_EN_1_CAM BIT(22) > > +#define MT8195_TOP_AXI_PROT_EN_2_CAM BIT(0) > > +#define MT8195_TOP_AXI_PROT_EN_2_MFG1_2ND GENMASK(6, > > 5) > > +#define MT8195_TOP_AXI_PROT_EN_2_MFG1 BIT(7) > > +#define MT8195_TOP_AXI_PROT_EN_2_AUDIO_ASRC (BIT(8) | > > BIT(17)) > > +#define MT8195_TOP_AXI_PROT_EN_2_AUDIO (BIT(9) | > > BIT(11)) > > +#define MT8195_TOP_AXI_PROT_EN_2_ADSP (BIT(12) | > > GENMASK(16, 14)) > > +#define MT8195_TOP_AXI_PROT_EN_2_NNA0_2ND BIT(19) > > +#define MT8195_TOP_AXI_PROT_EN_2_NNA1_2ND BIT(20) > > +#define MT8195_TOP_AXI_PROT_EN_2_NNA_2ND GENMASK(20, > > 19) > > +#define MT8195_TOP_AXI_PROT_EN_2_NNA0 BIT(21) > > +#define MT8195_TOP_AXI_PROT_EN_2_NNA1 BIT(22) > > +#define MT8195_TOP_AXI_PROT_EN_2_NNA GENMASK(22, > > 21) > > +#define MT8195_TOP_AXI_PROT_EN_MM_CAM (BIT(0) | > > BIT(2) | BIT(4)) > > +#define MT8195_TOP_AXI_PROT_EN_MM_IPE BIT(1) > > +#define MT8195_TOP_AXI_PROT_EN_MM_IMG (BIT(1) | > > BIT(3)) > > +#define MT8195_TOP_AXI_PROT_EN_MM_VPPSYS0 (GENMASK(2, > > 0) | GENMASK(8, 6) | \ > > + GENMASK(12, > > 10) | GENMASK(21, 19) | \ > > + BIT(31)) > > +#define MT8195_TOP_AXI_PROT_EN_MM_VDOSYS0 (GENMASK(5, > > 3) | BIT(9) | \ > > + GENMASK(14, > > 13) | GENMASK(21, 17) | \ > > + BIT(30)) > > +#define MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1 GENMASK(8, > > 5) > > +#define MT8195_TOP_AXI_PROT_EN_MM_VENC (BIT(9) | > > BIT(11)) > > +#define MT8195_TOP_AXI_PROT_EN_MM_VENC_CORE1 (BIT(10) | > > BIT(12)) > > +#define > > MT8195_TOP_AXI_PROT_EN_MM_VDEC0 BIT(13) > > +#define > > MT8195_TOP_AXI_PROT_EN_MM_VDEC1 BIT(14) > > +#define MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1_2ND BIT(22) > > +#define MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1_2ND BIT(23) > > +#define MT8195_TOP_AXI_PROT_EN_MM_CAM_2ND BIT(24) > > +#define MT8195_TOP_AXI_PROT_EN_MM_IMG_2ND BIT(25) > > +#define MT8195_TOP_AXI_PROT_EN_MM_VENC_2ND BIT(26) > > +#define MT8195_TOP_AXI_PROT_EN_MM_WPESYS BIT(27) > > +#define MT8195_TOP_AXI_PROT_EN_MM_VDEC0_2ND BIT(28) > > +#define MT8195_TOP_AXI_PROT_EN_MM_VDEC1_2ND BIT(29) > > +#define MT8195_TOP_AXI_PROT_EN_MM_VDOSYS0_2ND GENMASK(29, > > 22) > > +#define MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1 GENMASK(31, > > 30) > > There's significant overlap within this block. This means when the > base > VDOSYS0 power domain is on, all the overlapped protection bits get > turned > off. I'm not sure that's correct. > > Same goes for IMG, which overlaps with IPE. > Because the timing of enable & disable protection are different, we duplicate some control bit in different power domain. For example: IMG & IPE are parent and child relation, so IMG must power on before IPE, IPE must power off before IMG. We want to clear some bits (protection disable) when power on IMG and set some bits (protection enable) when power off IPE. > > +#define > > MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0_2ND (GENMASK(7, > > 0) | GENMASK(18, 11)) > > +#define MT8195_TOP_AXI_PROT_EN_MM_2_VENC BIT(2) > > +#define MT8195_TOP_AXI_PROT_EN_MM_2_VENC_CORE1 (BIT(3) | > > BIT(15)) > > +#define > > MT8195_TOP_AXI_PROT_EN_MM_2_CAM (BIT(5) | > > BIT(17)) > > +#define MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS1 (GENMASK(7, > > 6) | BIT(18)) > > +#define MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0 (GENMASK(9, > > 8) | GENMASK(22, 21) | BIT(24)) > > +#define MT8195_TOP_AXI_PROT_EN_MM_2_VDOSYS1 BIT(10) > > +#define MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2_2ND BIT(12) > > +#define MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0_2ND BIT(13) > > +#define MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS_2ND BIT(14) > > +#define > > MT8195_TOP_AXI_PROT_EN_MM_2_IMG BIT(16) > > +#define > > MT8195_TOP_AXI_PROT_EN_MM_2_IPE BIT(16) > > And here, IMG and IPE are the same. > > > +#define MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2 BIT(21) > > +#define MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0 BIT(22) > > +#define MT8195_TOP_AXI_PROT_EN_MM_2_VDOSYS0 BIT(23) > > +#define MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS GENMASK(24, > > 23) > > +#define MT8195_TOP_AXI_PROT_EN_VDNR_1_EPD_TX BIT(1) > > +#define MT8195_TOP_AXI_PROT_EN_VDNR_1_DP_TX BIT(2) > > +#define > > MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P0 (BIT(11) | > > BIT(28)) > > +#define > > MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P1 (BIT(12) | > > BIT(29)) > > +#define MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P0 BIT(13) > > +#define MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P1 BIT(14) > > +#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1 (BIT(17) | > > BIT(19)) > > +#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VPPSYS0 BIT(20) > > +#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VDOSYS0 BIT(21) > > +#define MT8195_TOP_AXI_PROT_EN_VDNR_2_NNA0 BIT(25) > > +#define MT8195_TOP_AXI_PROT_EN_VDNR_2_NNA1 BIT(26) > > +#define MT8195_TOP_AXI_PROT_EN_VDNR_2_NNA GENMASK(26, > > 25) > > + > > All these MT8195_TOP_AXI_PROT_EN_* bit offsets aren't documented. > Besides > the huge overlap above, it seems NNA also includes NNA0 and NNA1. > > > Regards > ChenYu > The detail of MT8195_TOP_AXI_PROT_EN_* bit is related to the bus design, so we don't descript the detail in datasheet. I will remove the unused power domain and data (like NNA) because these are not used in 8195 chrome project. Best Regards, Chun-Jie > > > #define MT8192_TOP_AXI_PROT_EN_STA1 0x228 > > #define MT8192_TOP_AXI_PROT_EN_1_STA1 0x258 > > #define MT8192_TOP_AXI_PROT_EN_SET 0x2a0 > > -- > > 2.18.0 > > _______________________________________________ > > Linux-mediatek mailing list > > Linux-mediatek@lists.infradead.org > > https://urldefense.com/v3/__http://lists.infradead.org/mailman/listinfo/linux-mediatek__;!!CTRNKA9wMg0ARbw!3jALcSgob2IQknQnQlIPVKd79QdKmXI1Y9X7kaQ2KR8AYdyP0V8Km3u_Cfq8VPMJ4-zn$ > > _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3B44CC4338F for ; Fri, 30 Jul 2021 03:14:59 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id ED50960E9B for ; Fri, 30 Jul 2021 03:14:58 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org ED50960E9B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Date:CC:To:From:Subject:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=P1c/7Z0eipeU+46l6ek+z73q7vwxREJMK53jIa0DwQw=; b=fHzmfGOYvnBh9h XM6n/xdtjLBxkD93v88vVbAdpC2GEw9Yoqt5JwixjjCOHuW6MHBp2o9XvFZiZ1HfP6LErNkOwE9Y7 ys2qRaPhXQm/AzYizQVrAkrCC/smCp6j6EikjkY9HxpCDZlYu9sb7Ln+HxLkxXDefAZAyWHy1Lkni GglgOk4We2sbNB+U47b6BLARE+JKF8NcUIfNHHsmhKLHnwsohT8ZX8ZsipHI0hYhBcUCsnaqJ8nFp 2YCYXaqzPR7WQgWded6pWDXsqORN8DFe/95rok3C93YL6ZK68PgfD+goWysYWDiAJlxl20RvZL8ec ie67m9z1jDoNQN4YmDKw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1m9IxQ-006rmd-Ek; Fri, 30 Jul 2021 03:13:08 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1m9IxI-006rjp-HD; Fri, 30 Jul 2021 03:13:02 +0000 X-UUID: ea50fadba73b404fbef1650e1c1f11d9-20210729 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:From:Subject:Message-ID; bh=LejJWnZ2JOLo/DhJM3s97omYPuDb/lLAN8IlUBxwa7k=; b=h1+sYkduhXDBwaUJTp2EDoRCqHiU2fZAqAVrU6beVzXSojWToT8zMSE3q3X6js8O/L8optyeXYkCm5sJkapGC1zWUKb5vR4RS1FMmvLLH5AuclJHiJHCa24O1FC7LmwHJ1fdH3VtM7FrGKqin7I2av57DRVK2did+BPU5QyGZes=; X-UUID: ea50fadba73b404fbef1650e1c1f11d9-20210729 Received: from mtkcas67.mediatek.inc [(172.29.193.45)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 975429444; Thu, 29 Jul 2021 20:12:57 -0700 Received: from MTKMBS07N2.mediatek.inc (172.21.101.141) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 29 Jul 2021 20:12:55 -0700 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 30 Jul 2021 11:12:54 +0800 Received: from mtksdccf07 (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 30 Jul 2021 11:12:53 +0800 Message-ID: <526dc9077c696015d1f1065cb6e7f2c7c446ad61.camel@mediatek.com> Subject: Re: [v3 3/5] soc: mediatek: pm-domains: Add support for mt8195 From: Chun-Jie Chen To: Chen-Yu Tsai CC: Enric Balletbo i Serra , Matthias Brugger , Nicolas Boichat , "Rob Herring" , , LKML , , , srv_heupstream , Project_Global_Chrome_Upstream_Group Date: Fri, 30 Jul 2021 11:12:53 +0800 In-Reply-To: References: <20210705054111.4473-1-chun-jie.chen@mediatek.com> <20210705054111.4473-4-chun-jie.chen@mediatek.com> X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210729_201300_634331_1FCAD713 X-CRM114-Status: GOOD ( 26.20 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, 2021-07-20 at 16:51 +0800, Chen-Yu Tsai wrote: > Hi, > On Mon, Jul 5, 2021 at 1:42 PM Chun-Jie Chen < > chun-jie.chen@mediatek.com> wrote: > > > > Add domain control data including bus protection data size > > change due to more protection steps in mt8195. > > > > Signed-off-by: Chun-Jie Chen > > --- > > drivers/soc/mediatek/mt8195-pm-domains.h | 738 > > +++++++++++++++++++++++ > > drivers/soc/mediatek/mtk-pm-domains.c | 5 + > > drivers/soc/mediatek/mtk-pm-domains.h | 2 +- > > include/linux/soc/mediatek/infracfg.h | 103 ++++ > > 4 files changed, 847 insertions(+), 1 deletion(-) > > create mode 100644 drivers/soc/mediatek/mt8195-pm-domains.h > > > > diff --git a/drivers/soc/mediatek/mt8195-pm-domains.h > > b/drivers/soc/mediatek/mt8195-pm-domains.h > > new file mode 100644 > > index 000000000000..54bb7af8e9a3 > > --- /dev/null > > +++ b/drivers/soc/mediatek/mt8195-pm-domains.h > > @@ -0,0 +1,738 @@ > > +/* SPDX-License-Identifier: GPL-2.0-only */ > > +/* > > + * Copyright (c) 2021 MediaTek Inc. > > + * Author: Chun-Jie Chen > > + */ > > + > > +#ifndef __SOC_MEDIATEK_MT8195_PM_DOMAINS_H > > +#define __SOC_MEDIATEK_MT8195_PM_DOMAINS_H > > + > > +#include "mtk-pm-domains.h" > > +#include > > + > > +/* > > + * MT8195 power domain support > > + */ > > + > > +static const struct scpsys_domain_data scpsys_domain_data_mt8195[] > > = { > > The SCPSYS block is not documented in the datasheets available. > However > I did look at all the register and bit offsets and confirmed nothing > overlapped. > > > diff --git a/drivers/soc/mediatek/mtk-pm-domains.c > > b/drivers/soc/mediatek/mtk-pm-domains.c > > index 2689f02d7a41..12552c9996ac 100644 > > --- a/drivers/soc/mediatek/mtk-pm-domains.c > > +++ b/drivers/soc/mediatek/mtk-pm-domains.c > > @@ -20,6 +20,7 @@ > > #include "mt8173-pm-domains.h" > > #include "mt8183-pm-domains.h" > > #include "mt8192-pm-domains.h" > > +#include "mt8195-pm-domains.h" > > > > #define MTK_POLL_DELAY_US 10 > > #define MTK_POLL_TIMEOUT USEC_PER_SEC > > @@ -576,6 +577,10 @@ static const struct of_device_id > > scpsys_of_match[] = { > > .compatible = "mediatek,mt8192-power-controller", > > .data = &mt8192_scpsys_data, > > }, > > + { > > + .compatible = "mediatek,mt8195-power-controller", > > + .data = &mt8195_scpsys_data, > > + }, > > { } > > }; > > > > diff --git a/drivers/soc/mediatek/mtk-pm-domains.h > > b/drivers/soc/mediatek/mtk-pm-domains.h > > index 8b86ed22ca56..caaa38100093 100644 > > --- a/drivers/soc/mediatek/mtk-pm-domains.h > > +++ b/drivers/soc/mediatek/mtk-pm-domains.h > > @@ -37,7 +37,7 @@ > > #define PWR_STATUS_AUDIO BIT(24) > > #define PWR_STATUS_USB BIT(25) > > > > -#define SPM_MAX_BUS_PROT_DATA 5 > > +#define SPM_MAX_BUS_PROT_DATA 6 > > > > #define _BUS_PROT(_mask, _set, _clr, _sta, _update, _ignore) { \ > > .bus_prot_mask = (_mask), \ > > diff --git a/include/linux/soc/mediatek/infracfg.h > > b/include/linux/soc/mediatek/infracfg.h > > index 4615a228da51..3e90fb9b926a 100644 > > --- a/include/linux/soc/mediatek/infracfg.h > > +++ b/include/linux/soc/mediatek/infracfg.h > > @@ -2,6 +2,109 @@ > > #ifndef __SOC_MEDIATEK_INFRACFG_H > > #define __SOC_MEDIATEK_INFRACFG_H > > > > +#define MT8195_TOP_AXI_PROT_EN_STA1 0x228 > > +#define MT8195_TOP_AXI_PROT_EN_1_STA1 0x258 > > +#define MT8195_TOP_AXI_PROT_EN_SET 0x2a0 > > +#define MT8195_TOP_AXI_PROT_EN_CLR 0x2a4 > > +#define MT8195_TOP_AXI_PROT_EN_1_SET 0x2a8 > > +#define MT8195_TOP_AXI_PROT_EN_1_CLR 0x2ac > > +#define MT8195_TOP_AXI_PROT_EN_MM_SET 0x2d4 > > +#define MT8195_TOP_AXI_PROT_EN_MM_CLR 0x2d8 > > +#define MT8195_TOP_AXI_PROT_EN_MM_STA1 0x2ec > > +#define MT8195_TOP_AXI_PROT_EN_2_SET 0x714 > > +#define MT8195_TOP_AXI_PROT_EN_2_CLR 0x718 > > +#define MT8195_TOP_AXI_PROT_EN_2_STA1 0x724 > > +#define MT8195_TOP_AXI_PROT_EN_VDNR_SET 0xb84 > > +#define MT8195_TOP_AXI_PROT_EN_VDNR_CLR 0xb88 > > +#define MT8195_TOP_AXI_PROT_EN_VDNR_STA1 0xb90 > > +#define MT8195_TOP_AXI_PROT_EN_VDNR_1_SET 0xba4 > > +#define MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR 0xba8 > > +#define MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1 0xbb0 > > +#define MT8195_TOP_AXI_PROT_EN_VDNR_2_SET 0xbb8 > > +#define MT8195_TOP_AXI_PROT_EN_VDNR_2_CLR 0xbbc > > +#define MT8195_TOP_AXI_PROT_EN_VDNR_2_STA1 0xbc4 > > +#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET 0xbcc > > +#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR 0xbd0 > > +#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1 0xbd8 > > +#define MT8195_TOP_AXI_PROT_EN_MM_2_SET 0xdcc > > +#define MT8195_TOP_AXI_PROT_EN_MM_2_CLR 0xdd0 > > +#define MT8195_TOP_AXI_PROT_EN_MM_2_STA1 0xdd8 > > These all look correct. > > > +#define MT8195_TOP_AXI_PROT_EN_NNA0 BIT(1) > > +#define MT8195_TOP_AXI_PROT_EN_NNA1 BIT(2) > > +#define MT8195_TOP_AXI_PROT_EN_NNA GENMASK(2, > > 1) > > +#define MT8195_TOP_AXI_PROT_EN_VDOSYS0 BIT(6) > > +#define MT8195_TOP_AXI_PROT_EN_VPPSYS0 BIT(10) > > +#define MT8195_TOP_AXI_PROT_EN_MFG1 BIT(11) > > +#define > > MT8195_TOP_AXI_PROT_EN_MFG1_2ND GENMASK(22, > > 21) > > +#define MT8195_TOP_AXI_PROT_EN_VPPSYS0_2ND BIT(23) > > +#define MT8195_TOP_AXI_PROT_EN_1_MFG1 GENMASK(20, > > 19) > > +#define MT8195_TOP_AXI_PROT_EN_1_CAM BIT(22) > > +#define MT8195_TOP_AXI_PROT_EN_2_CAM BIT(0) > > +#define MT8195_TOP_AXI_PROT_EN_2_MFG1_2ND GENMASK(6, > > 5) > > +#define MT8195_TOP_AXI_PROT_EN_2_MFG1 BIT(7) > > +#define MT8195_TOP_AXI_PROT_EN_2_AUDIO_ASRC (BIT(8) | > > BIT(17)) > > +#define MT8195_TOP_AXI_PROT_EN_2_AUDIO (BIT(9) | > > BIT(11)) > > +#define MT8195_TOP_AXI_PROT_EN_2_ADSP (BIT(12) | > > GENMASK(16, 14)) > > +#define MT8195_TOP_AXI_PROT_EN_2_NNA0_2ND BIT(19) > > +#define MT8195_TOP_AXI_PROT_EN_2_NNA1_2ND BIT(20) > > +#define MT8195_TOP_AXI_PROT_EN_2_NNA_2ND GENMASK(20, > > 19) > > +#define MT8195_TOP_AXI_PROT_EN_2_NNA0 BIT(21) > > +#define MT8195_TOP_AXI_PROT_EN_2_NNA1 BIT(22) > > +#define MT8195_TOP_AXI_PROT_EN_2_NNA GENMASK(22, > > 21) > > +#define MT8195_TOP_AXI_PROT_EN_MM_CAM (BIT(0) | > > BIT(2) | BIT(4)) > > +#define MT8195_TOP_AXI_PROT_EN_MM_IPE BIT(1) > > +#define MT8195_TOP_AXI_PROT_EN_MM_IMG (BIT(1) | > > BIT(3)) > > +#define MT8195_TOP_AXI_PROT_EN_MM_VPPSYS0 (GENMASK(2, > > 0) | GENMASK(8, 6) | \ > > + GENMASK(12, > > 10) | GENMASK(21, 19) | \ > > + BIT(31)) > > +#define MT8195_TOP_AXI_PROT_EN_MM_VDOSYS0 (GENMASK(5, > > 3) | BIT(9) | \ > > + GENMASK(14, > > 13) | GENMASK(21, 17) | \ > > + BIT(30)) > > +#define MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1 GENMASK(8, > > 5) > > +#define MT8195_TOP_AXI_PROT_EN_MM_VENC (BIT(9) | > > BIT(11)) > > +#define MT8195_TOP_AXI_PROT_EN_MM_VENC_CORE1 (BIT(10) | > > BIT(12)) > > +#define > > MT8195_TOP_AXI_PROT_EN_MM_VDEC0 BIT(13) > > +#define > > MT8195_TOP_AXI_PROT_EN_MM_VDEC1 BIT(14) > > +#define MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1_2ND BIT(22) > > +#define MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1_2ND BIT(23) > > +#define MT8195_TOP_AXI_PROT_EN_MM_CAM_2ND BIT(24) > > +#define MT8195_TOP_AXI_PROT_EN_MM_IMG_2ND BIT(25) > > +#define MT8195_TOP_AXI_PROT_EN_MM_VENC_2ND BIT(26) > > +#define MT8195_TOP_AXI_PROT_EN_MM_WPESYS BIT(27) > > +#define MT8195_TOP_AXI_PROT_EN_MM_VDEC0_2ND BIT(28) > > +#define MT8195_TOP_AXI_PROT_EN_MM_VDEC1_2ND BIT(29) > > +#define MT8195_TOP_AXI_PROT_EN_MM_VDOSYS0_2ND GENMASK(29, > > 22) > > +#define MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1 GENMASK(31, > > 30) > > There's significant overlap within this block. This means when the > base > VDOSYS0 power domain is on, all the overlapped protection bits get > turned > off. I'm not sure that's correct. > > Same goes for IMG, which overlaps with IPE. > Because the timing of enable & disable protection are different, we duplicate some control bit in different power domain. For example: IMG & IPE are parent and child relation, so IMG must power on before IPE, IPE must power off before IMG. We want to clear some bits (protection disable) when power on IMG and set some bits (protection enable) when power off IPE. > > +#define > > MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0_2ND (GENMASK(7, > > 0) | GENMASK(18, 11)) > > +#define MT8195_TOP_AXI_PROT_EN_MM_2_VENC BIT(2) > > +#define MT8195_TOP_AXI_PROT_EN_MM_2_VENC_CORE1 (BIT(3) | > > BIT(15)) > > +#define > > MT8195_TOP_AXI_PROT_EN_MM_2_CAM (BIT(5) | > > BIT(17)) > > +#define MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS1 (GENMASK(7, > > 6) | BIT(18)) > > +#define MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0 (GENMASK(9, > > 8) | GENMASK(22, 21) | BIT(24)) > > +#define MT8195_TOP_AXI_PROT_EN_MM_2_VDOSYS1 BIT(10) > > +#define MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2_2ND BIT(12) > > +#define MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0_2ND BIT(13) > > +#define MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS_2ND BIT(14) > > +#define > > MT8195_TOP_AXI_PROT_EN_MM_2_IMG BIT(16) > > +#define > > MT8195_TOP_AXI_PROT_EN_MM_2_IPE BIT(16) > > And here, IMG and IPE are the same. > > > +#define MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2 BIT(21) > > +#define MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0 BIT(22) > > +#define MT8195_TOP_AXI_PROT_EN_MM_2_VDOSYS0 BIT(23) > > +#define MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS GENMASK(24, > > 23) > > +#define MT8195_TOP_AXI_PROT_EN_VDNR_1_EPD_TX BIT(1) > > +#define MT8195_TOP_AXI_PROT_EN_VDNR_1_DP_TX BIT(2) > > +#define > > MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P0 (BIT(11) | > > BIT(28)) > > +#define > > MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P1 (BIT(12) | > > BIT(29)) > > +#define MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P0 BIT(13) > > +#define MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P1 BIT(14) > > +#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1 (BIT(17) | > > BIT(19)) > > +#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VPPSYS0 BIT(20) > > +#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VDOSYS0 BIT(21) > > +#define MT8195_TOP_AXI_PROT_EN_VDNR_2_NNA0 BIT(25) > > +#define MT8195_TOP_AXI_PROT_EN_VDNR_2_NNA1 BIT(26) > > +#define MT8195_TOP_AXI_PROT_EN_VDNR_2_NNA GENMASK(26, > > 25) > > + > > All these MT8195_TOP_AXI_PROT_EN_* bit offsets aren't documented. > Besides > the huge overlap above, it seems NNA also includes NNA0 and NNA1. > > > Regards > ChenYu > The detail of MT8195_TOP_AXI_PROT_EN_* bit is related to the bus design, so we don't descript the detail in datasheet. I will remove the unused power domain and data (like NNA) because these are not used in 8195 chrome project. Best Regards, Chun-Jie > > > #define MT8192_TOP_AXI_PROT_EN_STA1 0x228 > > #define MT8192_TOP_AXI_PROT_EN_1_STA1 0x258 > > #define MT8192_TOP_AXI_PROT_EN_SET 0x2a0 > > -- > > 2.18.0 > > _______________________________________________ > > Linux-mediatek mailing list > > Linux-mediatek@lists.infradead.org > > https://urldefense.com/v3/__http://lists.infradead.org/mailman/listinfo/linux-mediatek__;!!CTRNKA9wMg0ARbw!3jALcSgob2IQknQnQlIPVKd79QdKmXI1Y9X7kaQ2KR8AYdyP0V8Km3u_Cfq8VPMJ4-zn$ > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel