From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753312AbcGTDlo (ORCPT ); Tue, 19 Jul 2016 23:41:44 -0400 Received: from mail-pf0-f179.google.com ([209.85.192.179]:36204 "EHLO mail-pf0-f179.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753136AbcGTDl3 (ORCPT ); Tue, 19 Jul 2016 23:41:29 -0400 From: Andrey Pronin To: Jarkko Sakkinen Cc: Peter Huewe , Marcel Selhorst , Jason Gunthorpe , tpmdd-devel@lists.sourceforge.net, linux-kernel@vger.kernel.org, Christophe Ricard , Andrey Pronin , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , devicetree@vger.kernel.org Subject: [PATCH v2 1/2] tpm: devicetree: document properties for cr50 Date: Tue, 19 Jul 2016 20:41:24 -0700 Message-Id: <5274cc806888a709c639e701dad894543885b2c9.1468985673.git.apronin@chromium.org> X-Mailer: git-send-email 2.8.0.rc3.226.g39d4020 In-Reply-To: References: <1468549218-19215-1-git-send-email-apronin@chromium.org> In-Reply-To: References: <1468549218-19215-1-git-send-email-apronin@chromium.org> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add TPM2.0 PTP FIFO compatible SPI interface for chips with Cr50 firmware. Several timing-related properties that may differ from one firmware version to another are added to devicetree. Document these properties. Signed-off-by: Andrey Pronin --- .../devicetree/bindings/security/tpm/cr50_spi.txt | 32 ++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 Documentation/devicetree/bindings/security/tpm/cr50_spi.txt diff --git a/Documentation/devicetree/bindings/security/tpm/cr50_spi.txt b/Documentation/devicetree/bindings/security/tpm/cr50_spi.txt new file mode 100644 index 0000000..f212b6b --- /dev/null +++ b/Documentation/devicetree/bindings/security/tpm/cr50_spi.txt @@ -0,0 +1,32 @@ +* H1 Secure Microcontroller with Cr50 Firmware on SPI Bus. + +H1 Secure Microcontroller running Cr50 firmware provides several +functions, including TPM-like functionality. It communicates over +SPI using the FIFO protocol described in the PTP Spec, section 6. + +Required properties: +- compatible: Should be "google,cr50". +- spi-max-frequency: Maximum SPI frequency. + +Optional properties: +- access-delay-ms: Required delay between subsequent transactions on SPI. +- sleep-delay-ms: Time after the last SPI activity, after which the chip + may go to sleep. +- wake-start-delay-ms: Time after initiating wake up before the chip is + ready to accept commands over SPI. + +Example: + +&spi0 { + status = "okay"; + + cr50@0 { + compatible = "google,cr50"; + reg = <0>; + spi-max-frequency = <800000>; + + access-delay-ms = <2>; + sleep-delay-ms = <1000>; + wake-start-delay-ms = <60>; + }; +}; -- 2.6.6 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andrey Pronin Subject: [PATCH v2 1/2] tpm: devicetree: document properties for cr50 Date: Tue, 19 Jul 2016 20:41:24 -0700 Message-ID: <5274cc806888a709c639e701dad894543885b2c9.1468985673.git.apronin@chromium.org> References: <1468549218-19215-1-git-send-email-apronin@chromium.org> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: In-Reply-To: References: <1468549218-19215-1-git-send-email-apronin-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: tpmdd-devel-bounces-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org To: Jarkko Sakkinen Cc: Mark Rutland , devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Christophe Ricard , Pawel Moll , Ian Campbell , linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Rob Herring , tpmdd-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org, Kumar Gala List-Id: devicetree@vger.kernel.org Add TPM2.0 PTP FIFO compatible SPI interface for chips with Cr50 firmware. Several timing-related properties that may differ from one firmware version to another are added to devicetree. Document these properties. Signed-off-by: Andrey Pronin --- .../devicetree/bindings/security/tpm/cr50_spi.txt | 32 ++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 Documentation/devicetree/bindings/security/tpm/cr50_spi.txt diff --git a/Documentation/devicetree/bindings/security/tpm/cr50_spi.txt b/Documentation/devicetree/bindings/security/tpm/cr50_spi.txt new file mode 100644 index 0000000..f212b6b --- /dev/null +++ b/Documentation/devicetree/bindings/security/tpm/cr50_spi.txt @@ -0,0 +1,32 @@ +* H1 Secure Microcontroller with Cr50 Firmware on SPI Bus. + +H1 Secure Microcontroller running Cr50 firmware provides several +functions, including TPM-like functionality. It communicates over +SPI using the FIFO protocol described in the PTP Spec, section 6. + +Required properties: +- compatible: Should be "google,cr50". +- spi-max-frequency: Maximum SPI frequency. + +Optional properties: +- access-delay-ms: Required delay between subsequent transactions on SPI. +- sleep-delay-ms: Time after the last SPI activity, after which the chip + may go to sleep. +- wake-start-delay-ms: Time after initiating wake up before the chip is + ready to accept commands over SPI. + +Example: + +&spi0 { + status = "okay"; + + cr50@0 { + compatible = "google,cr50"; + reg = <0>; + spi-max-frequency = <800000>; + + access-delay-ms = <2>; + sleep-delay-ms = <1000>; + wake-start-delay-ms = <60>; + }; +}; -- 2.6.6 ------------------------------------------------------------------------------ What NetFlow Analyzer can do for you? Monitors network bandwidth and traffic patterns at an interface-level. Reveals which users, apps, and protocols are consuming the most bandwidth. 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