From mboxrd@z Thu Jan  1 00:00:00 1970
From: Vandana Kannan <vandana.kannan@intel.com>
Subject: Re: [PATCH 5/5] drm/i915/bdw: Add support for DRRS to
 switch RR
Date: Wed, 18 Dec 2013 15:36:07 +0530
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To: Chris Wilson <chris@chris-wilson.co.uk>
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On Dec-18-2013 2:31 PM, Chris Wilson wrote:
> On Wed, Dec 18, 2013 at 01:54:56PM +0530, Vandana Kannan wrote:
>> On Dec-17-2013 6:00 PM, Chris Wilson wrote:
>>> On Tue, Dec 17, 2013 at 10:58:27AM +0530, Vandana Kannan wrote:
>>>> For Broadwell, there is one instance of Transcoder MN values per transcoder.
>>>> For dynamic switching between multiple refreshr rates, M/N values may be
>>>> reprogrammed on the fly. Link N programming triggers update of all data and
>>>> link M & N registers and the new M/N values will be used in the next frame
>>>> that is output.
>>>>
>>>> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
>>>> Signed-off-by: Pradeep Bhat <pradeep.bhat@intel.com>
>>>> ---
>>>>  drivers/gpu/drm/i915/intel_dp.c |   23 +++++++++++++++++++----
>>>>  1 file changed, 19 insertions(+), 4 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>>>> index 209be3c..183cfd7 100644
>>>> --- a/drivers/gpu/drm/i915/intel_dp.c
>>>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>>>> @@ -798,9 +798,15 @@ intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n)
>>>>  	struct drm_i915_private *dev_priv = dev->dev_private;
>>>>  	enum transcoder transcoder = crtc->config.cpu_transcoder;
>>>>  
>>>> -	if (INTEL_INFO(dev)->gen >= 5 && INTEL_INFO(dev)->gen < 8) {
>>>> +	if (INTEL_INFO(dev)->gen >= 8) {
>>>> +		I915_WRITE(PIPE_DATA_M1(transcoder),
>>>> +			TU_SIZE(m_n->tu) | m_n->gmch_m);
>>>> +		I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
>>>> +		I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
>>>> +		I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
>>>> +	} else if (INTEL_INFO(dev)->gen >= 5 && INTEL_INFO(dev)->gen < 8) {
>>>
>>> Ouch. Double ouch later.
>>> -Chris
>>>
>> We are looking to write in M1/N1 registers for BDW and M2/N2 registers
>> for HSW and below. What is your suggestion on how to implement this ?
> 
>   if (gen >= 8) {
>   } else if (gen >= 5) {
>   }
> 
> Or as you use gen >= 5 && gen < 8 elsewhere, a feature macro would be
> even more sensible, HAS_DRRS().
> -Chris
> 
I will make this change to
   if (gen >= 8) {
   } else if (gen >= 5) {
   }
- Vandana