From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Jan Beulich" Subject: Re: [PATCH V4.1] mcheck, vmce: Allow vmce_amd_* functions to handle AMD thresolding MSRs Date: Fri, 14 Feb 2014 08:28:46 +0000 Message-ID: <52FDE1CE020000780011C575@nat28.tlf.novell.com> References: <1392247608-6960-1-git-send-email-aravind.gopalakrishnan@amd.com> <52FC927D020000780011BF0A@nat28.tlf.novell.com> <52FD0079.8050601@amd.com> <52FD0DCC.1030904@amd.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <52FD0DCC.1030904@amd.com> Content-Disposition: inline List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: chegger@amazon.de, Aravind Gopalakrishnan Cc: jinsong.liu@intel.com, boris.ostrovsky@oracle.com, suravee.suthikulpanit@amd.com, xen-devel@lists.xen.org List-Id: xen-devel@lists.xenproject.org >>> On 13.02.14 at 19:24, Aravind Gopalakrishnan wrote: > On 2/13/2014 11:27 AM, Aravind Gopalakrishnan wrote: >> On 2/13/2014 2:38 AM, Jan Beulich wrote: >>>> *val = 0; >>>> - switch ( msr & (MSR_IA32_MC0_CTL | 3) ) >>>> + /* Allow only first 3 MC banks into switch() */ >>>> + switch ( msr & (-MSR_IA32_MC0_CTL | 3) ) >>>> { >>>> case MSR_IA32_MC0_CTL: >>>> /* stick all 1's to MCi_CTL */ >>> I'm confused: You now add a comment as if the mask was including >>> bit 4, which it doesn't. What am I missing? >> >> Darn. Sorry about that. Will fix.. > > Jan, > > Do let me know if the following wording is fine: > > /* > * Apply mask to allow bits[0:1] (necessary to uniquely identify MC0) > * MC1 is handled by virtue of 'bank' value. > */ > > If not, I'm open to suggestions:) I don't particularly like this, but I also don't have a good alternative suggestion. It was Christoph who asked for a comment in the first place. Since I don't see a particular need for a comment here, you two should work out what best suits both of you. Jan