From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40394) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WEKmA-0003aV-62 for qemu-devel@nongnu.org; Fri, 14 Feb 2014 10:34:07 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WEKm4-0008Vc-R1 for qemu-devel@nongnu.org; Fri, 14 Feb 2014 10:34:01 -0500 Received: from cantor2.suse.de ([195.135.220.15]:48311 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WEKm4-0008VP-H8 for qemu-devel@nongnu.org; Fri, 14 Feb 2014 10:33:56 -0500 Message-ID: <52FE3761.7020403@suse.de> Date: Fri, 14 Feb 2014 16:33:53 +0100 From: =?UTF-8?B?QW5kcmVhcyBGw6RyYmVy?= MIME-Version: 1.0 References: <1392391000-5687-1-git-send-email-sebastian.huber@embedded-brains.de> In-Reply-To: <1392391000-5687-1-git-send-email-sebastian.huber@embedded-brains.de> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH v3] target-sparc: Add and use CPU_FEATURE_CASA List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Sebastian Huber , qemu-devel@nongnu.org Cc: blauwirbel@gmail.com, Fabien Chouteau Am 14.02.2014 16:16, schrieb Sebastian Huber: > The LEON3 processor has support for the CASA instruction which is > normally only available for SPARC V9 processors. Binutils 2.24 > and GCC 4.9 will support this instruction for LEON3. GCC uses it to > generate C11 atomic operations. >=20 > The CAS synthetic instruction uses an ASI of 0x80. If TARGET_SPARC64 i= s > not defined use a supervisor data load/store for an ASI of 0x80 in > helper_ld_asi()/helper_st_asi(). The supervisor data load/store was > choosen according to the LEON3 documentation. >=20 > The ASI 0x80 is defined in the SPARC V9 manual, Table 12=E2=80=94Addres= s Space > Identifiers (ASIs). Here we have: 0x80, ASI_PRIMARY, Unrestricted > access, Primary address space. >=20 > Tested with the following program: >=20 > #include > #include >=20 > void test(void) > { > atomic_int a; > int e; > _Bool b; >=20 > atomic_store(&a, 1); > e =3D 1; > b =3D atomic_compare_exchange_strong(&a, &e, 2); > assert(b); > assert(atomic_load(&a) =3D=3D 2); >=20 > atomic_store(&a, 3); > e =3D 4; > b =3D atomic_compare_exchange_strong(&a, &e, 5); > assert(!b); > assert(atomic_load(&a) =3D=3D 3); > } >=20 > Tested also on a NGMP board with a LEON4 processor. >=20 > Signed-off-by: Sebastian Huber > Reviewed-by: Fabien Chouteau > --- > target-sparc/cpu.c | 3 +- > target-sparc/cpu.h | 4 ++- > target-sparc/helper.h | 4 ++- > target-sparc/ldst_helper.c | 28 +++++++++++++++----------- > target-sparc/translate.c | 47 ++++++++++++++++++++++++++++--------= ------- > 5 files changed, 54 insertions(+), 32 deletions(-) >=20 > diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c > index e7f878e..5806e59 100644 > --- a/target-sparc/cpu.c > +++ b/target-sparc/cpu.c > @@ -458,7 +458,8 @@ static const sparc_def_t sparc_defs[] =3D { > .mmu_trcr_mask =3D 0xffffffff, > .nwindows =3D 8, > .features =3D CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN = | > - CPU_FEATURE_ASR17 | CPU_FEATURE_CACHE_CTRL | CPU_FEATURE_POWER= DOWN, > + CPU_FEATURE_ASR17 | CPU_FEATURE_CACHE_CTRL | CPU_FEATURE_POWER= DOWN | > + CPU_FEATURE_CASA, > }, > #endif > }; > diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h > index c519063..2531cf9 100644 > --- a/target-sparc/cpu.h > +++ b/target-sparc/cpu.h > @@ -271,12 +271,14 @@ typedef struct sparc_def_t { > #define CPU_FEATURE_ASR17 (1 << 15) > #define CPU_FEATURE_CACHE_CTRL (1 << 16) > #define CPU_FEATURE_POWERDOWN (1 << 17) > +#define CPU_FEATURE_CASA (1 << 18) > =20 > #ifndef TARGET_SPARC64 > #define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | = \ > CPU_FEATURE_MUL | CPU_FEATURE_DIV | = \ > CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | = \ > - CPU_FEATURE_FMUL | CPU_FEATURE_FSMULD) > + CPU_FEATURE_FMUL | CPU_FEATURE_FSMULD | = \ > + CPU_FEATURE_CASA) > #else > #define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | = \ > CPU_FEATURE_MUL | CPU_FEATURE_DIV | = \ > diff --git a/target-sparc/helper.h b/target-sparc/helper.h > index 2a771b2..cd8d3fa 100644 > --- a/target-sparc/helper.h > +++ b/target-sparc/helper.h > @@ -22,7 +22,6 @@ DEF_HELPER_1(popc, tl, tl) > DEF_HELPER_4(ldda_asi, void, env, tl, int, int) > DEF_HELPER_5(ldf_asi, void, env, tl, int, int, int) > DEF_HELPER_5(stf_asi, void, env, tl, int, int, int) > -DEF_HELPER_5(cas_asi, tl, env, tl, tl, tl, i32) > DEF_HELPER_5(casx_asi, tl, env, tl, tl, tl, i32) > DEF_HELPER_2(set_softint, void, env, i64) > DEF_HELPER_2(clear_softint, void, env, i64) > @@ -31,6 +30,9 @@ DEF_HELPER_2(tick_set_count, void, ptr, i64) > DEF_HELPER_1(tick_get_count, i64, ptr) > DEF_HELPER_2(tick_set_limit, void, ptr, i64) > #endif > +#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) > +DEF_HELPER_5(cas_asi, tl, env, tl, tl, tl, i32) > +#endif > DEF_HELPER_3(check_align, void, env, tl, i32) > DEF_HELPER_1(debug, void, env) > DEF_HELPER_1(save, void, env) > diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c > index 92761ad..32491b4 100644 > --- a/target-sparc/ldst_helper.c > +++ b/target-sparc/ldst_helper.c > @@ -584,6 +584,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_u= long addr, int asi, int size, > } > break; > case 0xb: /* Supervisor data access */ > + case 0x80: > switch (size) { > case 1: > ret =3D cpu_ldub_kernel(env, addr); > @@ -955,6 +956,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong= addr, uint64_t val, int asi, > } > break; > case 0xb: /* Supervisor data access */ > + case 0x80: > switch (size) { > case 1: > cpu_stb_kernel(env, addr, val); > @@ -2232,33 +2234,35 @@ void helper_stf_asi(CPUSPARCState *env, target_= ulong addr, int asi, int size, > } > } > =20 > -target_ulong helper_cas_asi(CPUSPARCState *env, target_ulong addr, > - target_ulong val1, target_ulong val2, uint= 32_t asi) > +target_ulong helper_casx_asi(CPUSPARCState *env, target_ulong addr, > + target_ulong val1, target_ulong val2, > + uint32_t asi) > { > target_ulong ret; > =20 > - val2 &=3D 0xffffffffUL; > - ret =3D helper_ld_asi(env, addr, asi, 4, 0); > - ret &=3D 0xffffffffUL; > + ret =3D helper_ld_asi(env, addr, asi, 8, 0); > if (val2 =3D=3D ret) { > - helper_st_asi(env, addr, val1 & 0xffffffffUL, asi, 4); > + helper_st_asi(env, addr, val1, asi, 8); > } > return ret; > } > +#endif /* TARGET_SPARC64 */ > =20 > -target_ulong helper_casx_asi(CPUSPARCState *env, target_ulong addr, > - target_ulong val1, target_ulong val2, > - uint32_t asi) > +#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) > +target_ulong helper_cas_asi(CPUSPARCState *env, target_ulong addr, > + target_ulong val1, target_ulong val2, uint= 32_t asi) > { > target_ulong ret; > =20 > - ret =3D helper_ld_asi(env, addr, asi, 8, 0); > + val2 &=3D 0xffffffffUL; > + ret =3D helper_ld_asi(env, addr, asi, 4, 0); > + ret &=3D 0xffffffffUL; > if (val2 =3D=3D ret) { > - helper_st_asi(env, addr, val1, asi, 8); > + helper_st_asi(env, addr, val1 & 0xffffffffUL, asi, 4); > } > return ret; > } > -#endif /* TARGET_SPARC64 */ > +#endif /* !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) */ > =20 > void helper_ldqf(CPUSPARCState *env, target_ulong addr, int mem_idx) > { > diff --git a/target-sparc/translate.c b/target-sparc/translate.c > index 6150b22..7481c85 100644 > --- a/target-sparc/translate.c > +++ b/target-sparc/translate.c > @@ -2107,18 +2107,6 @@ static inline void gen_stda_asi(DisasContext *dc= , TCGv hi, TCGv addr, > tcg_temp_free_i64(t64); > } > =20 > -static inline void gen_cas_asi(DisasContext *dc, TCGv addr, > - TCGv val2, int insn, int rd) > -{ > - TCGv val1 =3D gen_load_gpr(dc, rd); > - TCGv dst =3D gen_dest_gpr(dc, rd); > - TCGv_i32 r_asi =3D gen_get_asi(insn, addr); > - > - gen_helper_cas_asi(dst, cpu_env, addr, val1, val2, r_asi); > - tcg_temp_free_i32(r_asi); > - gen_store_gpr(dc, rd, dst); > -} > - > static inline void gen_casx_asi(DisasContext *dc, TCGv addr, > TCGv val2, int insn, int rd) > { > @@ -2229,6 +2217,22 @@ static inline void gen_stda_asi(DisasContext *dc= , TCGv hi, TCGv addr, > #endif > =20 > #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) > +static inline void gen_cas_asi(DisasContext *dc, TCGv addr, > + TCGv val2, int insn, int rd) > +{ > + TCGv val1 =3D gen_load_gpr(dc, rd); > + TCGv dst =3D gen_dest_gpr(dc, rd); > +#ifdef TARGET_SPARC64 > + TCGv_i32 r_asi =3D gen_get_asi(insn, addr); > +#else > + TCGv_i32 r_asi =3D tcg_const_i32(GET_FIELD(insn, 19, 26)); > +#endif > + > + gen_helper_cas_asi(dst, cpu_env, addr, val1, val2, r_asi); > + tcg_temp_free_i32(r_asi); > + gen_store_gpr(dc, rd, dst); > +} > + > static inline void gen_ldstub_asi(TCGv dst, TCGv addr, int insn) > { > TCGv_i64 r_val; > @@ -5103,11 +5107,6 @@ static void disas_sparc_insn(DisasContext * dc, = unsigned int insn) > } > gen_stf_asi(cpu_addr, insn, 8, DFPREG(rd)); > break; > - case 0x3c: /* V9 casa */ > - rs2 =3D GET_FIELD(insn, 27, 31); > - cpu_src2 =3D gen_load_gpr(dc, rs2); > - gen_cas_asi(dc, cpu_addr, cpu_src2, insn, rd); > - break; > case 0x3e: /* V9 casxa */ > rs2 =3D GET_FIELD(insn, 27, 31); > cpu_src2 =3D gen_load_gpr(dc, rs2); > @@ -5120,6 +5119,20 @@ static void disas_sparc_insn(DisasContext * dc, = unsigned int insn) > case 0x37: /* stdc */ > goto ncp_insn; > #endif > +#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) > + case 0x3c: /* V9 or LEON3 casa */ > + CHECK_FPU_FEATURE(dc, CASA); > +#ifndef TARGET_SPARC64 > + if (IS_IMM) Did you forget to run checkpatch.pl? Missing braces here ... > + goto illegal_insn; > + if (!supervisor(dc)) ... and here. > + goto priv_insn; Otherwise patch looks okay, thanks for the subject normalization. As for the other one you'll need to sort our who sends a pull if Blue doesn't resurface - I note that qemu-trivial is not CC'ed here and the patch probably isn't anyway. Maybe Fabien can help out with that? More generally, independent of this patch with test case in its commit message, you may want to consider setting up tests/tcg/sparc/ for test cases and/or use qtest with accel=3Dtcg similar to what mst did for ACPI regression testing. Regards, Andreas > +#endif > + rs2 =3D GET_FIELD(insn, 27, 31); > + cpu_src2 =3D gen_load_gpr(dc, rs2); > + gen_cas_asi(dc, cpu_addr, cpu_src2, insn, rd); > + break; > +#endif > default: > goto illegal_insn; > } >=20 --=20 SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N=C3=BCrnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imend=C3=B6rffer; HRB 16746 AG N=C3=BC= rnberg