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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id q13sm2834687pfg.155.2021.02.17.07.11.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 17 Feb 2021 07:11:40 -0800 (PST) Subject: Re: [PATCH] pc-bios/s390-ccw: Use memory barriers in virtio code To: Peter Maydell References: <20210216110056.1228582-1-thuth@redhat.com> <20210216154010.3691880f.pasic@linux.ibm.com> <72e9a5b3-dd88-85de-e4a8-88a6a9c45099@redhat.com> <5c37f1f1-5538-cd06-55a2-e266cc9a972c@linaro.org> From: Richard Henderson Message-ID: <52bc865c-9e4d-ebfa-e7c0-15747f194532@linaro.org> Date: Wed, 17 Feb 2021 07:11:37 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , Cornelia Huck , QEMU Developers , Halil Pasic , Christian Borntraeger , qemu-s390x Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 2/17/21 3:15 AM, Peter Maydell wrote: > This isn't aarch64-host-specific, though, is it? It's going to be > the situation for any host with a relaxed memory model. Yes. I intend to make the code-generation changes generic. > Do we really > want to make all loads and stores lower-performance by adding in > the ldacq/strel (or worse, barriers everywhere on host archs without > ldacq/strel)? Well, yes. But then we get to enable mttcg too. > I feel like there ought to be an alternate approach > involving using some kind of exclusion to ensure that we don't run > the iothreads in parallel with the vCPU thread if we're using the > non-MTTCG setup where all the vCPUs are on a single thread, and that > that's probably less of a perf hit. I don't know where to put such a block, do you? The memory barriers are a perf hit with -smp 1, but I would think that all that and more are recoverable by not having to run -smp 2 serially. r~