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Wed, 12 Feb 2020 23:51:42 -0800 Received: from xsj-pvapsmtp01 (smtp2.xilinx.com [149.199.38.66]) by xsj-smtp-dlp1.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id 01D7pfBq031167; Wed, 12 Feb 2020 23:51:41 -0800 Received: from [172.30.17.107] by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1j29Hg-0000uy-SI; Wed, 12 Feb 2020 23:51:41 -0800 Subject: Re: [PATCH 6/7] microblaze: Implement architecture spinlock To: Peter Zijlstra , Michal Simek Cc: linux-kernel@vger.kernel.org, monstr@monstr.eu, git@xilinx.com, arnd@arndb.de, Stefan Asserhall , Ingo Molnar , Will Deacon References: <20200212154756.GY14897@hirez.programming.kicks-ass.net> From: Michal Simek Message-ID: <5315513c-2492-6bb7-2961-b249851b2051@xilinx.com> Date: Thu, 13 Feb 2020 08:51:38 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 MIME-Version: 1.0 In-Reply-To: <20200212154756.GY14897@hirez.programming.kicks-ass.net> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83;IPV:;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(4636009)(396003)(376002)(136003)(346002)(39860400002)(189003)(199004)(81156014)(8676002)(4326008)(81166006)(31696002)(8936002)(2906002)(36756003)(9786002)(44832011)(336012)(2616005)(426003)(54906003)(26005)(31686004)(186003)(478600001)(6666004)(110136005)(356004)(5660300002)(70586007)(70206006)(316002);DIR:OUT;SFP:1101;SCL:1;SRVR:CY4PR02MB3383;H:xsj-pvapsmtpgw01;FPR:;SPF:Pass;LANG:en;PTR:unknown-60-83.xilinx.com;MX:1;A:1; X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 7a9e8892-6f34-4d2d-b7b3-08d7b0599460 X-MS-TrafficTypeDiagnostic: CY4PR02MB3383: X-LD-Processed: 657af505-d5df-48d0-8300-c31994686c5c,ExtAddr X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:8882; X-Forefront-PRVS: 031257FE13 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: IcUNaYSqUWeHHpq3u0wHj8A2YU+67JDpAnOEIMD0CWia2/981mHCZMxzjm2pyeKmyMfC4bt7ggMMEVCYe2fACr3qXnolvFS78iRsNws+SQaTZ4IBzwS+WTXcCQli5OgHTCrMaIXg+QEZ0bTZKWKAPzUrp9TbWbNNm0iNJXXSpxRub0RdC3/l9a5oHv01MsVbMiyD+uQxk7CjDEhGrZbM33OPb14ZCrporPACHVPIjI3Xa07g5TxJiJSnn+xPIy7h5xQ88ynqGxbKvQbUO9JI91WYiY+Y6sUmGC4t21pFxBezT/qJUpFq4w47yn644xLj00dPYYG0JHhX2aUo2EPMfZ1k4+PU8k0Zw426z8wDUjevsTYmaCJlbfrOZmSH4MsVziVs/kWQbYogNTs3dY5PaPWi39H5OqDCdaUi05Sh9pOZmZTYRpgt0QKCSi/D86RV X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Feb 2020 07:51:48.2867 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7a9e8892-6f34-4d2d-b7b3-08d7b0599460 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.60.83];Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR02MB3383 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 12. 02. 20 16:47, Peter Zijlstra wrote: > On Wed, Feb 12, 2020 at 04:42:28PM +0100, Michal Simek wrote: >> From: Stefan Asserhall >> >> Using exclusive loads/stores to implement spinlocks which can be used on >> SMP systems. >> >> Signed-off-by: Stefan Asserhall >> Signed-off-by: Michal Simek >> --- >> >> arch/microblaze/include/asm/spinlock.h | 240 +++++++++++++++++++ >> arch/microblaze/include/asm/spinlock_types.h | 25 ++ >> 2 files changed, 265 insertions(+) >> create mode 100644 arch/microblaze/include/asm/spinlock.h >> create mode 100644 arch/microblaze/include/asm/spinlock_types.h >> >> diff --git a/arch/microblaze/include/asm/spinlock.h b/arch/microblaze/include/asm/spinlock.h >> new file mode 100644 >> index 000000000000..0199ea9f7f0f >> --- /dev/null >> +++ b/arch/microblaze/include/asm/spinlock.h >> @@ -0,0 +1,240 @@ >> +/* SPDX-License-Identifier: GPL-2.0 */ >> +/* >> + * Copyright (C) 2013-2020 Xilinx, Inc. >> + */ >> + >> +#ifndef _ASM_MICROBLAZE_SPINLOCK_H >> +#define _ASM_MICROBLAZE_SPINLOCK_H >> + >> +/* >> + * Unlocked value: 0 >> + * Locked value: 1 >> + */ >> +#define arch_spin_is_locked(x) (READ_ONCE((x)->lock) != 0) >> + >> +static inline void arch_spin_lock(arch_spinlock_t *lock) >> +{ >> + unsigned long tmp; >> + >> + __asm__ __volatile__ ( >> + /* load conditional address in %1 to %0 */ >> + "1: lwx %0, %1, r0;\n" >> + /* not zero? try again */ >> + " bnei %0, 1b;\n" >> + /* increment lock by 1 */ >> + " addi %0, r0, 1;\n" >> + /* attempt store */ >> + " swx %0, %1, r0;\n" >> + /* checking msr carry flag */ >> + " addic %0, r0, 0;\n" >> + /* store failed (MSR[C] set)? try again */ >> + " bnei %0, 1b;\n" >> + /* Outputs: temp variable for load result */ >> + : "=&r" (tmp) >> + /* Inputs: lock address */ >> + : "r" (&lock->lock) >> + : "cc", "memory" >> + ); >> +} > > That's a test-and-set spinlock if I read it correctly. Why? that's the > worst possible spinlock implementation possible. This was written by Stefan and it is aligned with recommended implementation. What other options do we have? Thanks, Michal