Re: [patch net-next RFC 0/4] introduce infrastructure for support of switch chip datapath

From: Jamal Hadi Salim <jhs@mojatatu.com>
To: Jiri Pirko <jiri@resnulli.us>, Florian Fainelli <f.fainelli@gmail.com>
Cc: Roopa Prabhu <roopa@cumulusnetworks.com>,
	Neil Horman <nhorman@tuxdriver.com>, Thomas Graf <tgraf@suug.ch>,
	netdev <netdev@vger.kernel.org>,
	David Miller <davem@davemloft.net>,
	Andy Gospodarek <andy@greyhouse.net>,
	dborkman <dborkman@redhat.com>, ogerlitz <ogerlitz@mellanox.com>,
	jesse <jesse@nicira.com>, pshelar <pshelar@nicira.com>,
	azhou <azhou@nicira.com>, Ben Hutchings <ben@decadent.org.uk>,
	Stephen Hemminger <stephen@networkplumber.org>,
	jeffrey.t.kirsher@intel.com, vyasevic <vyasevic@redhat.com>,
	Cong Wang <xiyou.wangcong@gmail.com>,
	John Fastabend <john.r.fastabend@intel.com>,
	Eric Dumazet <edumazet@google.com>,
	Scott Feldman <sfeldma@cumulusnetworks.com>,
	Lennert Buytenhek <buytenh@wantstofly.org>,
	Shrijeet Mukherjee <shm@cumulusnetworks.com>
Subject: Re: [patch net-next RFC 0/4] introduce infrastructure for support of switch chip datapath
Date: Wed, 26 Mar 2014 17:51:22 -0400	[thread overview]
Message-ID: <53334BDA.1060608@mojatatu.com> (raw)
In-Reply-To: <20140326181436.GL2869@minipsycho.orion>

On 03/26/14 14:14, Jiri Pirko wrote:
> Wed, Mar 26, 2014 at 06:58:32PM CET, f.fainelli@gmail.com wrote:
>> 2014-03-26 10:35 GMT-07:00 Jiri Pirko <jiri@resnulli.us>:

>> You are right, sw1p0 and sw1p1 were meant to be, say LAN ports in my example.
>>
>> I think there is an implicit convention that sw1 represents the
>> Ethernet switch port connected to the CPU Ethernet MAC, and that it is
>> always connected, hence there is no need to create a "fake" bridge to
>> link sw1 to eth0 for instance?
>
> I think you are kind of mixing apples and oranges (or I might be I'm not
> understanding you correctly).
> This is how I see it, sticking to the names you use in the example:
>
>              (sw1) (abstract place-holder netdev)
>            --------
>           switch chip                   CPU
>     -----------------------            ------
>     sw1p0 sw1p1 sw1p2 sw1p3             eth0
>       |     |     |     |                |
>      PHY   PHY   PHY    ------someMII-----
>
> You see that eth0 is the CPU part of the "connection" and sw1p3 is the
> switch part (port representation).
>

Florian - I am sure you explained this before; I just dont remember. Why
is there need to expose eth0? It seems to me sw1p0-3 are abstracted
already in the kernel and the "cpu port" is merely a control interface.

Note: even the high end chips tend to have the concept of a "cpu port"
but my experience is to hide that as part of the switch driver.

cheers,
jamal