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Date: Fri, 28 Mar 2014 18:35:33 +0100
From: Gilles Chanteperdrix <gilles.chanteperdrix@xenomai.org>
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Subject: Re: [Xenomai] imx6q xenomai  ipipe-3.0-imx6q
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On 03/28/2014 06:02 AM, 嵌入式工程师 wrote:
> This is my logs
>
>
>
>
 > (...)
> hw perfevents: enabled with ARMv7 Cortex-A9 PMU driver, 7 counters available

I guess you should probably not enable perf. On some architectures, it 
creates unwanted latencies, by using NMI.

 > (...)
> l2x0: 16 ways, CACHE_ID 0x410000c7, AUX_CTRL 0x02870000, Cache size: 1048576 B

So, your auxiliary register has bit 23 set (0x800000), and has L2 write 
allocate disabled.

-- 
					    Gilles.