From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756546AbaEINXU (ORCPT ); Fri, 9 May 2014 09:23:20 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:56735 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755877AbaEINXR (ORCPT ); Fri, 9 May 2014 09:23:17 -0400 Message-ID: <536CD6BD.9000804@ti.com> Date: Fri, 9 May 2014 08:23:09 -0500 From: Nishanth Menon User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.5.0 MIME-Version: 1.0 To: jonghwan Choi , Viresh Kumar CC: Jonghwan Choi , Linux PM list , open list , "Rafael J. Wysocki" , Len Brown , Amit Daniel Kachhap Subject: Re: [PATCH 1/3] PM / OPP: Add support for descending order for cpufreq table References: <000001cf643d$69e5e350$3db1a9f0$@samsung.com> <5367946F.1030407@ti.com> <003e01cf6984$fb950280$f2bf0780$@samsung.com> <001501cf6a5c$07bc2520$17346f60$@samsung.com> <000301cf6a62$413c16b0$c3b44410$@samsung.com> <000e01cf6b23$58fda900$0af8fb00$@samsung.com> In-Reply-To: Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 05/09/2014 06:59 AM, jonghwan Choi wrote: > On Thu, May 8, 2014 at 11:00 PM, Viresh Kumar wrote: > >> Why? So, as far as I got it your dividers are nothing but 0,1,2... >> i.e. >> Freqs: 400 500 600 700 800 >> div: 4 3 2 1 0 >> >> right? That's what you are doing in exynos5440. So just add this in your >> probe after doing: dev_pm_opp_init_cpufreq_table >> >> for(i = 0; all-available-freqs; i++) >> dvfs_info->freq_table[i].driver_data = dvfs_info->freq_count - i; >> >> And this will work with changes in dts files. > > I am sorry > I couldn’t provide detailed information about this suggestion. > This suggestion is not for exynos5440. This is for exynos4210, > exynos4x12 and exynos5250. > (But this can be applied to exynos5440 also) > I want to make exynos cpufreq driver simple. > There are exynos-cpufreq.c, exynos4210-cpufreq.c exynos4x12-cpufreq. > exynos5250-cpufreq.c for exynos soc. > And exynos4210-cpufreq.c, exynos4x12 and exynos5250-cpufreq. c has a > clk divider table for each frequency. > > example) exynos4210-cpufreq.c > static struct apll_freq apll_freq_4210[] = { > /* > * values: > * freq > * clock divider for CORE, COREM0, COREM1, PERIPH, ATB, > PCLK_DBG, APLL, RESERVED > * clock divider for COPY, HPM, RESERVED > * PLL M, P, S > */ > APLL_FREQ(1200, 0, 3, 7, 3, 4, 1, 7, 0, 5, 0, 0, 150, 3, 1), > APLL_FREQ(1000, 0, 3, 7, 3, 4, 1, 7, 0, 4, 0, 0, 250, 6, 1), > APLL_FREQ(800, 0, 3, 7, 3, 3, 1, 7, 0, 3, 0, 0, 200, 6, 1), > APLL_FREQ(500, 0, 3, 7, 3, 3, 1, 7, 0, 3, 0, 0, 250, 6, 2), > APLL_FREQ(200, 0, 1, 3, 1, 3, 1, 0, 0, 3, 0, 0, 200, 6, 3), > }; > > If we can pass this clk divider value to exynos cpufreq driver through > DT, we can remove most of exynosxxxx-cpufreq.c files/codes. And when > new frequency is added/removed or new soc is released, for supporting > dvfs we have only to describe frequency, voltage and divider value in > dts file. Have you considered the option of having a clock driver which can decide the divider (based on dts OR index or whatever)? example: you could do clk_set_rate(apll, rate); and instead of implementing clock divider programmation inside cpufreq driver, you let corresponding clock driver do it for you. that allows you to reuse clock driver with various parameters needed for your SoC variations. IMHO, we are trying to solve a problem meant to be solved in clock framework instead of within cpufreq. -- Regards, Nishanth Menon From mboxrd@z Thu Jan 1 00:00:00 1970 From: Nishanth Menon Subject: Re: [PATCH 1/3] PM / OPP: Add support for descending order for cpufreq table Date: Fri, 9 May 2014 08:23:09 -0500 Message-ID: <536CD6BD.9000804@ti.com> References: <000001cf643d$69e5e350$3db1a9f0$@samsung.com> <5367946F.1030407@ti.com> <003e01cf6984$fb950280$f2bf0780$@samsung.com> <001501cf6a5c$07bc2520$17346f60$@samsung.com> <000301cf6a62$413c16b0$c3b44410$@samsung.com> <000e01cf6b23$58fda900$0af 8fb00$@samsung.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: QUOTED-PRINTABLE Return-path: Received: from arroyo.ext.ti.com ([192.94.94.40]:56735 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755877AbaEINXR (ORCPT ); Fri, 9 May 2014 09:23:17 -0400 In-Reply-To: Sender: linux-pm-owner@vger.kernel.org List-Id: linux-pm@vger.kernel.org To: jonghwan Choi , Viresh Kumar Cc: Jonghwan Choi , Linux PM list , open list , "Rafael J. Wysocki" , Len Brown , Amit Daniel Kachhap On 05/09/2014 06:59 AM, jonghwan Choi wrote: > On Thu, May 8, 2014 at 11:00 PM, Viresh Kumar wrote: >=20 >> Why? So, as far as I got it your dividers are nothing but 0,1,2... >> i.e. >> Freqs: 400 500 600 700 800 >> div: 4 3 2 1 0 >> >> right? That's what you are doing in exynos5440. So just add this in = your >> probe after doing: dev_pm_opp_init_cpufreq_table >> >> for(i =3D 0; all-available-freqs; i++) >> dvfs_info->freq_table[i].driver_data =3D dvfs_info->freq_count -= i; >> >> And this will work with changes in dts files. >=20 > I am sorry > I couldn=92t provide detailed information about this suggestion. > This suggestion is not for exynos5440. This is for exynos4210, > exynos4x12 and exynos5250. > (But this can be applied to exynos5440 also) > I want to make exynos cpufreq driver simple. > There are exynos-cpufreq.c, exynos4210-cpufreq.c exynos4x12-cpufreq. > exynos5250-cpufreq.c for exynos soc. > And exynos4210-cpufreq.c, exynos4x12 and exynos5250-cpufreq. c has a > clk divider table for each frequency. >=20 > example) exynos4210-cpufreq.c > static struct apll_freq apll_freq_4210[] =3D { > /* > * values: > * freq > * clock divider for CORE, COREM0, COREM1, PERIPH, ATB, > PCLK_DBG, APLL, RESERVED > * clock divider for COPY, HPM, RESERVED > * PLL M, P, S > */ > APLL_FREQ(1200, 0, 3, 7, 3, 4, 1, 7, 0, 5, 0, 0, 150, 3, 1), > APLL_FREQ(1000, 0, 3, 7, 3, 4, 1, 7, 0, 4, 0, 0, 250, 6, 1), > APLL_FREQ(800, 0, 3, 7, 3, 3, 1, 7, 0, 3, 0, 0, 200, 6, 1), > APLL_FREQ(500, 0, 3, 7, 3, 3, 1, 7, 0, 3, 0, 0, 250, 6, 2), > APLL_FREQ(200, 0, 1, 3, 1, 3, 1, 0, 0, 3, 0, 0, 200, 6, 3), > }; >=20 > If we can pass this clk divider value to exynos cpufreq driver throug= h > DT, we can remove most of exynosxxxx-cpufreq.c files/codes. And when > new frequency is added/removed or new soc is released, for supporting > dvfs we have only to describe frequency, voltage and divider value in > dts file. Have you considered the option of having a clock driver which can decide the divider (based on dts OR index or whatever)? example: you could do clk_set_rate(apll, rate); and instead of implementing clock divider programmation inside cpufreq driver, you let corresponding clock driver do it for you. that allows you to reuse clock driver with various parameters needed for your SoC variations. IMHO, we are trying to solve a problem meant to be solved in clock framework instead of within cpufreq. --=20 Regards, Nishanth Menon