From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B55F3C433FE for ; Thu, 24 Nov 2022 18:30:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229816AbiKXSai (ORCPT ); Thu, 24 Nov 2022 13:30:38 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50600 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229848AbiKXSaa (ORCPT ); Thu, 24 Nov 2022 13:30:30 -0500 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 01F0A88B74; Thu, 24 Nov 2022 10:30:25 -0800 (PST) Received: from ip5b412258.dynamic.kabel-deutschland.de ([91.65.34.88] helo=diego.localnet) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1oyGzE-0007Jc-Tu; Thu, 24 Nov 2022 19:30:12 +0100 From: Heiko =?ISO-8859-1?Q?St=FCbner?= To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Guo Ren , Prabhakar Cc: Jisheng Zhang , Atish Patra , Anup Patel , Andrew Jones , Nathan Chancellor , Philipp Tomsich , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar Subject: Re: [PATCH v4 7/7] soc: renesas: Add L2 cache management for RZ/Five SoC Date: Thu, 24 Nov 2022 19:30:11 +0100 Message-ID: <5382916.ejJDZkT8p0@diego> In-Reply-To: <20221124172207.153718-8-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20221124172207.153718-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20221124172207.153718-8-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Am Donnerstag, 24. November 2022, 18:22:07 CET schrieb Prabhakar: > From: Lad Prabhakar > > On the AX45MP core, cache coherency is a specification option so it may > not be supported. In this case DMA will fail. As a workaround, firstly we > allocate a global dma coherent pool from which DMA allocations are taken > and marked as non-cacheable + bufferable using the PMA region as specified > in the device tree. Synchronization callbacks are implemented to > synchronize when doing DMA transactions. > > The Andes AX45MP core has a Programmable Physical Memory Attributes (PMA) > block that allows dynamic adjustment of memory attributes in the runtime. > It contains a configurable amount of PMA entries implemented as CSR > registers to control the attributes of memory locations in interest. > > Below are the memory attributes supported: > * Device, Non-bufferable > * Device, bufferable > * Memory, Non-cacheable, Non-bufferable > * Memory, Non-cacheable, Bufferable > * Memory, Write-back, No-allocate > * Memory, Write-back, Read-allocate > * Memory, Write-back, Write-allocate > * Memory, Write-back, Read and Write-allocate > > This patch adds support to configure the memory attributes of the memory > regions as passed from the l2 cache node and exposes the cache management > ops. > > More info about PMA (section 10.3): > Link: http://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf > > Signed-off-by: Lad Prabhakar > --- > RFC v3 -> v4 > * Made use of runtime patching instead of compile time > * Now just exposing single function ax45mp_no_iocp_cmo() for CMO handling > * Added a check to make sure cache line size is always 64 bytes > * Renamed folder rzf -> rzfive > * Improved Kconfig description > * Dropped L2 cache configuration > * Dropped unnecessary casts > * Fixed comments pointed by Geert, apart from use of PTR_ALIGN_XYZ() macros. > --- > arch/riscv/include/asm/cacheflush.h | 8 + > arch/riscv/include/asm/errata_list.h | 32 +- > drivers/soc/renesas/Kconfig | 7 + > drivers/soc/renesas/Makefile | 2 + > drivers/soc/renesas/rzfive/Kconfig | 6 + > drivers/soc/renesas/rzfive/Makefile | 3 + > drivers/soc/renesas/rzfive/ax45mp_cache.c | 415 ++++++++++++++++++++++ > drivers/soc/renesas/rzfive/ax45mp_sbi.h | 29 ++ > 8 files changed, 496 insertions(+), 6 deletions(-) > create mode 100644 drivers/soc/renesas/rzfive/Kconfig > create mode 100644 drivers/soc/renesas/rzfive/Makefile > create mode 100644 drivers/soc/renesas/rzfive/ax45mp_cache.c > create mode 100644 drivers/soc/renesas/rzfive/ax45mp_sbi.h > > diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h > index 4a04d1be7c67..3226f3aceafe 100644 > --- a/arch/riscv/include/asm/cacheflush.h > +++ b/arch/riscv/include/asm/cacheflush.h > @@ -61,6 +61,14 @@ static inline void riscv_noncoherent_supported(void) {} > #define SYS_RISCV_FLUSH_ICACHE_LOCAL 1UL > #define SYS_RISCV_FLUSH_ICACHE_ALL (SYS_RISCV_FLUSH_ICACHE_LOCAL) > > +#ifdef CONFIG_AX45MP_L2_CACHE > +extern asmlinkage void ax45mp_no_iocp_cmo(unsigned int cache_size, void *vaddr, > + size_t size, int dir, int ops); > +#else > +inline void ax45mp_no_iocp_cmo(unsigned int cache_size, void *vaddr, > + size_t size, int dir, int ops) {} > +#endif > + > #include > > #endif /* _ASM_RISCV_CACHEFLUSH_H */ > diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h > index 48e899a8e7a9..300fed3bfd80 100644 > --- a/arch/riscv/include/asm/errata_list.h > +++ b/arch/riscv/include/asm/errata_list.h > @@ -125,8 +125,8 @@ asm volatile(ALTERNATIVE( \ > #define THEAD_SYNC_S ".long 0x0190000b" > > #define ALT_CMO_OP(_op, _start, _size, _cachesize, _dir, _ops) \ > -asm volatile(ALTERNATIVE_2( \ > - __nops(6), \ > +asm volatile(ALTERNATIVE_3( \ > + __nops(14), \ > "mv a0, %1\n\t" \ > "j 2f\n\t" \ > "3:\n\t" \ > @@ -134,7 +134,7 @@ asm volatile(ALTERNATIVE_2( \ > "add a0, a0, %0\n\t" \ > "2:\n\t" \ > "bltu a0, %2, 3b\n\t" \ > - "nop", 0, CPUFEATURE_ZICBOM, CONFIG_RISCV_ISA_ZICBOM, \ > + __nops(8), 0, CPUFEATURE_ZICBOM, CONFIG_RISCV_ISA_ZICBOM, \ > "mv a0, %1\n\t" \ > "j 2f\n\t" \ > "3:\n\t" \ > @@ -142,8 +142,28 @@ asm volatile(ALTERNATIVE_2( \ > "add a0, a0, %0\n\t" \ > "2:\n\t" \ > "bltu a0, %2, 3b\n\t" \ > - THEAD_SYNC_S, THEAD_VENDOR_ID, \ > - ERRATA_THEAD_CMO, CONFIG_ERRATA_THEAD_CMO) \ > + THEAD_SYNC_S "\n\t" \ > + __nops(8), THEAD_VENDOR_ID, \ > + ERRATA_THEAD_CMO, CONFIG_ERRATA_THEAD_CMO, \ > + ".option push\n\t\n\t" \ > + ".option norvc\n\t" \ > + ".option norelax\n\t"> \ alternatives already do the norvc + norelax options anyway for old and new instructions, so the .option stuff shouldn't be necessary I guess? > + "addi sp,sp,-16\n\t" \ > + "sd s0,0(sp)\n\t" \ > + "sd ra,8(sp)\n\t" \ > + "addi s0,sp,16\n\t" \ > + "mv a4,%6\n\t" \ > + "mv a3,%5\n\t" \ > + "mv a2,%4\n\t" \ > + "mv a1,%3\n\t" \ > + "mv a0,%0\n\t" \ > + "call ax45mp_no_iocp_cmo\n\t" \ > + "ld ra,8(sp)\n\t" \ > + "ld s0,0(sp)\n\t" \ > + "addi sp,sp,16\n\t" \ > + ".option pop\n\t", \ > + ANDESTECH_VENDOR_ID, ERRATA_ANDESTECH_NO_IOCP, \ > + CONFIG_ERRATA_ANDES_CMO) \ > : : "r"(_cachesize), \ > "r"((unsigned long)(_start) & ~((_cachesize) - 1UL)), \ > "r"((unsigned long)(_start) + (_size)), \ > @@ -151,7 +171,7 @@ asm volatile(ALTERNATIVE_2( \ > "r"((unsigned long)(_size)), \ > "r"((unsigned long)(_dir)), \ > "r"((unsigned long)(_ops)) \ > - : "a0") > + : "a0", "a1", "a2", "a3", "a4", "memory") > > #define THEAD_C9XX_RV_IRQ_PMU 17 > #define THEAD_C9XX_CSR_SCOUNTEROF 0x5c5 [...] > +static int ax45mp_configure_l2_cache(struct device_node *np) > +{ > + int ret; > + > + ret = of_property_read_u32(np, "cache-line-size", &ax45mp_priv->ax45mp_cache_line_size); > + if (ret) { > + pr_err("Failed to get cache-line-size defaulting to 64 bytes\n"); > + ax45mp_priv->ax45mp_cache_line_size = SZ_64; > + } > + > + if (ax45mp_priv->ax45mp_cache_line_size != SZ_64) { > + pr_err("Expected cache-line-size to 64 bytes (found:%u). Defaulting to 64 bytes\n", > + ax45mp_priv->ax45mp_cache_line_size); > + ax45mp_priv->ax45mp_cache_line_size = SZ_64; > + } > + > + ax45mp_priv->ucctl_ok = ax45mp_cpu_cache_controlable(); > + ax45mp_priv->l2cache_enabled = ax45mp_cpu_l2c_ctl_status() & AX45MP_L2_CACHE_CTL_CEN_MASK; > + > + return 0; > +} > + > +static int ax45mp_l2c_probe(struct platform_device *pdev) > +{ > + struct device_node *np = pdev->dev.of_node; > + int ret; > + > + ax45mp_priv = devm_kzalloc(&pdev->dev, sizeof(*ax45mp_priv), GFP_KERNEL); > + if (!ax45mp_priv) > + return -ENOMEM; > + > + ax45mp_priv->l2c_base = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL); > + if (!ax45mp_priv->l2c_base) { > + ret = -ENOMEM; > + goto l2c_err; > + } > + > + ret = ax45mp_configure_l2_cache(np); > + if (ret) > + goto l2c_err; > + > + ret = ax45mp_configure_pma_regions(np); > + if (ret) > + goto l2c_err; > + > + static_branch_disable(&ax45mp_l2c_configured); > + > + return 0; > + > +l2c_err: > + devm_kfree(&pdev->dev, ax45mp_priv); > + ax45mp_priv = NULL; > + return ret; > +} > + > +static const struct of_device_id ax45mp_cache_ids[] = { > + { .compatible = "andestech,ax45mp-cache" }, > + { /* sentinel */ } > +}; > + > +static struct platform_driver ax45mp_l2c_driver = { > + .driver = { > + .name = "ax45mp-l2c", > + .of_match_table = ax45mp_cache_ids, > + }, > + .probe = ax45mp_l2c_probe, > +}; > + > +static int __init ax45mp_cache_init(void) > +{ > + static_branch_enable(&ax45mp_l2c_configured); > + return platform_driver_register(&ax45mp_l2c_driver); the ordering is racy I think. I.e. in the function called from the cmo operations (ax45mp*_range) you need to access ax45mp_priv and its line-size element. But when you enable the static branch the driver is not yet registered but even more important, also not probed yet. So I guess the static-branch-enable should be living at the end of ax45mp_l2c_probe() Heiko From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5BB6EC433FE for ; Thu, 24 Nov 2022 18:30:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=EzzKH/qdeM1H7yVYsAVx/KwGG6P7y9bm0/FWwLi3qj8=; b=aBs+Xsc0unUvhQ 6LjU64JBuCHv5K11o+/wc3UW9kqmNn2O8LvqwcBAeKVGB7whEhRUgn6N38PTqO5oHQf/P4yOaucQ8 y3Ff3Z0U1WBaYrL3scB0CLT+P9uhyD6k4tW80zMZlhvhrtG4M1Wn3yjutdW6EWRJnUagBoT4FCRON alzslN76raVXmXVjmS/WaEgh5+5ybUx1uZqOYtgiFQ/35004Rd+bpH88AFJ8cVfOzYsfEZ7IJQAHP 1lEP7AauEWcK+HQn4IauOCGyChrjpkGG/H11fJ4s37wSXE4m9wCwXHgMgEJXl24zP1HjR9mrIgDFa CFO10n9n1vIrHFXfnjTQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oyGzU-00AuyN-D9; Thu, 24 Nov 2022 18:30:28 +0000 Received: from gloria.sntech.de ([185.11.138.130]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oyGzQ-00Auva-Hg for linux-riscv@lists.infradead.org; Thu, 24 Nov 2022 18:30:26 +0000 Received: from ip5b412258.dynamic.kabel-deutschland.de ([91.65.34.88] helo=diego.localnet) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1oyGzE-0007Jc-Tu; Thu, 24 Nov 2022 19:30:12 +0100 From: Heiko =?ISO-8859-1?Q?St=FCbner?= To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Guo Ren , Prabhakar Cc: Jisheng Zhang , Atish Patra , Anup Patel , Andrew Jones , Nathan Chancellor , Philipp Tomsich , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar Subject: Re: [PATCH v4 7/7] soc: renesas: Add L2 cache management for RZ/Five SoC Date: Thu, 24 Nov 2022 19:30:11 +0100 Message-ID: <5382916.ejJDZkT8p0@diego> In-Reply-To: <20221124172207.153718-8-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20221124172207.153718-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20221124172207.153718-8-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221124_103024_771919_AF69BFD7 X-CRM114-Status: GOOD ( 42.27 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Am Donnerstag, 24. November 2022, 18:22:07 CET schrieb Prabhakar: > From: Lad Prabhakar > > On the AX45MP core, cache coherency is a specification option so it may > not be supported. In this case DMA will fail. As a workaround, firstly we > allocate a global dma coherent pool from which DMA allocations are taken > and marked as non-cacheable + bufferable using the PMA region as specified > in the device tree. Synchronization callbacks are implemented to > synchronize when doing DMA transactions. > > The Andes AX45MP core has a Programmable Physical Memory Attributes (PMA) > block that allows dynamic adjustment of memory attributes in the runtime. > It contains a configurable amount of PMA entries implemented as CSR > registers to control the attributes of memory locations in interest. > > Below are the memory attributes supported: > * Device, Non-bufferable > * Device, bufferable > * Memory, Non-cacheable, Non-bufferable > * Memory, Non-cacheable, Bufferable > * Memory, Write-back, No-allocate > * Memory, Write-back, Read-allocate > * Memory, Write-back, Write-allocate > * Memory, Write-back, Read and Write-allocate > > This patch adds support to configure the memory attributes of the memory > regions as passed from the l2 cache node and exposes the cache management > ops. > > More info about PMA (section 10.3): > Link: http://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf > > Signed-off-by: Lad Prabhakar > --- > RFC v3 -> v4 > * Made use of runtime patching instead of compile time > * Now just exposing single function ax45mp_no_iocp_cmo() for CMO handling > * Added a check to make sure cache line size is always 64 bytes > * Renamed folder rzf -> rzfive > * Improved Kconfig description > * Dropped L2 cache configuration > * Dropped unnecessary casts > * Fixed comments pointed by Geert, apart from use of PTR_ALIGN_XYZ() macros. > --- > arch/riscv/include/asm/cacheflush.h | 8 + > arch/riscv/include/asm/errata_list.h | 32 +- > drivers/soc/renesas/Kconfig | 7 + > drivers/soc/renesas/Makefile | 2 + > drivers/soc/renesas/rzfive/Kconfig | 6 + > drivers/soc/renesas/rzfive/Makefile | 3 + > drivers/soc/renesas/rzfive/ax45mp_cache.c | 415 ++++++++++++++++++++++ > drivers/soc/renesas/rzfive/ax45mp_sbi.h | 29 ++ > 8 files changed, 496 insertions(+), 6 deletions(-) > create mode 100644 drivers/soc/renesas/rzfive/Kconfig > create mode 100644 drivers/soc/renesas/rzfive/Makefile > create mode 100644 drivers/soc/renesas/rzfive/ax45mp_cache.c > create mode 100644 drivers/soc/renesas/rzfive/ax45mp_sbi.h > > diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h > index 4a04d1be7c67..3226f3aceafe 100644 > --- a/arch/riscv/include/asm/cacheflush.h > +++ b/arch/riscv/include/asm/cacheflush.h > @@ -61,6 +61,14 @@ static inline void riscv_noncoherent_supported(void) {} > #define SYS_RISCV_FLUSH_ICACHE_LOCAL 1UL > #define SYS_RISCV_FLUSH_ICACHE_ALL (SYS_RISCV_FLUSH_ICACHE_LOCAL) > > +#ifdef CONFIG_AX45MP_L2_CACHE > +extern asmlinkage void ax45mp_no_iocp_cmo(unsigned int cache_size, void *vaddr, > + size_t size, int dir, int ops); > +#else > +inline void ax45mp_no_iocp_cmo(unsigned int cache_size, void *vaddr, > + size_t size, int dir, int ops) {} > +#endif > + > #include > > #endif /* _ASM_RISCV_CACHEFLUSH_H */ > diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h > index 48e899a8e7a9..300fed3bfd80 100644 > --- a/arch/riscv/include/asm/errata_list.h > +++ b/arch/riscv/include/asm/errata_list.h > @@ -125,8 +125,8 @@ asm volatile(ALTERNATIVE( \ > #define THEAD_SYNC_S ".long 0x0190000b" > > #define ALT_CMO_OP(_op, _start, _size, _cachesize, _dir, _ops) \ > -asm volatile(ALTERNATIVE_2( \ > - __nops(6), \ > +asm volatile(ALTERNATIVE_3( \ > + __nops(14), \ > "mv a0, %1\n\t" \ > "j 2f\n\t" \ > "3:\n\t" \ > @@ -134,7 +134,7 @@ asm volatile(ALTERNATIVE_2( \ > "add a0, a0, %0\n\t" \ > "2:\n\t" \ > "bltu a0, %2, 3b\n\t" \ > - "nop", 0, CPUFEATURE_ZICBOM, CONFIG_RISCV_ISA_ZICBOM, \ > + __nops(8), 0, CPUFEATURE_ZICBOM, CONFIG_RISCV_ISA_ZICBOM, \ > "mv a0, %1\n\t" \ > "j 2f\n\t" \ > "3:\n\t" \ > @@ -142,8 +142,28 @@ asm volatile(ALTERNATIVE_2( \ > "add a0, a0, %0\n\t" \ > "2:\n\t" \ > "bltu a0, %2, 3b\n\t" \ > - THEAD_SYNC_S, THEAD_VENDOR_ID, \ > - ERRATA_THEAD_CMO, CONFIG_ERRATA_THEAD_CMO) \ > + THEAD_SYNC_S "\n\t" \ > + __nops(8), THEAD_VENDOR_ID, \ > + ERRATA_THEAD_CMO, CONFIG_ERRATA_THEAD_CMO, \ > + ".option push\n\t\n\t" \ > + ".option norvc\n\t" \ > + ".option norelax\n\t"> \ alternatives already do the norvc + norelax options anyway for old and new instructions, so the .option stuff shouldn't be necessary I guess? > + "addi sp,sp,-16\n\t" \ > + "sd s0,0(sp)\n\t" \ > + "sd ra,8(sp)\n\t" \ > + "addi s0,sp,16\n\t" \ > + "mv a4,%6\n\t" \ > + "mv a3,%5\n\t" \ > + "mv a2,%4\n\t" \ > + "mv a1,%3\n\t" \ > + "mv a0,%0\n\t" \ > + "call ax45mp_no_iocp_cmo\n\t" \ > + "ld ra,8(sp)\n\t" \ > + "ld s0,0(sp)\n\t" \ > + "addi sp,sp,16\n\t" \ > + ".option pop\n\t", \ > + ANDESTECH_VENDOR_ID, ERRATA_ANDESTECH_NO_IOCP, \ > + CONFIG_ERRATA_ANDES_CMO) \ > : : "r"(_cachesize), \ > "r"((unsigned long)(_start) & ~((_cachesize) - 1UL)), \ > "r"((unsigned long)(_start) + (_size)), \ > @@ -151,7 +171,7 @@ asm volatile(ALTERNATIVE_2( \ > "r"((unsigned long)(_size)), \ > "r"((unsigned long)(_dir)), \ > "r"((unsigned long)(_ops)) \ > - : "a0") > + : "a0", "a1", "a2", "a3", "a4", "memory") > > #define THEAD_C9XX_RV_IRQ_PMU 17 > #define THEAD_C9XX_CSR_SCOUNTEROF 0x5c5 [...] > +static int ax45mp_configure_l2_cache(struct device_node *np) > +{ > + int ret; > + > + ret = of_property_read_u32(np, "cache-line-size", &ax45mp_priv->ax45mp_cache_line_size); > + if (ret) { > + pr_err("Failed to get cache-line-size defaulting to 64 bytes\n"); > + ax45mp_priv->ax45mp_cache_line_size = SZ_64; > + } > + > + if (ax45mp_priv->ax45mp_cache_line_size != SZ_64) { > + pr_err("Expected cache-line-size to 64 bytes (found:%u). Defaulting to 64 bytes\n", > + ax45mp_priv->ax45mp_cache_line_size); > + ax45mp_priv->ax45mp_cache_line_size = SZ_64; > + } > + > + ax45mp_priv->ucctl_ok = ax45mp_cpu_cache_controlable(); > + ax45mp_priv->l2cache_enabled = ax45mp_cpu_l2c_ctl_status() & AX45MP_L2_CACHE_CTL_CEN_MASK; > + > + return 0; > +} > + > +static int ax45mp_l2c_probe(struct platform_device *pdev) > +{ > + struct device_node *np = pdev->dev.of_node; > + int ret; > + > + ax45mp_priv = devm_kzalloc(&pdev->dev, sizeof(*ax45mp_priv), GFP_KERNEL); > + if (!ax45mp_priv) > + return -ENOMEM; > + > + ax45mp_priv->l2c_base = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL); > + if (!ax45mp_priv->l2c_base) { > + ret = -ENOMEM; > + goto l2c_err; > + } > + > + ret = ax45mp_configure_l2_cache(np); > + if (ret) > + goto l2c_err; > + > + ret = ax45mp_configure_pma_regions(np); > + if (ret) > + goto l2c_err; > + > + static_branch_disable(&ax45mp_l2c_configured); > + > + return 0; > + > +l2c_err: > + devm_kfree(&pdev->dev, ax45mp_priv); > + ax45mp_priv = NULL; > + return ret; > +} > + > +static const struct of_device_id ax45mp_cache_ids[] = { > + { .compatible = "andestech,ax45mp-cache" }, > + { /* sentinel */ } > +}; > + > +static struct platform_driver ax45mp_l2c_driver = { > + .driver = { > + .name = "ax45mp-l2c", > + .of_match_table = ax45mp_cache_ids, > + }, > + .probe = ax45mp_l2c_probe, > +}; > + > +static int __init ax45mp_cache_init(void) > +{ > + static_branch_enable(&ax45mp_l2c_configured); > + return platform_driver_register(&ax45mp_l2c_driver); the ordering is racy I think. I.e. in the function called from the cmo operations (ax45mp*_range) you need to access ax45mp_priv and its line-size element. But when you enable the static branch the driver is not yet registered but even more important, also not probed yet. So I guess the static-branch-enable should be living at the end of ax45mp_l2c_probe() Heiko _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv