* [PATCH 0/2] Renesas R8A77980 CPG/MSSR clock support
@ 2018-01-31 20:23 ` Sergei Shtylyov
0 siblings, 0 replies; 36+ messages in thread
From: Sergei Shtylyov @ 2018-01-31 20:23 UTC (permalink / raw)
To: Rob Herring, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA, Michael Turquette,
Stephen Boyd, Geert Uytterhoeven, linux-clk
Cc: Mark Rutland
Hello!
Here's the set of 2 patches against the 'clk-renesas' branch of Geert Uytterhoeven's
'renesas-drivers.git' repo.
[1/2] dt-bindings: clock: add R8A77980 CPG core clock definitions
[2/2] clk: renesas: cpg-mssr: add R8A77980 support
MBR, Sergei
--
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^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 0/2] Renesas R8A77980 CPG/MSSR clock support
@ 2018-01-31 20:23 ` Sergei Shtylyov
0 siblings, 0 replies; 36+ messages in thread
From: Sergei Shtylyov @ 2018-01-31 20:23 UTC (permalink / raw)
To: Rob Herring, devicetree, linux-renesas-soc, Michael Turquette,
Stephen Boyd, Geert Uytterhoeven, linux-clk
Cc: Mark Rutland
Hello!
Here's the set of 2 patches against the 'clk-renesas' branch of Geert Uytterhoeven's
'renesas-drivers.git' repo.
[1/2] dt-bindings: clock: add R8A77980 CPG core clock definitions
[2/2] clk: renesas: cpg-mssr: add R8A77980 support
MBR, Sergei
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 1/2] dt-bindings: clock: add R8A77980 CPG core clock definitions
2018-01-31 20:23 ` Sergei Shtylyov
@ 2018-01-31 20:27 ` Sergei Shtylyov
-1 siblings, 0 replies; 36+ messages in thread
From: Sergei Shtylyov @ 2018-01-31 20:27 UTC (permalink / raw)
To: Rob Herring, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA
Cc: Mark Rutland
Add macros usable by the device tree sources to reference the R8A77980
CPG core clocks by index. The data come from the table 8.2e of the R-Car
Series, 3rd Generation User's Manual: Hardware (Rev. 0.80, Oct, 2017),
however I had to add the Z2 clock which is somehow present only on the
figure 8.1e...
Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>
---
include/dt-bindings/clock/r8a77980-cpg-mssr.h | 51 ++++++++++++++++++++++++++
1 file changed, 51 insertions(+)
Index: renesas-drivers/include/dt-bindings/clock/r8a77980-cpg-mssr.h
===================================================================
--- /dev/null
+++ renesas-drivers/include/dt-bindings/clock/r8a77980-cpg-mssr.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ * Copyright (C) 2018 Cogent Embedded, Inc.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a77980 CPG Core Clocks */
+#define R8A77980_CLK_Z2 0
+#define R8A77980_CLK_ZR 1
+#define R8A77980_CLK_ZTR 2
+#define R8A77980_CLK_ZTRD2 3
+#define R8A77980_CLK_ZT 4
+#define R8A77980_CLK_ZX 5
+#define R8A77980_CLK_S0D1 6
+#define R8A77980_CLK_S0D2 7
+#define R8A77980_CLK_S0D3 8
+#define R8A77980_CLK_S0D4 9
+#define R8A77980_CLK_S0D6 10
+#define R8A77980_CLK_S0D12 11
+#define R8A77980_CLK_S0D24 12
+#define R8A77980_CLK_S1D1 13
+#define R8A77980_CLK_S1D2 14
+#define R8A77980_CLK_S1D4 15
+#define R8A77980_CLK_S2D1 16
+#define R8A77980_CLK_S2D2 17
+#define R8A77980_CLK_S2D4 18
+#define R8A77980_CLK_S3D1 19
+#define R8A77980_CLK_S3D2 20
+#define R8A77980_CLK_S3D4 21
+#define R8A77980_CLK_LB 22
+#define R8A77980_CLK_CL 23
+#define R8A77980_CLK_ZB3 24
+#define R8A77980_CLK_ZB3D2 25
+#define R8A77980_CLK_ZB3D4 26
+#define R8A77980_CLK_SD0H 27
+#define R8A77980_CLK_SD0 28
+#define R8A77980_CLK_RPC 29
+#define R8A77980_CLK_RPCD2 30
+#define R8A77980_CLK_MSO 31
+#define R8A77980_CLK_CANFD 32
+#define R8A77980_CLK_CSI0 33
+#define R8A77980_CLK_CP 34
+#define R8A77980_CLK_CPEX 35
+#define R8A77980_CLK_R 36
+#define R8A77980_CLK_OSC 37
+
+#endif /* __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__ */
--
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^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 1/2] dt-bindings: clock: add R8A77980 CPG core clock definitions
@ 2018-01-31 20:27 ` Sergei Shtylyov
0 siblings, 0 replies; 36+ messages in thread
From: Sergei Shtylyov @ 2018-01-31 20:27 UTC (permalink / raw)
To: Rob Herring, devicetree, linux-renesas-soc; +Cc: Mark Rutland
Add macros usable by the device tree sources to reference the R8A77980
CPG core clocks by index. The data come from the table 8.2e of the R-Car
Series, 3rd Generation User's Manual: Hardware (Rev. 0.80, Oct, 2017),
however I had to add the Z2 clock which is somehow present only on the
figure 8.1e...
Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
include/dt-bindings/clock/r8a77980-cpg-mssr.h | 51 ++++++++++++++++++++++++++
1 file changed, 51 insertions(+)
Index: renesas-drivers/include/dt-bindings/clock/r8a77980-cpg-mssr.h
===================================================================
--- /dev/null
+++ renesas-drivers/include/dt-bindings/clock/r8a77980-cpg-mssr.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ * Copyright (C) 2018 Cogent Embedded, Inc.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a77980 CPG Core Clocks */
+#define R8A77980_CLK_Z2 0
+#define R8A77980_CLK_ZR 1
+#define R8A77980_CLK_ZTR 2
+#define R8A77980_CLK_ZTRD2 3
+#define R8A77980_CLK_ZT 4
+#define R8A77980_CLK_ZX 5
+#define R8A77980_CLK_S0D1 6
+#define R8A77980_CLK_S0D2 7
+#define R8A77980_CLK_S0D3 8
+#define R8A77980_CLK_S0D4 9
+#define R8A77980_CLK_S0D6 10
+#define R8A77980_CLK_S0D12 11
+#define R8A77980_CLK_S0D24 12
+#define R8A77980_CLK_S1D1 13
+#define R8A77980_CLK_S1D2 14
+#define R8A77980_CLK_S1D4 15
+#define R8A77980_CLK_S2D1 16
+#define R8A77980_CLK_S2D2 17
+#define R8A77980_CLK_S2D4 18
+#define R8A77980_CLK_S3D1 19
+#define R8A77980_CLK_S3D2 20
+#define R8A77980_CLK_S3D4 21
+#define R8A77980_CLK_LB 22
+#define R8A77980_CLK_CL 23
+#define R8A77980_CLK_ZB3 24
+#define R8A77980_CLK_ZB3D2 25
+#define R8A77980_CLK_ZB3D4 26
+#define R8A77980_CLK_SD0H 27
+#define R8A77980_CLK_SD0 28
+#define R8A77980_CLK_RPC 29
+#define R8A77980_CLK_RPCD2 30
+#define R8A77980_CLK_MSO 31
+#define R8A77980_CLK_CANFD 32
+#define R8A77980_CLK_CSI0 33
+#define R8A77980_CLK_CP 34
+#define R8A77980_CLK_CPEX 35
+#define R8A77980_CLK_R 36
+#define R8A77980_CLK_OSC 37
+
+#endif /* __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__ */
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 0/2] Renesas R8A77980 CPG/MSSR clock support
2018-01-31 20:23 ` Sergei Shtylyov
(?)
(?)
@ 2018-01-31 20:29 ` Sergei Shtylyov
-1 siblings, 0 replies; 36+ messages in thread
From: Sergei Shtylyov @ 2018-01-31 20:29 UTC (permalink / raw)
To: Rob Herring, devicetree, linux-renesas-soc, Michael Turquette,
Stephen Boyd, Geert Uytterhoeven, linux-clk
Cc: Mark Rutland
Add R-Car V3H (R8A77980) Clock Pulse Generator / Module Standby and
Software Reset support, using the CPG/MSSR driver core and the common
R-Car Gen3 code.
Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt | 5
drivers/clk/renesas/Kconfig | 5
drivers/clk/renesas/Makefile | 1
drivers/clk/renesas/r8a77980-cpg-mssr.c | 227 +++++++++++
drivers/clk/renesas/renesas-cpg-mssr.c | 6
drivers/clk/renesas/renesas-cpg-mssr.h | 1
6 files changed, 243 insertions(+), 2 deletions(-)
Index: renesas-drivers/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
===================================================================
--- renesas-drivers.orig/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
+++ renesas-drivers/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
@@ -23,6 +23,7 @@ Required Properties:
- "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3)
- "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W)
- "renesas,r8a77970-cpg-mssr" for the r8a77970 SoC (R-Car V3M)
+ - "renesas,r8a77980-cpg-mssr" for the r8a77980 SoC (R-Car V3H)
- "renesas,r8a77995-cpg-mssr" for the r8a77995 SoC (R-Car D3)
- reg: Base address and length of the memory resource used by the CPG/MSSR
@@ -32,8 +33,8 @@ Required Properties:
clock-names
- clock-names: List of external parent clock names. Valid names are:
- "extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7792, r8a7793, r8a7794,
- r8a7795, r8a7796, r8a77970, r8a77995)
- - "extalr" (r8a7795, r8a7796, r8a77970)
+ r8a7795, r8a7796, r8a77970, r8a77980, r8a77995)
+ - "extalr" (r8a7795, r8a7796, r8a77970, r8a77980)
- "usb_extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7793, r8a7794)
- #clock-cells: Must be 2
Index: renesas-drivers/drivers/clk/renesas/Kconfig
===================================================================
--- renesas-drivers.orig/drivers/clk/renesas/Kconfig
+++ renesas-drivers/drivers/clk/renesas/Kconfig
@@ -16,6 +16,7 @@ config CLK_RENESAS
select CLK_R8A7795 if ARCH_R8A7795
select CLK_R8A7796 if ARCH_R8A7796
select CLK_R8A77970 if ARCH_R8A77970
+ select CLK_R8A77980 if ARCH_R8A77980
select CLK_R8A77995 if ARCH_R8A77995
select CLK_SH73A0 if ARCH_SH73A0
@@ -101,6 +102,10 @@ config CLK_R8A77970
bool "R-Car V3M clock support" if COMPILE_TEST
select CLK_RCAR_GEN3_CPG
+config CLK_R8A77980
+ bool "R-Car V3H clock support" if COMPILE_TEST
+ select CLK_RCAR_GEN3_CPG
+
config CLK_R8A77995
bool "R-Car D3 clock support" if COMPILE_TEST
select CLK_RCAR_GEN3_CPG
Index: renesas-drivers/drivers/clk/renesas/Makefile
===================================================================
--- renesas-drivers.orig/drivers/clk/renesas/Makefile
+++ renesas-drivers/drivers/clk/renesas/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_CLK_R8A7794) += r8a7794-cp
obj-$(CONFIG_CLK_R8A7795) += r8a7795-cpg-mssr.o
obj-$(CONFIG_CLK_R8A7796) += r8a7796-cpg-mssr.o
obj-$(CONFIG_CLK_R8A77970) += r8a77970-cpg-mssr.o
+obj-$(CONFIG_CLK_R8A77980) += r8a77980-cpg-mssr.o
obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o
obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o
Index: renesas-drivers/drivers/clk/renesas/r8a77980-cpg-mssr.c
===================================================================
--- /dev/null
+++ renesas-drivers/drivers/clk/renesas/r8a77980-cpg-mssr.c
@@ -0,0 +1,227 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * r8a77980 Clock Pulse Generator / Module Standby and Software Reset
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ * Copyright (C) 2018 Cogent Embedded, Inc.
+ *
+ * Based on r8a7795-cpg-mssr.c
+ *
+ * Copyright (C) 2016 Renesas Electronics Corp.
+ */
+
+#include <linux/device.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/soc/renesas/rcar-rst.h>
+#include <linux/sys_soc.h>
+
+#include <dt-bindings/clock/r8a77980-cpg-mssr.h>
+
+#include "renesas-cpg-mssr.h"
+#include "rcar-gen3-cpg.h"
+
+enum clk_ids {
+ /* Core Clock Outputs exported to DT */
+ LAST_DT_CORE_CLK = R8A77980_CLK_OSC,
+
+ /* External Input Clocks */
+ CLK_EXTAL,
+ CLK_EXTALR,
+
+ /* Internal Core Clocks */
+ CLK_MAIN,
+ CLK_PLL1,
+ CLK_PLL2,
+ CLK_PLL3,
+ CLK_PLL1_DIV2,
+ CLK_PLL1_DIV4,
+ CLK_S0,
+ CLK_S1,
+ CLK_S2,
+ CLK_S3,
+ CLK_SDSRC,
+
+ /* Module Clocks */
+ MOD_CLK_BASE
+};
+
+static const struct cpg_core_clk r8a77980_core_clks[] __initconst = {
+ /* External Clock Inputs */
+ DEF_INPUT("extal", CLK_EXTAL),
+ DEF_INPUT("extalr", CLK_EXTALR),
+
+ /* Internal Core Clocks */
+ DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
+ DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
+ DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
+ DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
+
+ DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
+ DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
+ DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
+ DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1),
+ DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
+ DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
+ DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
+
+ /* Core Clock Outputs */
+ DEF_FIXED("ztr", R8A77980_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
+ DEF_FIXED("ztrd2", R8A77980_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
+ DEF_FIXED("zt", R8A77980_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
+ DEF_FIXED("zx", R8A77980_CLK_ZX, CLK_PLL1_DIV2, 2, 1),
+ DEF_FIXED("s0d1", R8A77980_CLK_S0D1, CLK_S0, 1, 1),
+ DEF_FIXED("s0d2", R8A77980_CLK_S0D2, CLK_S0, 2, 1),
+ DEF_FIXED("s0d3", R8A77980_CLK_S0D3, CLK_S0, 3, 1),
+ DEF_FIXED("s0d4", R8A77980_CLK_S0D4, CLK_S0, 4, 1),
+ DEF_FIXED("s0d6", R8A77980_CLK_S0D6, CLK_S0, 6, 1),
+ DEF_FIXED("s0d12", R8A77980_CLK_S0D12, CLK_S0, 12, 1),
+ DEF_FIXED("s0d24", R8A77980_CLK_S0D24, CLK_S0, 24, 1),
+ DEF_FIXED("s1d1", R8A77980_CLK_S1D1, CLK_S1, 1, 1),
+ DEF_FIXED("s1d2", R8A77980_CLK_S1D2, CLK_S1, 2, 1),
+ DEF_FIXED("s1d4", R8A77980_CLK_S1D4, CLK_S1, 4, 1),
+ DEF_FIXED("s2d1", R8A77980_CLK_S2D1, CLK_S2, 1, 1),
+ DEF_FIXED("s2d2", R8A77980_CLK_S2D2, CLK_S2, 2, 1),
+ DEF_FIXED("s2d4", R8A77980_CLK_S2D4, CLK_S2, 4, 1),
+ DEF_FIXED("s3d1", R8A77980_CLK_S3D1, CLK_S3, 1, 1),
+ DEF_FIXED("s3d2", R8A77980_CLK_S3D2, CLK_S3, 2, 1),
+ DEF_FIXED("s3d4", R8A77980_CLK_S3D4, CLK_S3, 4, 1),
+
+ DEF_GEN3_SD("sd0", R8A77980_CLK_SD0, CLK_SDSRC, 0x0074),
+
+ DEF_FIXED("cl", R8A77980_CLK_CL, CLK_PLL1_DIV2, 48, 1),
+ DEF_FIXED("cp", R8A77980_CLK_CP, CLK_EXTAL, 2, 1),
+ DEF_FIXED("cpex", R8A77980_CLK_CPEX, CLK_EXTAL, 2, 1),
+
+ DEF_DIV6P1("canfd", R8A77980_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
+ DEF_DIV6P1("csi0", R8A77980_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
+ DEF_DIV6P1("mso", R8A77980_CLK_MSO, CLK_PLL1_DIV4, 0x014),
+};
+
+static const struct mssr_mod_clk r8a77980_mod_clks[] __initconst = {
+ DEF_MOD("tmu4", 121, R8A77980_CLK_S0D6),
+ DEF_MOD("tmu3", 122, R8A77980_CLK_S0D6),
+ DEF_MOD("tmu2", 123, R8A77980_CLK_S0D6),
+ DEF_MOD("tmu1", 124, R8A77980_CLK_S0D6),
+ DEF_MOD("tmu0", 125, R8A77980_CLK_CP),
+ DEF_MOD("scif4", 203, R8A77980_CLK_S3D4),
+ DEF_MOD("scif3", 204, R8A77980_CLK_S3D4),
+ DEF_MOD("scif1", 206, R8A77980_CLK_S3D4),
+ DEF_MOD("scif0", 207, R8A77980_CLK_S3D4),
+ DEF_MOD("msiof3", 208, R8A77980_CLK_MSO),
+ DEF_MOD("msiof2", 209, R8A77980_CLK_MSO),
+ DEF_MOD("msiof1", 210, R8A77980_CLK_MSO),
+ DEF_MOD("msiof0", 211, R8A77980_CLK_MSO),
+ DEF_MOD("sys-dmac2", 217, R8A77980_CLK_S0D3),
+ DEF_MOD("sys-dmac1", 218, R8A77980_CLK_S0D3),
+ DEF_MOD("tpu0", 304, R8A77980_CLK_S3D4),
+ DEF_MOD("sdif", 314, R8A77980_CLK_SD0), /* OK */
+ DEF_MOD("pciec0", 319, R8A77980_CLK_S3D1),
+ DEF_MOD("intc-ex", 407, R8A77980_CLK_CP), /* OK */
+ DEF_MOD("intc-ap", 408, R8A77980_CLK_S0D3),
+ DEF_MOD("hscif3", 517, R8A77980_CLK_S3D1),
+ DEF_MOD("hscif2", 518, R8A77980_CLK_S3D1),
+ DEF_MOD("hscif1", 519, R8A77980_CLK_S3D1),
+ DEF_MOD("hscif0", 520, R8A77980_CLK_S3D1),
+ DEF_MOD("imp4", 521, R8A77980_CLK_S1D1), /* OK? */
+ DEF_MOD("thermal", 522, R8A77980_CLK_CP),
+ DEF_MOD("pwm", 523, R8A77980_CLK_S0D12),
+ DEF_MOD("impdma1", 526, R8A77980_CLK_S1D1),
+ DEF_MOD("impdma0", 527, R8A77980_CLK_S1D1),
+ DEF_MOD("imp-ocv4", 528, R8A77980_CLK_S1D1),
+ DEF_MOD("imp-ocv3", 529, R8A77980_CLK_S1D1),
+ DEF_MOD("imp-ocv2", 531, R8A77980_CLK_S1D1),
+ DEF_MOD("fcpvd0", 603, R8A77980_CLK_S3D1),
+ DEF_MOD("vspd0", 623, R8A77980_CLK_S3D1),
+ DEF_MOD("csi41", 715, R8A77980_CLK_CSI0),
+ DEF_MOD("csi40", 716, R8A77980_CLK_CSI0),
+ DEF_MOD("du0", 724, R8A77980_CLK_S2D1),
+ DEF_MOD("lvds", 727, R8A77980_CLK_S2D1),
+ DEF_MOD("etheravb", 812, R8A77980_CLK_S3D2),
+ DEF_MOD("gether", 813, R8A77980_CLK_S3D2),
+ DEF_MOD("imp3", 824, R8A77980_CLK_S1D1),
+ DEF_MOD("imp2", 825, R8A77980_CLK_S1D1),
+ DEF_MOD("imp1", 826, R8A77980_CLK_S1D1),
+ DEF_MOD("imp0", 827, R8A77980_CLK_S1D1),
+ DEF_MOD("imp-ocv1", 828, R8A77980_CLK_S1D1),
+ DEF_MOD("imp-ocv0", 829, R8A77980_CLK_S1D1),
+ DEF_MOD("impram", 830, R8A77980_CLK_S1D1),
+ DEF_MOD("impcnn", 831, R8A77980_CLK_S1D1),
+ DEF_MOD("gpio5", 907, R8A77980_CLK_CP),
+ DEF_MOD("gpio4", 908, R8A77980_CLK_CP),
+ DEF_MOD("gpio3", 909, R8A77980_CLK_CP),
+ DEF_MOD("gpio2", 910, R8A77980_CLK_CP),
+ DEF_MOD("gpio1", 911, R8A77980_CLK_CP),
+ DEF_MOD("gpio0", 912, R8A77980_CLK_CP),
+ DEF_MOD("can-fd", 914, R8A77980_CLK_S3D2),
+ DEF_MOD("i2c4", 927, R8A77980_CLK_S0D6),
+ DEF_MOD("i2c3", 928, R8A77980_CLK_S0D6),
+ DEF_MOD("i2c2", 929, R8A77980_CLK_S3D2),
+ DEF_MOD("i2c1", 930, R8A77980_CLK_S3D2),
+ DEF_MOD("i2c0", 931, R8A77980_CLK_S3D2),
+};
+
+static const unsigned int r8a77980_crit_mod_clks[] __initconst = {
+ MOD_CLK_ID(408), /* INTC-AP (GIC) */
+};
+
+
+/*
+ * CPG Clock Data
+ */
+
+/*
+ * MD EXTAL PLL2 PLL1 PLL3
+ * 14 13 (MHz)
+ * --------------------------------------------------
+ * 0 0 16.66 x 1 x240 x192 x192
+ * 0 1 20 x 1 x200 x160 x160
+ * 1 0 27 x 1 x148 x118 x118
+ * 1 1 33.33 / 2 x240 x192 x192
+ */
+#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
+ (((md) & BIT(13)) >> 13))
+
+static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[4] __initconst = {
+ /* EXTAL div PLL1 mult/div PLL3 mult/div */
+ { 1, 192, 1, 192, 1, },
+ { 1, 160, 1, 160, 1, },
+ { 1, 118, 1, 118, 1, },
+ { 2, 192, 1, 192, 1, },
+};
+
+static int __init r8a77980_cpg_mssr_init(struct device *dev)
+{
+ const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
+ u32 cpg_mode;
+ int error;
+
+ error = rcar_rst_read_mode_pins(&cpg_mode);
+ if (error)
+ return error;
+
+ cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
+
+ return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
+}
+
+const struct cpg_mssr_info r8a77980_cpg_mssr_info __initconst = {
+ /* Core Clocks */
+ .core_clks = r8a77980_core_clks,
+ .num_core_clks = ARRAY_SIZE(r8a77980_core_clks),
+ .last_dt_core_clk = LAST_DT_CORE_CLK,
+ .num_total_core_clks = MOD_CLK_BASE,
+
+ /* Module Clocks */
+ .mod_clks = r8a77980_mod_clks,
+ .num_mod_clks = ARRAY_SIZE(r8a77980_mod_clks),
+ .num_hw_mod_clks = 12 * 32,
+
+ /* Critical Module Clocks */
+ .crit_mod_clks = r8a77980_crit_mod_clks,
+ .num_crit_mod_clks = ARRAY_SIZE(r8a77980_crit_mod_clks),
+
+ /* Callbacks */
+ .init = r8a77980_cpg_mssr_init,
+ .cpg_clk_register = rcar_gen3_cpg_clk_register,
+};
Index: renesas-drivers/drivers/clk/renesas/renesas-cpg-mssr.c
===================================================================
--- renesas-drivers.orig/drivers/clk/renesas/renesas-cpg-mssr.c
+++ renesas-drivers/drivers/clk/renesas/renesas-cpg-mssr.c
@@ -699,6 +699,12 @@ static const struct of_device_id cpg_mss
.data = &r8a77970_cpg_mssr_info,
},
#endif
+#ifdef CONFIG_ARCH_R8A77980
+ {
+ .compatible = "renesas,r8a77980-cpg-mssr",
+ .data = &r8a77980_cpg_mssr_info,
+ },
+#endif
#ifdef CONFIG_CLK_R8A77995
{
.compatible = "renesas,r8a77995-cpg-mssr",
Index: renesas-drivers/drivers/clk/renesas/renesas-cpg-mssr.h
===================================================================
--- renesas-drivers.orig/drivers/clk/renesas/renesas-cpg-mssr.h
+++ renesas-drivers/drivers/clk/renesas/renesas-cpg-mssr.h
@@ -140,6 +140,7 @@ extern const struct cpg_mssr_info r8a779
extern const struct cpg_mssr_info r8a7795_cpg_mssr_info;
extern const struct cpg_mssr_info r8a7796_cpg_mssr_info;
extern const struct cpg_mssr_info r8a77970_cpg_mssr_info;
+extern const struct cpg_mssr_info r8a77980_cpg_mssr_info;
extern const struct cpg_mssr_info r8a77995_cpg_mssr_info;
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 2/2] clk: renesas: cpg-mssr: add R8A77980 support
2018-01-31 20:23 ` Sergei Shtylyov
@ 2018-01-31 20:31 ` Sergei Shtylyov
-1 siblings, 0 replies; 36+ messages in thread
From: Sergei Shtylyov @ 2018-01-31 20:31 UTC (permalink / raw)
To: Rob Herring, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA, Michael Turquette,
Stephen Boyd, Geert Uytterhoeven, linux-clk
Cc: Mark Rutland
Add R-Car V3H (R8A77980) Clock Pulse Generator / Module Standby and
Software Reset support, using the CPG/MSSR driver core and the common
R-Car Gen3 code.
Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>
---
Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt | 5
drivers/clk/renesas/Kconfig | 5
drivers/clk/renesas/Makefile | 1
drivers/clk/renesas/r8a77980-cpg-mssr.c | 227 +++++++++++
drivers/clk/renesas/renesas-cpg-mssr.c | 6
drivers/clk/renesas/renesas-cpg-mssr.h | 1
6 files changed, 243 insertions(+), 2 deletions(-)
Index: renesas-drivers/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
===================================================================
--- renesas-drivers.orig/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
+++ renesas-drivers/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
@@ -23,6 +23,7 @@ Required Properties:
- "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3)
- "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W)
- "renesas,r8a77970-cpg-mssr" for the r8a77970 SoC (R-Car V3M)
+ - "renesas,r8a77980-cpg-mssr" for the r8a77980 SoC (R-Car V3H)
- "renesas,r8a77995-cpg-mssr" for the r8a77995 SoC (R-Car D3)
- reg: Base address and length of the memory resource used by the CPG/MSSR
@@ -32,8 +33,8 @@ Required Properties:
clock-names
- clock-names: List of external parent clock names. Valid names are:
- "extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7792, r8a7793, r8a7794,
- r8a7795, r8a7796, r8a77970, r8a77995)
- - "extalr" (r8a7795, r8a7796, r8a77970)
+ r8a7795, r8a7796, r8a77970, r8a77980, r8a77995)
+ - "extalr" (r8a7795, r8a7796, r8a77970, r8a77980)
- "usb_extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7793, r8a7794)
- #clock-cells: Must be 2
Index: renesas-drivers/drivers/clk/renesas/Kconfig
===================================================================
--- renesas-drivers.orig/drivers/clk/renesas/Kconfig
+++ renesas-drivers/drivers/clk/renesas/Kconfig
@@ -16,6 +16,7 @@ config CLK_RENESAS
select CLK_R8A7795 if ARCH_R8A7795
select CLK_R8A7796 if ARCH_R8A7796
select CLK_R8A77970 if ARCH_R8A77970
+ select CLK_R8A77980 if ARCH_R8A77980
select CLK_R8A77995 if ARCH_R8A77995
select CLK_SH73A0 if ARCH_SH73A0
@@ -101,6 +102,10 @@ config CLK_R8A77970
bool "R-Car V3M clock support" if COMPILE_TEST
select CLK_RCAR_GEN3_CPG
+config CLK_R8A77980
+ bool "R-Car V3H clock support" if COMPILE_TEST
+ select CLK_RCAR_GEN3_CPG
+
config CLK_R8A77995
bool "R-Car D3 clock support" if COMPILE_TEST
select CLK_RCAR_GEN3_CPG
Index: renesas-drivers/drivers/clk/renesas/Makefile
===================================================================
--- renesas-drivers.orig/drivers/clk/renesas/Makefile
+++ renesas-drivers/drivers/clk/renesas/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_CLK_R8A7794) += r8a7794-cp
obj-$(CONFIG_CLK_R8A7795) += r8a7795-cpg-mssr.o
obj-$(CONFIG_CLK_R8A7796) += r8a7796-cpg-mssr.o
obj-$(CONFIG_CLK_R8A77970) += r8a77970-cpg-mssr.o
+obj-$(CONFIG_CLK_R8A77980) += r8a77980-cpg-mssr.o
obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o
obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o
Index: renesas-drivers/drivers/clk/renesas/r8a77980-cpg-mssr.c
===================================================================
--- /dev/null
+++ renesas-drivers/drivers/clk/renesas/r8a77980-cpg-mssr.c
@@ -0,0 +1,227 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * r8a77980 Clock Pulse Generator / Module Standby and Software Reset
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ * Copyright (C) 2018 Cogent Embedded, Inc.
+ *
+ * Based on r8a7795-cpg-mssr.c
+ *
+ * Copyright (C) 2016 Renesas Electronics Corp.
+ */
+
+#include <linux/device.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/soc/renesas/rcar-rst.h>
+#include <linux/sys_soc.h>
+
+#include <dt-bindings/clock/r8a77980-cpg-mssr.h>
+
+#include "renesas-cpg-mssr.h"
+#include "rcar-gen3-cpg.h"
+
+enum clk_ids {
+ /* Core Clock Outputs exported to DT */
+ LAST_DT_CORE_CLK = R8A77980_CLK_OSC,
+
+ /* External Input Clocks */
+ CLK_EXTAL,
+ CLK_EXTALR,
+
+ /* Internal Core Clocks */
+ CLK_MAIN,
+ CLK_PLL1,
+ CLK_PLL2,
+ CLK_PLL3,
+ CLK_PLL1_DIV2,
+ CLK_PLL1_DIV4,
+ CLK_S0,
+ CLK_S1,
+ CLK_S2,
+ CLK_S3,
+ CLK_SDSRC,
+
+ /* Module Clocks */
+ MOD_CLK_BASE
+};
+
+static const struct cpg_core_clk r8a77980_core_clks[] __initconst = {
+ /* External Clock Inputs */
+ DEF_INPUT("extal", CLK_EXTAL),
+ DEF_INPUT("extalr", CLK_EXTALR),
+
+ /* Internal Core Clocks */
+ DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
+ DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
+ DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
+ DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
+
+ DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
+ DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
+ DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
+ DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1),
+ DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
+ DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
+ DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
+
+ /* Core Clock Outputs */
+ DEF_FIXED("ztr", R8A77980_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
+ DEF_FIXED("ztrd2", R8A77980_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
+ DEF_FIXED("zt", R8A77980_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
+ DEF_FIXED("zx", R8A77980_CLK_ZX, CLK_PLL1_DIV2, 2, 1),
+ DEF_FIXED("s0d1", R8A77980_CLK_S0D1, CLK_S0, 1, 1),
+ DEF_FIXED("s0d2", R8A77980_CLK_S0D2, CLK_S0, 2, 1),
+ DEF_FIXED("s0d3", R8A77980_CLK_S0D3, CLK_S0, 3, 1),
+ DEF_FIXED("s0d4", R8A77980_CLK_S0D4, CLK_S0, 4, 1),
+ DEF_FIXED("s0d6", R8A77980_CLK_S0D6, CLK_S0, 6, 1),
+ DEF_FIXED("s0d12", R8A77980_CLK_S0D12, CLK_S0, 12, 1),
+ DEF_FIXED("s0d24", R8A77980_CLK_S0D24, CLK_S0, 24, 1),
+ DEF_FIXED("s1d1", R8A77980_CLK_S1D1, CLK_S1, 1, 1),
+ DEF_FIXED("s1d2", R8A77980_CLK_S1D2, CLK_S1, 2, 1),
+ DEF_FIXED("s1d4", R8A77980_CLK_S1D4, CLK_S1, 4, 1),
+ DEF_FIXED("s2d1", R8A77980_CLK_S2D1, CLK_S2, 1, 1),
+ DEF_FIXED("s2d2", R8A77980_CLK_S2D2, CLK_S2, 2, 1),
+ DEF_FIXED("s2d4", R8A77980_CLK_S2D4, CLK_S2, 4, 1),
+ DEF_FIXED("s3d1", R8A77980_CLK_S3D1, CLK_S3, 1, 1),
+ DEF_FIXED("s3d2", R8A77980_CLK_S3D2, CLK_S3, 2, 1),
+ DEF_FIXED("s3d4", R8A77980_CLK_S3D4, CLK_S3, 4, 1),
+
+ DEF_GEN3_SD("sd0", R8A77980_CLK_SD0, CLK_SDSRC, 0x0074),
+
+ DEF_FIXED("cl", R8A77980_CLK_CL, CLK_PLL1_DIV2, 48, 1),
+ DEF_FIXED("cp", R8A77980_CLK_CP, CLK_EXTAL, 2, 1),
+ DEF_FIXED("cpex", R8A77980_CLK_CPEX, CLK_EXTAL, 2, 1),
+
+ DEF_DIV6P1("canfd", R8A77980_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
+ DEF_DIV6P1("csi0", R8A77980_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
+ DEF_DIV6P1("mso", R8A77980_CLK_MSO, CLK_PLL1_DIV4, 0x014),
+};
+
+static const struct mssr_mod_clk r8a77980_mod_clks[] __initconst = {
+ DEF_MOD("tmu4", 121, R8A77980_CLK_S0D6),
+ DEF_MOD("tmu3", 122, R8A77980_CLK_S0D6),
+ DEF_MOD("tmu2", 123, R8A77980_CLK_S0D6),
+ DEF_MOD("tmu1", 124, R8A77980_CLK_S0D6),
+ DEF_MOD("tmu0", 125, R8A77980_CLK_CP),
+ DEF_MOD("scif4", 203, R8A77980_CLK_S3D4),
+ DEF_MOD("scif3", 204, R8A77980_CLK_S3D4),
+ DEF_MOD("scif1", 206, R8A77980_CLK_S3D4),
+ DEF_MOD("scif0", 207, R8A77980_CLK_S3D4),
+ DEF_MOD("msiof3", 208, R8A77980_CLK_MSO),
+ DEF_MOD("msiof2", 209, R8A77980_CLK_MSO),
+ DEF_MOD("msiof1", 210, R8A77980_CLK_MSO),
+ DEF_MOD("msiof0", 211, R8A77980_CLK_MSO),
+ DEF_MOD("sys-dmac2", 217, R8A77980_CLK_S0D3),
+ DEF_MOD("sys-dmac1", 218, R8A77980_CLK_S0D3),
+ DEF_MOD("tpu0", 304, R8A77980_CLK_S3D4),
+ DEF_MOD("sdif", 314, R8A77980_CLK_SD0), /* OK */
+ DEF_MOD("pciec0", 319, R8A77980_CLK_S3D1),
+ DEF_MOD("intc-ex", 407, R8A77980_CLK_CP), /* OK */
+ DEF_MOD("intc-ap", 408, R8A77980_CLK_S0D3),
+ DEF_MOD("hscif3", 517, R8A77980_CLK_S3D1),
+ DEF_MOD("hscif2", 518, R8A77980_CLK_S3D1),
+ DEF_MOD("hscif1", 519, R8A77980_CLK_S3D1),
+ DEF_MOD("hscif0", 520, R8A77980_CLK_S3D1),
+ DEF_MOD("imp4", 521, R8A77980_CLK_S1D1), /* OK? */
+ DEF_MOD("thermal", 522, R8A77980_CLK_CP),
+ DEF_MOD("pwm", 523, R8A77980_CLK_S0D12),
+ DEF_MOD("impdma1", 526, R8A77980_CLK_S1D1),
+ DEF_MOD("impdma0", 527, R8A77980_CLK_S1D1),
+ DEF_MOD("imp-ocv4", 528, R8A77980_CLK_S1D1),
+ DEF_MOD("imp-ocv3", 529, R8A77980_CLK_S1D1),
+ DEF_MOD("imp-ocv2", 531, R8A77980_CLK_S1D1),
+ DEF_MOD("fcpvd0", 603, R8A77980_CLK_S3D1),
+ DEF_MOD("vspd0", 623, R8A77980_CLK_S3D1),
+ DEF_MOD("csi41", 715, R8A77980_CLK_CSI0),
+ DEF_MOD("csi40", 716, R8A77980_CLK_CSI0),
+ DEF_MOD("du0", 724, R8A77980_CLK_S2D1),
+ DEF_MOD("lvds", 727, R8A77980_CLK_S2D1),
+ DEF_MOD("etheravb", 812, R8A77980_CLK_S3D2),
+ DEF_MOD("gether", 813, R8A77980_CLK_S3D2),
+ DEF_MOD("imp3", 824, R8A77980_CLK_S1D1),
+ DEF_MOD("imp2", 825, R8A77980_CLK_S1D1),
+ DEF_MOD("imp1", 826, R8A77980_CLK_S1D1),
+ DEF_MOD("imp0", 827, R8A77980_CLK_S1D1),
+ DEF_MOD("imp-ocv1", 828, R8A77980_CLK_S1D1),
+ DEF_MOD("imp-ocv0", 829, R8A77980_CLK_S1D1),
+ DEF_MOD("impram", 830, R8A77980_CLK_S1D1),
+ DEF_MOD("impcnn", 831, R8A77980_CLK_S1D1),
+ DEF_MOD("gpio5", 907, R8A77980_CLK_CP),
+ DEF_MOD("gpio4", 908, R8A77980_CLK_CP),
+ DEF_MOD("gpio3", 909, R8A77980_CLK_CP),
+ DEF_MOD("gpio2", 910, R8A77980_CLK_CP),
+ DEF_MOD("gpio1", 911, R8A77980_CLK_CP),
+ DEF_MOD("gpio0", 912, R8A77980_CLK_CP),
+ DEF_MOD("can-fd", 914, R8A77980_CLK_S3D2),
+ DEF_MOD("i2c4", 927, R8A77980_CLK_S0D6),
+ DEF_MOD("i2c3", 928, R8A77980_CLK_S0D6),
+ DEF_MOD("i2c2", 929, R8A77980_CLK_S3D2),
+ DEF_MOD("i2c1", 930, R8A77980_CLK_S3D2),
+ DEF_MOD("i2c0", 931, R8A77980_CLK_S3D2),
+};
+
+static const unsigned int r8a77980_crit_mod_clks[] __initconst = {
+ MOD_CLK_ID(408), /* INTC-AP (GIC) */
+};
+
+
+/*
+ * CPG Clock Data
+ */
+
+/*
+ * MD EXTAL PLL2 PLL1 PLL3
+ * 14 13 (MHz)
+ * --------------------------------------------------
+ * 0 0 16.66 x 1 x240 x192 x192
+ * 0 1 20 x 1 x200 x160 x160
+ * 1 0 27 x 1 x148 x118 x118
+ * 1 1 33.33 / 2 x240 x192 x192
+ */
+#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
+ (((md) & BIT(13)) >> 13))
+
+static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[4] __initconst = {
+ /* EXTAL div PLL1 mult/div PLL3 mult/div */
+ { 1, 192, 1, 192, 1, },
+ { 1, 160, 1, 160, 1, },
+ { 1, 118, 1, 118, 1, },
+ { 2, 192, 1, 192, 1, },
+};
+
+static int __init r8a77980_cpg_mssr_init(struct device *dev)
+{
+ const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
+ u32 cpg_mode;
+ int error;
+
+ error = rcar_rst_read_mode_pins(&cpg_mode);
+ if (error)
+ return error;
+
+ cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
+
+ return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
+}
+
+const struct cpg_mssr_info r8a77980_cpg_mssr_info __initconst = {
+ /* Core Clocks */
+ .core_clks = r8a77980_core_clks,
+ .num_core_clks = ARRAY_SIZE(r8a77980_core_clks),
+ .last_dt_core_clk = LAST_DT_CORE_CLK,
+ .num_total_core_clks = MOD_CLK_BASE,
+
+ /* Module Clocks */
+ .mod_clks = r8a77980_mod_clks,
+ .num_mod_clks = ARRAY_SIZE(r8a77980_mod_clks),
+ .num_hw_mod_clks = 12 * 32,
+
+ /* Critical Module Clocks */
+ .crit_mod_clks = r8a77980_crit_mod_clks,
+ .num_crit_mod_clks = ARRAY_SIZE(r8a77980_crit_mod_clks),
+
+ /* Callbacks */
+ .init = r8a77980_cpg_mssr_init,
+ .cpg_clk_register = rcar_gen3_cpg_clk_register,
+};
Index: renesas-drivers/drivers/clk/renesas/renesas-cpg-mssr.c
===================================================================
--- renesas-drivers.orig/drivers/clk/renesas/renesas-cpg-mssr.c
+++ renesas-drivers/drivers/clk/renesas/renesas-cpg-mssr.c
@@ -699,6 +699,12 @@ static const struct of_device_id cpg_mss
.data = &r8a77970_cpg_mssr_info,
},
#endif
+#ifdef CONFIG_ARCH_R8A77980
+ {
+ .compatible = "renesas,r8a77980-cpg-mssr",
+ .data = &r8a77980_cpg_mssr_info,
+ },
+#endif
#ifdef CONFIG_CLK_R8A77995
{
.compatible = "renesas,r8a77995-cpg-mssr",
Index: renesas-drivers/drivers/clk/renesas/renesas-cpg-mssr.h
===================================================================
--- renesas-drivers.orig/drivers/clk/renesas/renesas-cpg-mssr.h
+++ renesas-drivers/drivers/clk/renesas/renesas-cpg-mssr.h
@@ -140,6 +140,7 @@ extern const struct cpg_mssr_info r8a779
extern const struct cpg_mssr_info r8a7795_cpg_mssr_info;
extern const struct cpg_mssr_info r8a7796_cpg_mssr_info;
extern const struct cpg_mssr_info r8a77970_cpg_mssr_info;
+extern const struct cpg_mssr_info r8a77980_cpg_mssr_info;
extern const struct cpg_mssr_info r8a77995_cpg_mssr_info;
--
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^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 2/2] clk: renesas: cpg-mssr: add R8A77980 support
@ 2018-01-31 20:31 ` Sergei Shtylyov
0 siblings, 0 replies; 36+ messages in thread
From: Sergei Shtylyov @ 2018-01-31 20:31 UTC (permalink / raw)
To: Rob Herring, devicetree, linux-renesas-soc, Michael Turquette,
Stephen Boyd, Geert Uytterhoeven, linux-clk
Cc: Mark Rutland
Add R-Car V3H (R8A77980) Clock Pulse Generator / Module Standby and
Software Reset support, using the CPG/MSSR driver core and the common
R-Car Gen3 code.
Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt | 5
drivers/clk/renesas/Kconfig | 5
drivers/clk/renesas/Makefile | 1
drivers/clk/renesas/r8a77980-cpg-mssr.c | 227 +++++++++++
drivers/clk/renesas/renesas-cpg-mssr.c | 6
drivers/clk/renesas/renesas-cpg-mssr.h | 1
6 files changed, 243 insertions(+), 2 deletions(-)
Index: renesas-drivers/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
===================================================================
--- renesas-drivers.orig/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
+++ renesas-drivers/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
@@ -23,6 +23,7 @@ Required Properties:
- "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3)
- "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W)
- "renesas,r8a77970-cpg-mssr" for the r8a77970 SoC (R-Car V3M)
+ - "renesas,r8a77980-cpg-mssr" for the r8a77980 SoC (R-Car V3H)
- "renesas,r8a77995-cpg-mssr" for the r8a77995 SoC (R-Car D3)
- reg: Base address and length of the memory resource used by the CPG/MSSR
@@ -32,8 +33,8 @@ Required Properties:
clock-names
- clock-names: List of external parent clock names. Valid names are:
- "extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7792, r8a7793, r8a7794,
- r8a7795, r8a7796, r8a77970, r8a77995)
- - "extalr" (r8a7795, r8a7796, r8a77970)
+ r8a7795, r8a7796, r8a77970, r8a77980, r8a77995)
+ - "extalr" (r8a7795, r8a7796, r8a77970, r8a77980)
- "usb_extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7793, r8a7794)
- #clock-cells: Must be 2
Index: renesas-drivers/drivers/clk/renesas/Kconfig
===================================================================
--- renesas-drivers.orig/drivers/clk/renesas/Kconfig
+++ renesas-drivers/drivers/clk/renesas/Kconfig
@@ -16,6 +16,7 @@ config CLK_RENESAS
select CLK_R8A7795 if ARCH_R8A7795
select CLK_R8A7796 if ARCH_R8A7796
select CLK_R8A77970 if ARCH_R8A77970
+ select CLK_R8A77980 if ARCH_R8A77980
select CLK_R8A77995 if ARCH_R8A77995
select CLK_SH73A0 if ARCH_SH73A0
@@ -101,6 +102,10 @@ config CLK_R8A77970
bool "R-Car V3M clock support" if COMPILE_TEST
select CLK_RCAR_GEN3_CPG
+config CLK_R8A77980
+ bool "R-Car V3H clock support" if COMPILE_TEST
+ select CLK_RCAR_GEN3_CPG
+
config CLK_R8A77995
bool "R-Car D3 clock support" if COMPILE_TEST
select CLK_RCAR_GEN3_CPG
Index: renesas-drivers/drivers/clk/renesas/Makefile
===================================================================
--- renesas-drivers.orig/drivers/clk/renesas/Makefile
+++ renesas-drivers/drivers/clk/renesas/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_CLK_R8A7794) += r8a7794-cp
obj-$(CONFIG_CLK_R8A7795) += r8a7795-cpg-mssr.o
obj-$(CONFIG_CLK_R8A7796) += r8a7796-cpg-mssr.o
obj-$(CONFIG_CLK_R8A77970) += r8a77970-cpg-mssr.o
+obj-$(CONFIG_CLK_R8A77980) += r8a77980-cpg-mssr.o
obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o
obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o
Index: renesas-drivers/drivers/clk/renesas/r8a77980-cpg-mssr.c
===================================================================
--- /dev/null
+++ renesas-drivers/drivers/clk/renesas/r8a77980-cpg-mssr.c
@@ -0,0 +1,227 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * r8a77980 Clock Pulse Generator / Module Standby and Software Reset
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ * Copyright (C) 2018 Cogent Embedded, Inc.
+ *
+ * Based on r8a7795-cpg-mssr.c
+ *
+ * Copyright (C) 2016 Renesas Electronics Corp.
+ */
+
+#include <linux/device.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/soc/renesas/rcar-rst.h>
+#include <linux/sys_soc.h>
+
+#include <dt-bindings/clock/r8a77980-cpg-mssr.h>
+
+#include "renesas-cpg-mssr.h"
+#include "rcar-gen3-cpg.h"
+
+enum clk_ids {
+ /* Core Clock Outputs exported to DT */
+ LAST_DT_CORE_CLK = R8A77980_CLK_OSC,
+
+ /* External Input Clocks */
+ CLK_EXTAL,
+ CLK_EXTALR,
+
+ /* Internal Core Clocks */
+ CLK_MAIN,
+ CLK_PLL1,
+ CLK_PLL2,
+ CLK_PLL3,
+ CLK_PLL1_DIV2,
+ CLK_PLL1_DIV4,
+ CLK_S0,
+ CLK_S1,
+ CLK_S2,
+ CLK_S3,
+ CLK_SDSRC,
+
+ /* Module Clocks */
+ MOD_CLK_BASE
+};
+
+static const struct cpg_core_clk r8a77980_core_clks[] __initconst = {
+ /* External Clock Inputs */
+ DEF_INPUT("extal", CLK_EXTAL),
+ DEF_INPUT("extalr", CLK_EXTALR),
+
+ /* Internal Core Clocks */
+ DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
+ DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
+ DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
+ DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
+
+ DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
+ DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
+ DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
+ DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1),
+ DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
+ DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
+ DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
+
+ /* Core Clock Outputs */
+ DEF_FIXED("ztr", R8A77980_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
+ DEF_FIXED("ztrd2", R8A77980_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
+ DEF_FIXED("zt", R8A77980_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
+ DEF_FIXED("zx", R8A77980_CLK_ZX, CLK_PLL1_DIV2, 2, 1),
+ DEF_FIXED("s0d1", R8A77980_CLK_S0D1, CLK_S0, 1, 1),
+ DEF_FIXED("s0d2", R8A77980_CLK_S0D2, CLK_S0, 2, 1),
+ DEF_FIXED("s0d3", R8A77980_CLK_S0D3, CLK_S0, 3, 1),
+ DEF_FIXED("s0d4", R8A77980_CLK_S0D4, CLK_S0, 4, 1),
+ DEF_FIXED("s0d6", R8A77980_CLK_S0D6, CLK_S0, 6, 1),
+ DEF_FIXED("s0d12", R8A77980_CLK_S0D12, CLK_S0, 12, 1),
+ DEF_FIXED("s0d24", R8A77980_CLK_S0D24, CLK_S0, 24, 1),
+ DEF_FIXED("s1d1", R8A77980_CLK_S1D1, CLK_S1, 1, 1),
+ DEF_FIXED("s1d2", R8A77980_CLK_S1D2, CLK_S1, 2, 1),
+ DEF_FIXED("s1d4", R8A77980_CLK_S1D4, CLK_S1, 4, 1),
+ DEF_FIXED("s2d1", R8A77980_CLK_S2D1, CLK_S2, 1, 1),
+ DEF_FIXED("s2d2", R8A77980_CLK_S2D2, CLK_S2, 2, 1),
+ DEF_FIXED("s2d4", R8A77980_CLK_S2D4, CLK_S2, 4, 1),
+ DEF_FIXED("s3d1", R8A77980_CLK_S3D1, CLK_S3, 1, 1),
+ DEF_FIXED("s3d2", R8A77980_CLK_S3D2, CLK_S3, 2, 1),
+ DEF_FIXED("s3d4", R8A77980_CLK_S3D4, CLK_S3, 4, 1),
+
+ DEF_GEN3_SD("sd0", R8A77980_CLK_SD0, CLK_SDSRC, 0x0074),
+
+ DEF_FIXED("cl", R8A77980_CLK_CL, CLK_PLL1_DIV2, 48, 1),
+ DEF_FIXED("cp", R8A77980_CLK_CP, CLK_EXTAL, 2, 1),
+ DEF_FIXED("cpex", R8A77980_CLK_CPEX, CLK_EXTAL, 2, 1),
+
+ DEF_DIV6P1("canfd", R8A77980_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
+ DEF_DIV6P1("csi0", R8A77980_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
+ DEF_DIV6P1("mso", R8A77980_CLK_MSO, CLK_PLL1_DIV4, 0x014),
+};
+
+static const struct mssr_mod_clk r8a77980_mod_clks[] __initconst = {
+ DEF_MOD("tmu4", 121, R8A77980_CLK_S0D6),
+ DEF_MOD("tmu3", 122, R8A77980_CLK_S0D6),
+ DEF_MOD("tmu2", 123, R8A77980_CLK_S0D6),
+ DEF_MOD("tmu1", 124, R8A77980_CLK_S0D6),
+ DEF_MOD("tmu0", 125, R8A77980_CLK_CP),
+ DEF_MOD("scif4", 203, R8A77980_CLK_S3D4),
+ DEF_MOD("scif3", 204, R8A77980_CLK_S3D4),
+ DEF_MOD("scif1", 206, R8A77980_CLK_S3D4),
+ DEF_MOD("scif0", 207, R8A77980_CLK_S3D4),
+ DEF_MOD("msiof3", 208, R8A77980_CLK_MSO),
+ DEF_MOD("msiof2", 209, R8A77980_CLK_MSO),
+ DEF_MOD("msiof1", 210, R8A77980_CLK_MSO),
+ DEF_MOD("msiof0", 211, R8A77980_CLK_MSO),
+ DEF_MOD("sys-dmac2", 217, R8A77980_CLK_S0D3),
+ DEF_MOD("sys-dmac1", 218, R8A77980_CLK_S0D3),
+ DEF_MOD("tpu0", 304, R8A77980_CLK_S3D4),
+ DEF_MOD("sdif", 314, R8A77980_CLK_SD0), /* OK */
+ DEF_MOD("pciec0", 319, R8A77980_CLK_S3D1),
+ DEF_MOD("intc-ex", 407, R8A77980_CLK_CP), /* OK */
+ DEF_MOD("intc-ap", 408, R8A77980_CLK_S0D3),
+ DEF_MOD("hscif3", 517, R8A77980_CLK_S3D1),
+ DEF_MOD("hscif2", 518, R8A77980_CLK_S3D1),
+ DEF_MOD("hscif1", 519, R8A77980_CLK_S3D1),
+ DEF_MOD("hscif0", 520, R8A77980_CLK_S3D1),
+ DEF_MOD("imp4", 521, R8A77980_CLK_S1D1), /* OK? */
+ DEF_MOD("thermal", 522, R8A77980_CLK_CP),
+ DEF_MOD("pwm", 523, R8A77980_CLK_S0D12),
+ DEF_MOD("impdma1", 526, R8A77980_CLK_S1D1),
+ DEF_MOD("impdma0", 527, R8A77980_CLK_S1D1),
+ DEF_MOD("imp-ocv4", 528, R8A77980_CLK_S1D1),
+ DEF_MOD("imp-ocv3", 529, R8A77980_CLK_S1D1),
+ DEF_MOD("imp-ocv2", 531, R8A77980_CLK_S1D1),
+ DEF_MOD("fcpvd0", 603, R8A77980_CLK_S3D1),
+ DEF_MOD("vspd0", 623, R8A77980_CLK_S3D1),
+ DEF_MOD("csi41", 715, R8A77980_CLK_CSI0),
+ DEF_MOD("csi40", 716, R8A77980_CLK_CSI0),
+ DEF_MOD("du0", 724, R8A77980_CLK_S2D1),
+ DEF_MOD("lvds", 727, R8A77980_CLK_S2D1),
+ DEF_MOD("etheravb", 812, R8A77980_CLK_S3D2),
+ DEF_MOD("gether", 813, R8A77980_CLK_S3D2),
+ DEF_MOD("imp3", 824, R8A77980_CLK_S1D1),
+ DEF_MOD("imp2", 825, R8A77980_CLK_S1D1),
+ DEF_MOD("imp1", 826, R8A77980_CLK_S1D1),
+ DEF_MOD("imp0", 827, R8A77980_CLK_S1D1),
+ DEF_MOD("imp-ocv1", 828, R8A77980_CLK_S1D1),
+ DEF_MOD("imp-ocv0", 829, R8A77980_CLK_S1D1),
+ DEF_MOD("impram", 830, R8A77980_CLK_S1D1),
+ DEF_MOD("impcnn", 831, R8A77980_CLK_S1D1),
+ DEF_MOD("gpio5", 907, R8A77980_CLK_CP),
+ DEF_MOD("gpio4", 908, R8A77980_CLK_CP),
+ DEF_MOD("gpio3", 909, R8A77980_CLK_CP),
+ DEF_MOD("gpio2", 910, R8A77980_CLK_CP),
+ DEF_MOD("gpio1", 911, R8A77980_CLK_CP),
+ DEF_MOD("gpio0", 912, R8A77980_CLK_CP),
+ DEF_MOD("can-fd", 914, R8A77980_CLK_S3D2),
+ DEF_MOD("i2c4", 927, R8A77980_CLK_S0D6),
+ DEF_MOD("i2c3", 928, R8A77980_CLK_S0D6),
+ DEF_MOD("i2c2", 929, R8A77980_CLK_S3D2),
+ DEF_MOD("i2c1", 930, R8A77980_CLK_S3D2),
+ DEF_MOD("i2c0", 931, R8A77980_CLK_S3D2),
+};
+
+static const unsigned int r8a77980_crit_mod_clks[] __initconst = {
+ MOD_CLK_ID(408), /* INTC-AP (GIC) */
+};
+
+
+/*
+ * CPG Clock Data
+ */
+
+/*
+ * MD EXTAL PLL2 PLL1 PLL3
+ * 14 13 (MHz)
+ * --------------------------------------------------
+ * 0 0 16.66 x 1 x240 x192 x192
+ * 0 1 20 x 1 x200 x160 x160
+ * 1 0 27 x 1 x148 x118 x118
+ * 1 1 33.33 / 2 x240 x192 x192
+ */
+#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
+ (((md) & BIT(13)) >> 13))
+
+static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[4] __initconst = {
+ /* EXTAL div PLL1 mult/div PLL3 mult/div */
+ { 1, 192, 1, 192, 1, },
+ { 1, 160, 1, 160, 1, },
+ { 1, 118, 1, 118, 1, },
+ { 2, 192, 1, 192, 1, },
+};
+
+static int __init r8a77980_cpg_mssr_init(struct device *dev)
+{
+ const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
+ u32 cpg_mode;
+ int error;
+
+ error = rcar_rst_read_mode_pins(&cpg_mode);
+ if (error)
+ return error;
+
+ cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
+
+ return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
+}
+
+const struct cpg_mssr_info r8a77980_cpg_mssr_info __initconst = {
+ /* Core Clocks */
+ .core_clks = r8a77980_core_clks,
+ .num_core_clks = ARRAY_SIZE(r8a77980_core_clks),
+ .last_dt_core_clk = LAST_DT_CORE_CLK,
+ .num_total_core_clks = MOD_CLK_BASE,
+
+ /* Module Clocks */
+ .mod_clks = r8a77980_mod_clks,
+ .num_mod_clks = ARRAY_SIZE(r8a77980_mod_clks),
+ .num_hw_mod_clks = 12 * 32,
+
+ /* Critical Module Clocks */
+ .crit_mod_clks = r8a77980_crit_mod_clks,
+ .num_crit_mod_clks = ARRAY_SIZE(r8a77980_crit_mod_clks),
+
+ /* Callbacks */
+ .init = r8a77980_cpg_mssr_init,
+ .cpg_clk_register = rcar_gen3_cpg_clk_register,
+};
Index: renesas-drivers/drivers/clk/renesas/renesas-cpg-mssr.c
===================================================================
--- renesas-drivers.orig/drivers/clk/renesas/renesas-cpg-mssr.c
+++ renesas-drivers/drivers/clk/renesas/renesas-cpg-mssr.c
@@ -699,6 +699,12 @@ static const struct of_device_id cpg_mss
.data = &r8a77970_cpg_mssr_info,
},
#endif
+#ifdef CONFIG_ARCH_R8A77980
+ {
+ .compatible = "renesas,r8a77980-cpg-mssr",
+ .data = &r8a77980_cpg_mssr_info,
+ },
+#endif
#ifdef CONFIG_CLK_R8A77995
{
.compatible = "renesas,r8a77995-cpg-mssr",
Index: renesas-drivers/drivers/clk/renesas/renesas-cpg-mssr.h
===================================================================
--- renesas-drivers.orig/drivers/clk/renesas/renesas-cpg-mssr.h
+++ renesas-drivers/drivers/clk/renesas/renesas-cpg-mssr.h
@@ -140,6 +140,7 @@ extern const struct cpg_mssr_info r8a779
extern const struct cpg_mssr_info r8a7795_cpg_mssr_info;
extern const struct cpg_mssr_info r8a7796_cpg_mssr_info;
extern const struct cpg_mssr_info r8a77970_cpg_mssr_info;
+extern const struct cpg_mssr_info r8a77980_cpg_mssr_info;
extern const struct cpg_mssr_info r8a77995_cpg_mssr_info;
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 1/2] dt-bindings: clock: add R8A77980 CPG core clock definitions
2018-01-31 20:27 ` Sergei Shtylyov
(?)
@ 2018-02-05 6:08 ` Rob Herring
-1 siblings, 0 replies; 36+ messages in thread
From: Rob Herring @ 2018-02-05 6:08 UTC (permalink / raw)
To: Sergei Shtylyov; +Cc: devicetree, linux-renesas-soc, Mark Rutland
On Wed, Jan 31, 2018 at 11:27:47PM +0300, Sergei Shtylyov wrote:
> Add macros usable by the device tree sources to reference the R8A77980
> CPG core clocks by index. The data come from the table 8.2e of the R-Car
> Series, 3rd Generation User's Manual: Hardware (Rev. 0.80, Oct, 2017),
> however I had to add the Z2 clock which is somehow present only on the
> figure 8.1e...
>
> Based on the original (and large) patch by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>
> ---
> include/dt-bindings/clock/r8a77980-cpg-mssr.h | 51 ++++++++++++++++++++++++++
> 1 file changed, 51 insertions(+)
>
> Index: renesas-drivers/include/dt-bindings/clock/r8a77980-cpg-mssr.h
> ===================================================================
> --- /dev/null
> +++ renesas-drivers/include/dt-bindings/clock/r8a77980-cpg-mssr.h
> @@ -0,0 +1,51 @@
> +/* SPDX-License-Identifier: GPL-2.0+
This should end with ' */' and be its own comment. Otherwise,
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 2/2] clk: renesas: cpg-mssr: add R8A77980 support
2018-01-31 20:31 ` Sergei Shtylyov
(?)
@ 2018-02-05 6:08 ` Rob Herring
-1 siblings, 0 replies; 36+ messages in thread
From: Rob Herring @ 2018-02-05 6:08 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: devicetree, linux-renesas-soc, Michael Turquette, Stephen Boyd,
Geert Uytterhoeven, linux-clk, Mark Rutland
On Wed, Jan 31, 2018 at 11:31:05PM +0300, Sergei Shtylyov wrote:
> Add R-Car V3H (R8A77980) Clock Pulse Generator / Module Standby and
> Software Reset support, using the CPG/MSSR driver core and the common
> R-Car Gen3 code.
>
> Based on the original (and large) patch by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>
> ---
> Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt | 5
Reviewed-by: Rob Herring <robh@kernel.org>
> drivers/clk/renesas/Kconfig | 5
> drivers/clk/renesas/Makefile | 1
> drivers/clk/renesas/r8a77980-cpg-mssr.c | 227 +++++++++++
> drivers/clk/renesas/renesas-cpg-mssr.c | 6
> drivers/clk/renesas/renesas-cpg-mssr.h | 1
> 6 files changed, 243 insertions(+), 2 deletions(-)
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 2/2] clk: renesas: cpg-mssr: add R8A77980 support
2018-01-31 20:31 ` Sergei Shtylyov
(?)
(?)
@ 2018-02-05 8:59 ` Simon Horman
-1 siblings, 0 replies; 36+ messages in thread
From: Simon Horman @ 2018-02-05 8:59 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Rob Herring, devicetree, linux-renesas-soc, Michael Turquette,
Stephen Boyd, Geert Uytterhoeven, linux-clk, Mark Rutland
On Wed, Jan 31, 2018 at 11:31:05PM +0300, Sergei Shtylyov wrote:
> Add R-Car V3H (R8A77980) Clock Pulse Generator / Module Standby and
> Software Reset support, using the CPG/MSSR driver core and the common
> R-Car Gen3 code.
>
> Based on the original (and large) patch by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 1/2] dt-bindings: clock: add R8A77980 CPG core clock definitions
2018-01-31 20:27 ` Sergei Shtylyov
@ 2018-02-05 9:00 ` Simon Horman
-1 siblings, 0 replies; 36+ messages in thread
From: Simon Horman @ 2018-02-05 9:00 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Rob Herring, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA, Mark Rutland
On Wed, Jan 31, 2018 at 11:27:47PM +0300, Sergei Shtylyov wrote:
> Add macros usable by the device tree sources to reference the R8A77980
> CPG core clocks by index. The data come from the table 8.2e of the R-Car
> Series, 3rd Generation User's Manual: Hardware (Rev. 0.80, Oct, 2017),
> however I had to add the Z2 clock which is somehow present only on the
> figure 8.1e...
>
> Based on the original (and large) patch by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>
Reviewed-by: Simon Horman <horms+renesas-/R6kz+dDXgpPR4JQBCEnsQ@public.gmane.org>
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
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^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 1/2] dt-bindings: clock: add R8A77980 CPG core clock definitions
@ 2018-02-05 9:00 ` Simon Horman
0 siblings, 0 replies; 36+ messages in thread
From: Simon Horman @ 2018-02-05 9:00 UTC (permalink / raw)
To: Sergei Shtylyov; +Cc: Rob Herring, devicetree, linux-renesas-soc, Mark Rutland
On Wed, Jan 31, 2018 at 11:27:47PM +0300, Sergei Shtylyov wrote:
> Add macros usable by the device tree sources to reference the R8A77980
> CPG core clocks by index. The data come from the table 8.2e of the R-Car
> Series, 3rd Generation User's Manual: Hardware (Rev. 0.80, Oct, 2017),
> however I had to add the Z2 clock which is somehow present only on the
> figure 8.1e...
>
> Based on the original (and large) patch by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 1/2] dt-bindings: clock: add R8A77980 CPG core clock definitions
2018-01-31 20:27 ` Sergei Shtylyov
@ 2018-02-05 15:01 ` Geert Uytterhoeven
-1 siblings, 0 replies; 36+ messages in thread
From: Geert Uytterhoeven @ 2018-02-05 15:01 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Rob Herring, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA, Mark Rutland
On Wed, Jan 31, 2018 at 9:27 PM, Sergei Shtylyov
<sergei.shtylyov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org> wrote:
> Add macros usable by the device tree sources to reference the R8A77980
> CPG core clocks by index. The data come from the table 8.2e of the R-Car
> Series, 3rd Generation User's Manual: Hardware (Rev. 0.80, Oct, 2017),
> however I had to add the Z2 clock which is somehow present only on the
> figure 8.1e...
>
> Based on the original (and large) patch by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert-Td1EMuHUCqxL1ZNQvxDV9g@public.gmane.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 1/2] dt-bindings: clock: add R8A77980 CPG core clock definitions
@ 2018-02-05 15:01 ` Geert Uytterhoeven
0 siblings, 0 replies; 36+ messages in thread
From: Geert Uytterhoeven @ 2018-02-05 15:01 UTC (permalink / raw)
To: Sergei Shtylyov; +Cc: Rob Herring, devicetree, linux-renesas-soc, Mark Rutland
On Wed, Jan 31, 2018 at 9:27 PM, Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> Add macros usable by the device tree sources to reference the R8A77980
> CPG core clocks by index. The data come from the table 8.2e of the R-Car
> Series, 3rd Generation User's Manual: Hardware (Rev. 0.80, Oct, 2017),
> however I had to add the Z2 clock which is somehow present only on the
> figure 8.1e...
>
> Based on the original (and large) patch by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 2/2] clk: renesas: cpg-mssr: add R8A77980 support
2018-01-31 20:31 ` Sergei Shtylyov
@ 2018-02-05 19:18 ` Geert Uytterhoeven
-1 siblings, 0 replies; 36+ messages in thread
From: Geert Uytterhoeven @ 2018-02-05 19:18 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Rob Herring, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA, Michael Turquette,
Stephen Boyd, Geert Uytterhoeven, linux-clk, Mark Rutland
Hi Sergei,
On Wed, Jan 31, 2018 at 9:31 PM, Sergei Shtylyov
<sergei.shtylyov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org> wrote:
> Add R-Car V3H (R8A77980) Clock Pulse Generator / Module Standby and
> Software Reset support, using the CPG/MSSR driver core and the common
> R-Car Gen3 code.
>
> Based on the original (and large) patch by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>
Thanks for your patch!
> --- /dev/null
> +++ renesas-drivers/drivers/clk/renesas/r8a77980-cpg-mssr.c
> @@ -0,0 +1,227 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * r8a77980 Clock Pulse Generator / Module Standby and Software Reset
> + *
> + * Copyright (C) 2018 Renesas Electronics Corp.
> + * Copyright (C) 2018 Cogent Embedded, Inc.
> + *
> + * Based on r8a7795-cpg-mssr.c
> + *
> + * Copyright (C) 2016 Renesas Electronics Corp.
Interesting, the above copyright line isn't present in r8a7795-cpg-mssr.c?
> +static const struct mssr_mod_clk r8a77980_mod_clks[] __initconst = {
> + DEF_MOD("tmu4", 121, R8A77980_CLK_S0D6),
> + DEF_MOD("tmu3", 122, R8A77980_CLK_S0D6),
> + DEF_MOD("tmu2", 123, R8A77980_CLK_S0D6),
> + DEF_MOD("tmu1", 124, R8A77980_CLK_S0D6),
> + DEF_MOD("tmu0", 125, R8A77980_CLK_CP),
> + DEF_MOD("scif4", 203, R8A77980_CLK_S3D4),
> + DEF_MOD("scif3", 204, R8A77980_CLK_S3D4),
> + DEF_MOD("scif1", 206, R8A77980_CLK_S3D4),
> + DEF_MOD("scif0", 207, R8A77980_CLK_S3D4),
> + DEF_MOD("msiof3", 208, R8A77980_CLK_MSO),
> + DEF_MOD("msiof2", 209, R8A77980_CLK_MSO),
> + DEF_MOD("msiof1", 210, R8A77980_CLK_MSO),
> + DEF_MOD("msiof0", 211, R8A77980_CLK_MSO),
> + DEF_MOD("sys-dmac2", 217, R8A77980_CLK_S0D3),
> + DEF_MOD("sys-dmac1", 218, R8A77980_CLK_S0D3),
> + DEF_MOD("tpu0", 304, R8A77980_CLK_S3D4),
> + DEF_MOD("sdif", 314, R8A77980_CLK_SD0), /* OK */
Please remove the "OK" comment.
> + DEF_MOD("pciec0", 319, R8A77980_CLK_S3D1),
> + DEF_MOD("intc-ex", 407, R8A77980_CLK_CP), /* OK */
Please remove the "OK" comment.
> + DEF_MOD("intc-ap", 408, R8A77980_CLK_S0D3),
> + DEF_MOD("hscif3", 517, R8A77980_CLK_S3D1),
> + DEF_MOD("hscif2", 518, R8A77980_CLK_S3D1),
> + DEF_MOD("hscif1", 519, R8A77980_CLK_S3D1),
> + DEF_MOD("hscif0", 520, R8A77980_CLK_S3D1),
> + DEF_MOD("imp4", 521, R8A77980_CLK_S1D1), /* OK? */
Please remove the "OK" comment.
I couldn't verify all parent clocks though, especially for multimedia-related
blocks.
With the above fixed:
Reviewed-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert-Td1EMuHUCqxL1ZNQvxDV9g@public.gmane.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 2/2] clk: renesas: cpg-mssr: add R8A77980 support
@ 2018-02-05 19:18 ` Geert Uytterhoeven
0 siblings, 0 replies; 36+ messages in thread
From: Geert Uytterhoeven @ 2018-02-05 19:18 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Rob Herring, devicetree, linux-renesas-soc, Michael Turquette,
Stephen Boyd, Geert Uytterhoeven, linux-clk, Mark Rutland
Hi Sergei,
On Wed, Jan 31, 2018 at 9:31 PM, Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> Add R-Car V3H (R8A77980) Clock Pulse Generator / Module Standby and
> Software Reset support, using the CPG/MSSR driver core and the common
> R-Car Gen3 code.
>
> Based on the original (and large) patch by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Thanks for your patch!
> --- /dev/null
> +++ renesas-drivers/drivers/clk/renesas/r8a77980-cpg-mssr.c
> @@ -0,0 +1,227 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * r8a77980 Clock Pulse Generator / Module Standby and Software Reset
> + *
> + * Copyright (C) 2018 Renesas Electronics Corp.
> + * Copyright (C) 2018 Cogent Embedded, Inc.
> + *
> + * Based on r8a7795-cpg-mssr.c
> + *
> + * Copyright (C) 2016 Renesas Electronics Corp.
Interesting, the above copyright line isn't present in r8a7795-cpg-mssr.c?
> +static const struct mssr_mod_clk r8a77980_mod_clks[] __initconst = {
> + DEF_MOD("tmu4", 121, R8A77980_CLK_S0D6),
> + DEF_MOD("tmu3", 122, R8A77980_CLK_S0D6),
> + DEF_MOD("tmu2", 123, R8A77980_CLK_S0D6),
> + DEF_MOD("tmu1", 124, R8A77980_CLK_S0D6),
> + DEF_MOD("tmu0", 125, R8A77980_CLK_CP),
> + DEF_MOD("scif4", 203, R8A77980_CLK_S3D4),
> + DEF_MOD("scif3", 204, R8A77980_CLK_S3D4),
> + DEF_MOD("scif1", 206, R8A77980_CLK_S3D4),
> + DEF_MOD("scif0", 207, R8A77980_CLK_S3D4),
> + DEF_MOD("msiof3", 208, R8A77980_CLK_MSO),
> + DEF_MOD("msiof2", 209, R8A77980_CLK_MSO),
> + DEF_MOD("msiof1", 210, R8A77980_CLK_MSO),
> + DEF_MOD("msiof0", 211, R8A77980_CLK_MSO),
> + DEF_MOD("sys-dmac2", 217, R8A77980_CLK_S0D3),
> + DEF_MOD("sys-dmac1", 218, R8A77980_CLK_S0D3),
> + DEF_MOD("tpu0", 304, R8A77980_CLK_S3D4),
> + DEF_MOD("sdif", 314, R8A77980_CLK_SD0), /* OK */
Please remove the "OK" comment.
> + DEF_MOD("pciec0", 319, R8A77980_CLK_S3D1),
> + DEF_MOD("intc-ex", 407, R8A77980_CLK_CP), /* OK */
Please remove the "OK" comment.
> + DEF_MOD("intc-ap", 408, R8A77980_CLK_S0D3),
> + DEF_MOD("hscif3", 517, R8A77980_CLK_S3D1),
> + DEF_MOD("hscif2", 518, R8A77980_CLK_S3D1),
> + DEF_MOD("hscif1", 519, R8A77980_CLK_S3D1),
> + DEF_MOD("hscif0", 520, R8A77980_CLK_S3D1),
> + DEF_MOD("imp4", 521, R8A77980_CLK_S1D1), /* OK? */
Please remove the "OK" comment.
I couldn't verify all parent clocks though, especially for multimedia-related
blocks.
With the above fixed:
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH] clk: renesas: r8a77970: add SD0H/SD0 clocks for SDHI
2018-01-31 20:23 ` Sergei Shtylyov
` (2 preceding siblings ...)
(?)
@ 2018-08-21 16:41 ` Sergei Shtylyov
2018-08-28 8:58 ` Geert Uytterhoeven
-1 siblings, 1 reply; 36+ messages in thread
From: Sergei Shtylyov @ 2018-08-21 16:41 UTC (permalink / raw)
To: linux-renesas-soc, Michael Turquette, Stephen Boyd,
Geert Uytterhoeven, linux-clk
On R-Car V3M (AKA R8A77970), the SD0CKCR is laid out differently than on
the other R-Car gen3 SoCs. In fact, the layout is the same as on R-Car gen2
SoCs, so we'll need to copy the divisor tables from the R-Car gen2 driver.
We'll also need to support the SoC specific clock types, thus we're adding
CLK_TYPE_GEN3_SOC_BASE at the end of 'enum rcar_gen3_clk_types', declare
SD0H/SDH clocks in 'enum r8a77970_clk_types', and handle those clocks in
the overridden cpg_clk_register() method; then, finally, add the SD-IF
module clock (derived from the SD0 clock).
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
This patch is against the 'clk-renesas' branch of Geert's 'renesas-drivers.git'
repo.
drivers/clk/renesas/r8a77970-cpg-mssr.c | 64 +++++++++++++++++++++++++++++++-
drivers/clk/renesas/rcar-gen3-cpg.h | 3 +
2 files changed, 65 insertions(+), 2 deletions(-)
Index: renesas-drivers/drivers/clk/renesas/r8a77970-cpg-mssr.c
===================================================================
--- renesas-drivers.orig/drivers/clk/renesas/r8a77970-cpg-mssr.c
+++ renesas-drivers/drivers/clk/renesas/r8a77970-cpg-mssr.c
@@ -1,7 +1,7 @@
/*
* r8a77970 Clock Pulse Generator / Module Standby and Software Reset
*
- * Copyright (C) 2017 Cogent Embedded Inc.
+ * Copyright (C) 2017-2018 Cogent Embedded Inc.
*
* Based on r8a7795-cpg-mssr.c
*
@@ -12,6 +12,7 @@
* the Free Software Foundation; version 2 of the License.
*/
+#include <linux/clk-provider.h>
#include <linux/device.h>
#include <linux/init.h>
#include <linux/kernel.h>
@@ -22,6 +23,11 @@
#include "renesas-cpg-mssr.h"
#include "rcar-gen3-cpg.h"
+enum r8a77970_clk_types {
+ CLK_TYPE_R8A77970_SD0H = CLK_TYPE_GEN3_SOC_BASE,
+ CLK_TYPE_R8A77970_SD0,
+};
+
enum clk_ids {
/* Core Clock Outputs exported to DT */
LAST_DT_CORE_CLK = R8A77970_CLK_OSC,
@@ -42,6 +48,20 @@ enum clk_ids {
MOD_CLK_BASE
};
+static spinlock_t cpg_lock;
+
+static const struct clk_div_table cpg_sd0h_div_table[] = {
+ { 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 },
+ { 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 },
+ { 8, 24 }, { 10, 36 }, { 11, 48 }, { 0, 0 },
+};
+
+static const struct clk_div_table cpg_sd0_div_table[] = {
+ { 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 },
+ { 8, 24 }, { 10, 36 }, { 11, 48 }, { 12, 10 },
+ { 0, 0 },
+};
+
static const struct cpg_core_clk r8a77970_core_clks[] __initconst = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
@@ -68,6 +88,10 @@ static const struct cpg_core_clk r8a7797
DEF_FIXED("s2d2", R8A77970_CLK_S2D2, CLK_PLL1_DIV2, 12, 1),
DEF_FIXED("s2d4", R8A77970_CLK_S2D4, CLK_PLL1_DIV2, 24, 1),
+ DEF_BASE("sd0h", R8A77970_CLK_SD0H, CLK_TYPE_R8A77970_SD0H,
+ CLK_PLL1_DIV2),
+ DEF_BASE("sd0", R8A77970_CLK_SD0, CLK_TYPE_R8A77970_SD0, CLK_PLL1_DIV2),
+
DEF_FIXED("cl", R8A77970_CLK_CL, CLK_PLL1_DIV2, 48, 1),
DEF_FIXED("cp", R8A77970_CLK_CP, CLK_EXTAL, 2, 1),
@@ -92,6 +116,7 @@ static const struct mssr_mod_clk r8a7797
DEF_MOD("mfis", 213, R8A77970_CLK_S2D2),
DEF_MOD("sys-dmac2", 217, R8A77970_CLK_S2D1),
DEF_MOD("sys-dmac1", 218, R8A77970_CLK_S2D1),
+ DEF_MOD("sd-if", 314, R8A77970_CLK_SD0),
DEF_MOD("rwdt", 402, R8A77970_CLK_R),
DEF_MOD("intc-ex", 407, R8A77970_CLK_CP),
DEF_MOD("intc-ap", 408, R8A77970_CLK_S2D1),
@@ -173,11 +198,46 @@ static int __init r8a77970_cpg_mssr_init
if (error)
return error;
+ spin_lock_init(&cpg_lock);
+
cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
}
+struct clk * __init r8a77970_cpg_clk_register(struct device *dev,
+ const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
+ struct clk **clks, void __iomem *base,
+ struct raw_notifier_head *notifiers)
+{
+ const struct clk_div_table *table;
+ const struct clk *parent;
+ unsigned int shift;
+
+ switch (core->type) {
+ case CLK_TYPE_R8A77970_SD0H:
+ table = cpg_sd0h_div_table;
+ shift = 8;
+ break;
+ case CLK_TYPE_R8A77970_SD0:
+ table = cpg_sd0_div_table;
+ shift = 4;
+ break;
+ default:
+ return rcar_gen3_cpg_clk_register(dev, core, info, clks, base,
+ notifiers);
+ }
+
+ parent = clks[core->parent];
+ if (IS_ERR(parent))
+ return ERR_CAST(parent);
+
+ return clk_register_divider_table(NULL, core->name,
+ __clk_get_name(parent), 0,
+ base + 0x74, shift, 4, 0, table,
+ &cpg_lock);
+}
+
const struct cpg_mssr_info r8a77970_cpg_mssr_info __initconst = {
/* Core Clocks */
.core_clks = r8a77970_core_clks,
@@ -196,5 +256,5 @@ const struct cpg_mssr_info r8a77970_cpg_
/* Callbacks */
.init = r8a77970_cpg_mssr_init,
- .cpg_clk_register = rcar_gen3_cpg_clk_register,
+ .cpg_clk_register = r8a77970_cpg_clk_register,
};
Index: renesas-drivers/drivers/clk/renesas/rcar-gen3-cpg.h
===================================================================
--- renesas-drivers.orig/drivers/clk/renesas/rcar-gen3-cpg.h
+++ renesas-drivers/drivers/clk/renesas/rcar-gen3-cpg.h
@@ -25,6 +25,9 @@ enum rcar_gen3_clk_types {
CLK_TYPE_GEN3_Z2,
CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */
CLK_TYPE_GEN3_RCKSEL, /* Select parent/divider using RCKCR.CKSEL */
+
+ /* SoC specific definitions start here */
+ CLK_TYPE_GEN3_SOC_BASE,
};
#define DEF_GEN3_SD(_name, _id, _parent, _offset) \
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH] clk: renesas: r8a77970: add SD0H/SD0 clocks for SDHI
2018-08-21 16:41 ` [PATCH] clk: renesas: r8a77970: add SD0H/SD0 clocks for SDHI Sergei Shtylyov
@ 2018-08-28 8:58 ` Geert Uytterhoeven
0 siblings, 0 replies; 36+ messages in thread
From: Geert Uytterhoeven @ 2018-08-28 8:58 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Linux-Renesas, Michael Turquette, Stephen Boyd,
Geert Uytterhoeven, linux-clk
Hi Sergei,
On Tue, Aug 21, 2018 at 6:41 PM Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> On R-Car V3M (AKA R8A77970), the SD0CKCR is laid out differently than on
> the other R-Car gen3 SoCs. In fact, the layout is the same as on R-Car gen2
> SoCs, so we'll need to copy the divisor tables from the R-Car gen2 driver.
> We'll also need to support the SoC specific clock types, thus we're adding
> CLK_TYPE_GEN3_SOC_BASE at the end of 'enum rcar_gen3_clk_types', declare
> SD0H/SDH clocks in 'enum r8a77970_clk_types', and handle those clocks in
> the overridden cpg_clk_register() method; then, finally, add the SD-IF
> module clock (derived from the SD0 clock).
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Thanks for your patch!
Looks good to me, but two minor nits below.
> --- renesas-drivers.orig/drivers/clk/renesas/r8a77970-cpg-mssr.c
> +++ renesas-drivers/drivers/clk/renesas/r8a77970-cpg-mssr.c
> @@ -173,11 +198,46 @@ static int __init r8a77970_cpg_mssr_init
> if (error)
> return error;
>
> + spin_lock_init(&cpg_lock);
> +
> cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
>
> return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
> }
>
> +struct clk * __init r8a77970_cpg_clk_register(struct device *dev,
> + const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
> + struct clk **clks, void __iomem *base,
> + struct raw_notifier_head *notifiers)
static
> +{
> + const struct clk_div_table *table;
> + const struct clk *parent;
> + unsigned int shift;
> +
> + switch (core->type) {
> + case CLK_TYPE_R8A77970_SD0H:
> + table = cpg_sd0h_div_table;
> + shift = 8;
> + break;
> + case CLK_TYPE_R8A77970_SD0:
> + table = cpg_sd0_div_table;
> + shift = 4;
> + break;
> + default:
> + return rcar_gen3_cpg_clk_register(dev, core, info, clks, base,
> + notifiers);
> + }
> +
> + parent = clks[core->parent];
> + if (IS_ERR(parent))
> + return ERR_CAST(parent);
> +
> + return clk_register_divider_table(NULL, core->name,
> + __clk_get_name(parent), 0,
> + base + 0x74, shift, 4, 0, table,
CPG_SD0CKCR instead of hardcoded 0x74?
> + &cpg_lock);
> +}
> +
> const struct cpg_mssr_info r8a77970_cpg_mssr_info __initconst = {
> /* Core Clocks */
> .core_clks = r8a77970_core_clks,
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH] clk: renesas: r8a77980: add CMT clocks
2018-01-31 20:23 ` Sergei Shtylyov
` (3 preceding siblings ...)
(?)
@ 2018-09-01 18:54 ` Sergei Shtylyov
2018-09-03 7:48 ` Geert Uytterhoeven
-1 siblings, 1 reply; 36+ messages in thread
From: Sergei Shtylyov @ 2018-09-01 18:54 UTC (permalink / raw)
To: linux-renesas-soc, Michael Turquette, Stephen Boyd,
Geert Uytterhoeven, linux-clk
Now that RCLK has been added by Geert, we can add the CMT module clocks.
Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
This patch is against the 'clk-renesas' branch of Geert's 'renesas-drivers.git'
repo.
drivers/clk/renesas/r8a77980-cpg-mssr.c | 4 ++++
1 file changed, 4 insertions(+)
Index: renesas-drivers/drivers/clk/renesas/r8a77980-cpg-mssr.c
===================================================================
--- renesas-drivers.orig/drivers/clk/renesas/r8a77980-cpg-mssr.c
+++ renesas-drivers/drivers/clk/renesas/r8a77980-cpg-mssr.c
@@ -119,6 +119,10 @@ static const struct mssr_mod_clk r8a7798
DEF_MOD("msiof0", 211, R8A77980_CLK_MSO),
DEF_MOD("sys-dmac2", 217, R8A77980_CLK_S0D3),
DEF_MOD("sys-dmac1", 218, R8A77980_CLK_S0D3),
+ DEF_MOD("cmt3", 300, R8A77980_CLK_R),
+ DEF_MOD("cmt2", 301, R8A77980_CLK_R),
+ DEF_MOD("cmt1", 302, R8A77980_CLK_R),
+ DEF_MOD("cmt0", 303, R8A77980_CLK_R),
DEF_MOD("tpu0", 304, R8A77980_CLK_S3D4),
DEF_MOD("sdif", 314, R8A77980_CLK_SD0),
DEF_MOD("pciec0", 319, R8A77980_CLK_S2D2),
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH v2] clk: renesas: r8a77970: add SD0H/SD0 clocks for SDHI
2018-01-31 20:23 ` Sergei Shtylyov
` (4 preceding siblings ...)
(?)
@ 2018-09-01 20:12 ` Sergei Shtylyov
2018-09-03 7:43 ` Geert Uytterhoeven
-1 siblings, 1 reply; 36+ messages in thread
From: Sergei Shtylyov @ 2018-09-01 20:12 UTC (permalink / raw)
To: linux-renesas-soc, Michael Turquette, Stephen Boyd,
Geert Uytterhoeven, linux-clk
On R-Car V3M (AKA R8A77970), the SD0CKCR is laid out differently than on
the other R-Car gen3 SoCs. In fact, the layout is the same as on R-Car gen2
SoCs, so we'll need to copy the divisor tables from the R-Car gen2 driver.
We'll also need to support the SoC specific clock types, thus we're adding
CLK_TYPE_GEN3_SOC_BASE at the end of 'enum rcar_gen3_clk_types', declare
SD0H/SDH clocks in 'enum r8a77970_clk_types', and handle those clocks in
the overridden cpg_clk_register() method; then, finally, add the SD-IF
module clock (derived from the SD0 clock).
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
This patch is against the 'clk-renesas' branch of Geert's 'renesas-drivers.git'
repo.
Changes in version 2:
- made r8a77970_cpg_clk_register() *static*;
- #define'd CPG_SD0CKCR and used it instead of the bare number.
drivers/clk/renesas/r8a77970-cpg-mssr.c | 66 +++++++++++++++++++++++++++++++-
drivers/clk/renesas/rcar-gen3-cpg.h | 3 +
2 files changed, 67 insertions(+), 2 deletions(-)
Index: renesas-drivers/drivers/clk/renesas/r8a77970-cpg-mssr.c
===================================================================
--- renesas-drivers.orig/drivers/clk/renesas/r8a77970-cpg-mssr.c
+++ renesas-drivers/drivers/clk/renesas/r8a77970-cpg-mssr.c
@@ -1,7 +1,7 @@
/*
* r8a77970 Clock Pulse Generator / Module Standby and Software Reset
*
- * Copyright (C) 2017 Cogent Embedded Inc.
+ * Copyright (C) 2017-2018 Cogent Embedded Inc.
*
* Based on r8a7795-cpg-mssr.c
*
@@ -12,6 +12,7 @@
* the Free Software Foundation; version 2 of the License.
*/
+#include <linux/clk-provider.h>
#include <linux/device.h>
#include <linux/init.h>
#include <linux/kernel.h>
@@ -22,6 +23,13 @@
#include "renesas-cpg-mssr.h"
#include "rcar-gen3-cpg.h"
+#define CPG_SD0CKCR 0x0074
+
+enum r8a77970_clk_types {
+ CLK_TYPE_R8A77970_SD0H = CLK_TYPE_GEN3_SOC_BASE,
+ CLK_TYPE_R8A77970_SD0,
+};
+
enum clk_ids {
/* Core Clock Outputs exported to DT */
LAST_DT_CORE_CLK = R8A77970_CLK_OSC,
@@ -42,6 +50,20 @@ enum clk_ids {
MOD_CLK_BASE
};
+static spinlock_t cpg_lock;
+
+static const struct clk_div_table cpg_sd0h_div_table[] = {
+ { 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 },
+ { 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 },
+ { 8, 24 }, { 10, 36 }, { 11, 48 }, { 0, 0 },
+};
+
+static const struct clk_div_table cpg_sd0_div_table[] = {
+ { 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 },
+ { 8, 24 }, { 10, 36 }, { 11, 48 }, { 12, 10 },
+ { 0, 0 },
+};
+
static const struct cpg_core_clk r8a77970_core_clks[] __initconst = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
@@ -68,6 +90,10 @@ static const struct cpg_core_clk r8a7797
DEF_FIXED("s2d2", R8A77970_CLK_S2D2, CLK_PLL1_DIV2, 12, 1),
DEF_FIXED("s2d4", R8A77970_CLK_S2D4, CLK_PLL1_DIV2, 24, 1),
+ DEF_BASE("sd0h", R8A77970_CLK_SD0H, CLK_TYPE_R8A77970_SD0H,
+ CLK_PLL1_DIV2),
+ DEF_BASE("sd0", R8A77970_CLK_SD0, CLK_TYPE_R8A77970_SD0, CLK_PLL1_DIV2),
+
DEF_FIXED("cl", R8A77970_CLK_CL, CLK_PLL1_DIV2, 48, 1),
DEF_FIXED("cp", R8A77970_CLK_CP, CLK_EXTAL, 2, 1),
@@ -92,6 +118,7 @@ static const struct mssr_mod_clk r8a7797
DEF_MOD("mfis", 213, R8A77970_CLK_S2D2),
DEF_MOD("sys-dmac2", 217, R8A77970_CLK_S2D1),
DEF_MOD("sys-dmac1", 218, R8A77970_CLK_S2D1),
+ DEF_MOD("sd-if", 314, R8A77970_CLK_SD0),
DEF_MOD("rwdt", 402, R8A77970_CLK_R),
DEF_MOD("intc-ex", 407, R8A77970_CLK_CP),
DEF_MOD("intc-ap", 408, R8A77970_CLK_S2D1),
@@ -173,11 +200,46 @@ static int __init r8a77970_cpg_mssr_init
if (error)
return error;
+ spin_lock_init(&cpg_lock);
+
cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
}
+static struct clk * __init r8a77970_cpg_clk_register(struct device *dev,
+ const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
+ struct clk **clks, void __iomem *base,
+ struct raw_notifier_head *notifiers)
+{
+ const struct clk_div_table *table;
+ const struct clk *parent;
+ unsigned int shift;
+
+ switch (core->type) {
+ case CLK_TYPE_R8A77970_SD0H:
+ table = cpg_sd0h_div_table;
+ shift = 8;
+ break;
+ case CLK_TYPE_R8A77970_SD0:
+ table = cpg_sd0_div_table;
+ shift = 4;
+ break;
+ default:
+ return rcar_gen3_cpg_clk_register(dev, core, info, clks, base,
+ notifiers);
+ }
+
+ parent = clks[core->parent];
+ if (IS_ERR(parent))
+ return ERR_CAST(parent);
+
+ return clk_register_divider_table(NULL, core->name,
+ __clk_get_name(parent), 0,
+ base + CPG_SD0CKCR,
+ shift, 4, 0, table, &cpg_lock);
+}
+
const struct cpg_mssr_info r8a77970_cpg_mssr_info __initconst = {
/* Core Clocks */
.core_clks = r8a77970_core_clks,
@@ -196,5 +258,5 @@ const struct cpg_mssr_info r8a77970_cpg_
/* Callbacks */
.init = r8a77970_cpg_mssr_init,
- .cpg_clk_register = rcar_gen3_cpg_clk_register,
+ .cpg_clk_register = r8a77970_cpg_clk_register,
};
Index: renesas-drivers/drivers/clk/renesas/rcar-gen3-cpg.h
===================================================================
--- renesas-drivers.orig/drivers/clk/renesas/rcar-gen3-cpg.h
+++ renesas-drivers/drivers/clk/renesas/rcar-gen3-cpg.h
@@ -25,6 +25,9 @@ enum rcar_gen3_clk_types {
CLK_TYPE_GEN3_Z2,
CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */
CLK_TYPE_GEN3_RCKSEL, /* Select parent/divider using RCKCR.CKSEL */
+
+ /* SoC specific definitions start here */
+ CLK_TYPE_GEN3_SOC_BASE,
};
#define DEF_GEN3_SD(_name, _id, _parent, _offset) \
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v2] clk: renesas: r8a77970: add SD0H/SD0 clocks for SDHI
2018-09-01 20:12 ` [PATCH v2] clk: renesas: r8a77970: add SD0H/SD0 clocks for SDHI Sergei Shtylyov
@ 2018-09-03 7:43 ` Geert Uytterhoeven
0 siblings, 0 replies; 36+ messages in thread
From: Geert Uytterhoeven @ 2018-09-03 7:43 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Linux-Renesas, Michael Turquette, Stephen Boyd,
Geert Uytterhoeven, linux-clk
Hi Sergei,
On Sat, Sep 1, 2018 at 10:12 PM Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> On R-Car V3M (AKA R8A77970), the SD0CKCR is laid out differently than on
> the other R-Car gen3 SoCs. In fact, the layout is the same as on R-Car gen2
> SoCs, so we'll need to copy the divisor tables from the R-Car gen2 driver.
> We'll also need to support the SoC specific clock types, thus we're adding
> CLK_TYPE_GEN3_SOC_BASE at the end of 'enum rcar_gen3_clk_types', declare
> SD0H/SDH clocks in 'enum r8a77970_clk_types', and handle those clocks in
> the overridden cpg_clk_register() method; then, finally, add the SD-IF
> module clock (derived from the SD0 clock).
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>
> ---
> This patch is against the 'clk-renesas' branch of Geert's 'renesas-drivers.git'
> repo.
>
> Changes in version 2:
> - made r8a77970_cpg_clk_register() *static*;
> - #define'd CPG_SD0CKCR and used it instead of the bare number.
Thanks for the update!
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in clk-renesas-for-v4.20, with s/add/Add/ in the
oneline-summary,
and
> +static struct clk * __init r8a77970_cpg_clk_register(struct device *dev,
... the TAB after "static" replaced by a space.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH] clk: renesas: r8a77980: add CMT clocks
2018-09-01 18:54 ` [PATCH] clk: renesas: r8a77980: add CMT clocks Sergei Shtylyov
@ 2018-09-03 7:48 ` Geert Uytterhoeven
0 siblings, 0 replies; 36+ messages in thread
From: Geert Uytterhoeven @ 2018-09-03 7:48 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Linux-Renesas, Michael Turquette, Stephen Boyd,
Geert Uytterhoeven, linux-clk
On Sat, Sep 1, 2018 at 8:54 PM Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> Now that RCLK has been added by Geert, we can add the CMT module clocks.
>
> Based on the original (and large) patch by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in clk-renesas-for-v4.20 with s/add/Add/.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH] clk: renesas: r8a77970: add CMT clocks
2018-01-31 20:23 ` Sergei Shtylyov
` (5 preceding siblings ...)
(?)
@ 2018-09-05 16:59 ` Sergei Shtylyov
2018-09-06 8:10 ` Chris Paterson
2018-09-06 11:05 ` Geert Uytterhoeven
-1 siblings, 2 replies; 36+ messages in thread
From: Sergei Shtylyov @ 2018-09-05 16:59 UTC (permalink / raw)
To: linux-renesas-soc, Michael Turquette, Stephen Boyd,
Geert Uytterhoeven, linux-clk
Add the R8A77970 CMT module clocks.
Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
drivers/clk/renesas/r8a77970-cpg-mssr.c | 4 ++++
1 file changed, 4 insertions(+)
Index: renesas/drivers/clk/renesas/r8a77970-cpg-mssr.c
===================================================================
--- renesas.orig/drivers/clk/renesas/r8a77970-cpg-mssr.c
+++ renesas/drivers/clk/renesas/r8a77970-cpg-mssr.c
@@ -118,6 +118,10 @@ static const struct mssr_mod_clk r8a7797
DEF_MOD("mfis", 213, R8A77970_CLK_S2D2),
DEF_MOD("sys-dmac2", 217, R8A77970_CLK_S2D1),
DEF_MOD("sys-dmac1", 218, R8A77970_CLK_S2D1),
+ DEF_MOD("cmt3", 300, R8A77970_CLK_R),
+ DEF_MOD("cmt2", 301, R8A77970_CLK_R),
+ DEF_MOD("cmt1", 302, R8A77970_CLK_R),
+ DEF_MOD("cmt0", 303, R8A77970_CLK_R),
DEF_MOD("sd-if", 314, R8A77970_CLK_SD0),
DEF_MOD("rwdt", 402, R8A77970_CLK_R),
DEF_MOD("intc-ex", 407, R8A77970_CLK_CP),
^ permalink raw reply [flat|nested] 36+ messages in thread
* RE: [PATCH] clk: renesas: r8a77970: add CMT clocks
2018-09-05 16:59 ` [PATCH] clk: renesas: r8a77970: add CMT clocks Sergei Shtylyov
@ 2018-09-06 8:10 ` Chris Paterson
2018-09-06 11:05 ` Geert Uytterhoeven
1 sibling, 0 replies; 36+ messages in thread
From: Chris Paterson @ 2018-09-06 8:10 UTC (permalink / raw)
To: Sergei Shtylyov, linux-renesas-soc, Michael Turquette,
Stephen Boyd, Geert Uytterhoeven, linux-clk
Hello Sergei,
> From: linux-renesas-soc-owner@vger.kernel.org <linux-renesas-soc-
> owner@vger.kernel.org> On Behalf Of Sergei Shtylyov
> Sent: 05 September 2018 18:00
>
> Add the R8A77970 CMT module clocks.
>
> Based on the original (and large) patch by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Chris Paterson <chris.paterson2@renesas.com>
Kind regards, Chris
>
> ---
> drivers/clk/renesas/r8a77970-cpg-mssr.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> Index: renesas/drivers/clk/renesas/r8a77970-cpg-mssr.c
> ==========================================================
> =========
> --- renesas.orig/drivers/clk/renesas/r8a77970-cpg-mssr.c
> +++ renesas/drivers/clk/renesas/r8a77970-cpg-mssr.c
> @@ -118,6 +118,10 @@ static const struct mssr_mod_clk r8a7797
> DEF_MOD("mfis", 213,
> R8A77970_CLK_S2D2),
> DEF_MOD("sys-dmac2", 217,
> R8A77970_CLK_S2D1),
> DEF_MOD("sys-dmac1", 218,
> R8A77970_CLK_S2D1),
> + DEF_MOD("cmt3", 300, R8A77970_CLK_R),
> + DEF_MOD("cmt2", 301, R8A77970_CLK_R),
> + DEF_MOD("cmt1", 302, R8A77970_CLK_R),
> + DEF_MOD("cmt0", 303, R8A77970_CLK_R),
> DEF_MOD("sd-if", 314, R8A77970_CLK_SD0),
> DEF_MOD("rwdt", 402, R8A77970_CLK_R),
> DEF_MOD("intc-ex", 407, R8A77970_CLK_CP),
^ permalink raw reply [flat|nested] 36+ messages in thread
* RE: [PATCH] clk: renesas: r8a77970: add CMT clocks
@ 2018-09-06 8:10 ` Chris Paterson
0 siblings, 0 replies; 36+ messages in thread
From: Chris Paterson @ 2018-09-06 8:10 UTC (permalink / raw)
To: Sergei Shtylyov, linux-renesas-soc, Michael Turquette,
Stephen Boyd, Geert Uytterhoeven, linux-clk
SGVsbG8gU2VyZ2VpLA0KDQo+IEZyb206IGxpbnV4LXJlbmVzYXMtc29jLW93bmVyQHZnZXIua2Vy
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Z2VpLnNodHlseW92QGNvZ2VudGVtYmVkZGVkLmNvbT4NCg0KUmV2aWV3ZWQtYnk6IENocmlzIFBh
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IEluZGV4OiByZW5lc2FzL2RyaXZlcnMvY2xrL3JlbmVzYXMvcjhhNzc5NzAtY3BnLW1zc3IuYw0K
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IAlSOEE3Nzk3MF9DTEtfUzJEMiksDQo+ICAJREVGX01PRCgic3lzLWRtYWMyIiwJCSAyMTcsDQo+
IAlSOEE3Nzk3MF9DTEtfUzJEMSksDQo+ICAJREVGX01PRCgic3lzLWRtYWMxIiwJCSAyMTgsDQo+
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Cj4gKwlERUZfTU9EKCJjbXQxIiwJCQkgMzAyLAlSOEE3Nzk3MF9DTEtfUiksDQo+ICsJREVGX01P
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CSAzMTQsCVI4QTc3OTcwX0NMS19TRDApLA0KPiAgCURFRl9NT0QoInJ3ZHQiLAkJCSA0MDIsCVI4
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S19DUCksDQo=
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH] clk: renesas: r8a77970: add CMT clocks
2018-09-05 16:59 ` [PATCH] clk: renesas: r8a77970: add CMT clocks Sergei Shtylyov
2018-09-06 8:10 ` Chris Paterson
@ 2018-09-06 11:05 ` Geert Uytterhoeven
1 sibling, 0 replies; 36+ messages in thread
From: Geert Uytterhoeven @ 2018-09-06 11:05 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Linux-Renesas, Michael Turquette, Stephen Boyd,
Geert Uytterhoeven, linux-clk
On Wed, Sep 5, 2018 at 6:59 PM Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> Add the R8A77970 CMT module clocks.
>
> Based on the original (and large) patch by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in clk-renesas-for-v4.2.0.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH] clk: renesas: r8a77970: add TMU clocks
2018-01-31 20:23 ` Sergei Shtylyov
` (6 preceding siblings ...)
(?)
@ 2018-09-06 20:28 ` Sergei Shtylyov
2018-09-10 14:10 ` Geert Uytterhoeven
-1 siblings, 1 reply; 36+ messages in thread
From: Sergei Shtylyov @ 2018-09-06 20:28 UTC (permalink / raw)
To: linux-renesas-soc, Michael Turquette, Stephen Boyd,
Geert Uytterhoeven, linux-clk
The TMU clocks weren't present in the original R8A77970 patch by Daisuke
Matsushita, they were added in a later BSP version...
Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
This patch is against the 'clk-renesas' branch of Geert's 'renesas-drivers.git'
repo...
drivers/clk/renesas/r8a77970-cpg-mssr.c | 5 +++++
1 file changed, 5 insertions(+)
Index: renesas-drivers/drivers/clk/renesas/r8a77970-cpg-mssr.c
===================================================================
--- renesas-drivers.orig/drivers/clk/renesas/r8a77970-cpg-mssr.c
+++ renesas-drivers/drivers/clk/renesas/r8a77970-cpg-mssr.c
@@ -106,6 +106,11 @@ static const struct cpg_core_clk r8a7797
};
static const struct mssr_mod_clk r8a77970_mod_clks[] __initconst = {
+ DEF_MOD("tmu4", 121, R8A77970_CLK_S2D2),
+ DEF_MOD("tmu3", 122, R8A77970_CLK_S2D2),
+ DEF_MOD("tmu2", 123, R8A77970_CLK_S2D2),
+ DEF_MOD("tmu1", 124, R8A77970_CLK_S2D2),
+ DEF_MOD("tmu0", 125, R8A77970_CLK_CP),
DEF_MOD("ivcp1e", 127, R8A77970_CLK_S2D1),
DEF_MOD("scif4", 203, R8A77970_CLK_S2D4),
DEF_MOD("scif3", 204, R8A77970_CLK_S2D4),
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH] clk: renesas: r8a77970: add TMU clocks
2018-09-06 20:28 ` [PATCH] clk: renesas: r8a77970: add TMU clocks Sergei Shtylyov
@ 2018-09-10 14:10 ` Geert Uytterhoeven
0 siblings, 0 replies; 36+ messages in thread
From: Geert Uytterhoeven @ 2018-09-10 14:10 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Linux-Renesas, Michael Turquette, Stephen Boyd,
Geert Uytterhoeven, linux-clk
On Thu, Sep 6, 2018 at 10:28 PM Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> The TMU clocks weren't present in the original R8A77970 patch by Daisuke
> Matsushita, they were added in a later BSP version...
>
> Based on the original (and large) patch by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in clk-renesas-for-v4.20.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH] clk: renesas: r8a77970: add TPU clock
2018-01-31 20:23 ` Sergei Shtylyov
` (7 preceding siblings ...)
(?)
@ 2018-09-19 18:10 ` Sergei Shtylyov
2018-09-21 7:27 ` Simon Horman
2018-09-24 8:04 ` Geert Uytterhoeven
-1 siblings, 2 replies; 36+ messages in thread
From: Sergei Shtylyov @ 2018-09-19 18:10 UTC (permalink / raw)
To: linux-renesas-soc, Michael Turquette, Stephen Boyd,
Geert Uytterhoeven, linux-clk
The TPU0 clock wasn't present in the original R8A77970 patch by Daisuke
Matsushita, it was added in a later BSP version...
Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
This patch is against the 'clk-renesas' branch of Geert's 'renesas-drivers.git'
repo...
drivers/clk/renesas/r8a77970-cpg-mssr.c | 1 +
1 file changed, 1 insertion(+)
Index: renesas-drivers/drivers/clk/renesas/r8a77970-cpg-mssr.c
===================================================================
--- renesas-drivers.orig/drivers/clk/renesas/r8a77970-cpg-mssr.c
+++ renesas-drivers/drivers/clk/renesas/r8a77970-cpg-mssr.c
@@ -127,6 +127,7 @@ static const struct mssr_mod_clk r8a7797
DEF_MOD("cmt2", 301, R8A77970_CLK_R),
DEF_MOD("cmt1", 302, R8A77970_CLK_R),
DEF_MOD("cmt0", 303, R8A77970_CLK_R),
+ DEF_MOD("tpu0", 304, R8A77970_CLK_S2D4),
DEF_MOD("sd-if", 314, R8A77970_CLK_SD0),
DEF_MOD("rwdt", 402, R8A77970_CLK_R),
DEF_MOD("intc-ex", 407, R8A77970_CLK_CP),
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH] clk: renesas: r8a77970: add TPU clock
2018-09-19 18:10 ` [PATCH] clk: renesas: r8a77970: add TPU clock Sergei Shtylyov
@ 2018-09-21 7:27 ` Simon Horman
2018-09-24 8:04 ` Geert Uytterhoeven
1 sibling, 0 replies; 36+ messages in thread
From: Simon Horman @ 2018-09-21 7:27 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: linux-renesas-soc, Michael Turquette, Stephen Boyd,
Geert Uytterhoeven, linux-clk
On Wed, Sep 19, 2018 at 09:10:40PM +0300, Sergei Shtylyov wrote:
> The TPU0 clock wasn't present in the original R8A77970 patch by Daisuke
> Matsushita, it was added in a later BSP version...
>
> Based on the original (and large) patch by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
>
> ---
> This patch is against the 'clk-renesas' branch of Geert's 'renesas-drivers.git'
> repo...
>
> drivers/clk/renesas/r8a77970-cpg-mssr.c | 1 +
> 1 file changed, 1 insertion(+)
>
> Index: renesas-drivers/drivers/clk/renesas/r8a77970-cpg-mssr.c
> ===================================================================
> --- renesas-drivers.orig/drivers/clk/renesas/r8a77970-cpg-mssr.c
> +++ renesas-drivers/drivers/clk/renesas/r8a77970-cpg-mssr.c
> @@ -127,6 +127,7 @@ static const struct mssr_mod_clk r8a7797
> DEF_MOD("cmt2", 301, R8A77970_CLK_R),
> DEF_MOD("cmt1", 302, R8A77970_CLK_R),
> DEF_MOD("cmt0", 303, R8A77970_CLK_R),
> + DEF_MOD("tpu0", 304, R8A77970_CLK_S2D4),
> DEF_MOD("sd-if", 314, R8A77970_CLK_SD0),
> DEF_MOD("rwdt", 402, R8A77970_CLK_R),
> DEF_MOD("intc-ex", 407, R8A77970_CLK_CP),
>
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH] clk: renesas: r8a77970: add TPU clock
2018-09-19 18:10 ` [PATCH] clk: renesas: r8a77970: add TPU clock Sergei Shtylyov
2018-09-21 7:27 ` Simon Horman
@ 2018-09-24 8:04 ` Geert Uytterhoeven
1 sibling, 0 replies; 36+ messages in thread
From: Geert Uytterhoeven @ 2018-09-24 8:04 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Linux-Renesas, Michael Turquette, Stephen Boyd,
Geert Uytterhoeven, linux-clk
On Wed, Sep 19, 2018 at 8:10 PM Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> The TPU0 clock wasn't present in the original R8A77970 patch by Daisuke
> Matsushita, it was added in a later BSP version...
>
> Based on the original (and large) patch by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in clk-renesas-for-v4.20.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH] clk: renesas: r8a77970: add RPC clock
2018-01-31 20:23 ` Sergei Shtylyov
@ 2018-11-02 19:25 ` Sergei Shtylyov
-1 siblings, 0 replies; 36+ messages in thread
From: Sergei Shtylyov @ 2018-11-02 19:25 UTC (permalink / raw)
To: linux-renesas-soc, Michael Turquette, Stephen Boyd,
Geert Uytterhoeven, linux-clk
On R-Car V3M (R8A77970), the RPC/RPCD2 clocks are output by the common
divider. Describe them, as well as the RPC-IF module clock.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
This patch is against the 'clk-renesas' branch of Geert Uytterhoeven's
'renesas-drivers.git' repo.
drivers/clk/renesas/r8a77970-cpg-mssr.c | 4 ++++
1 file changed, 4 insertions(+)
Index: renesas/drivers/clk/renesas/r8a77970-cpg-mssr.c
===================================================================
--- renesas.orig/drivers/clk/renesas/r8a77970-cpg-mssr.c
+++ renesas/drivers/clk/renesas/r8a77970-cpg-mssr.c
@@ -94,6 +94,9 @@ static const struct cpg_core_clk r8a7797
CLK_PLL1_DIV2),
DEF_BASE("sd0", R8A77970_CLK_SD0, CLK_TYPE_R8A77970_SD0, CLK_PLL1_DIV2),
+ DEF_FIXED("rpc", R8A77970_CLK_RPC, CLK_PLL1_DIV2, 5, 1),
+ DEF_FIXED("rpcd2", R8A77970_CLK_RPCD2, CLK_PLL1_DIV2, 10, 1),
+
DEF_FIXED("cl", R8A77970_CLK_CL, CLK_PLL1_DIV2, 48, 1),
DEF_FIXED("cp", R8A77970_CLK_CP, CLK_EXTAL, 2, 1),
@@ -155,6 +158,7 @@ static const struct mssr_mod_clk r8a7797
DEF_MOD("gpio1", 911, R8A77970_CLK_CP),
DEF_MOD("gpio0", 912, R8A77970_CLK_CP),
DEF_MOD("can-fd", 914, R8A77970_CLK_S2D2),
+ DEF_MOD("rpc-if", 917, R8A77970_CLK_RPC),
DEF_MOD("i2c4", 927, R8A77970_CLK_S2D2),
DEF_MOD("i2c3", 928, R8A77970_CLK_S2D2),
DEF_MOD("i2c2", 929, R8A77970_CLK_S2D2),
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH] clk: renesas: r8a77970: add RPC clock
@ 2018-11-02 19:25 ` Sergei Shtylyov
0 siblings, 0 replies; 36+ messages in thread
From: Sergei Shtylyov @ 2018-11-02 19:25 UTC (permalink / raw)
To: linux-renesas-soc, Michael Turquette, Stephen Boyd,
Geert Uytterhoeven, linux-clk
On R-Car V3M (R8A77970), the RPC/RPCD2 clocks are output by the common
divider. Describe them, as well as the RPC-IF module clock.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
This patch is against the 'clk-renesas' branch of Geert Uytterhoeven's
'renesas-drivers.git' repo.
drivers/clk/renesas/r8a77970-cpg-mssr.c | 4 ++++
1 file changed, 4 insertions(+)
Index: renesas/drivers/clk/renesas/r8a77970-cpg-mssr.c
===================================================================
--- renesas.orig/drivers/clk/renesas/r8a77970-cpg-mssr.c
+++ renesas/drivers/clk/renesas/r8a77970-cpg-mssr.c
@@ -94,6 +94,9 @@ static const struct cpg_core_clk r8a7797
CLK_PLL1_DIV2),
DEF_BASE("sd0", R8A77970_CLK_SD0, CLK_TYPE_R8A77970_SD0, CLK_PLL1_DIV2),
+ DEF_FIXED("rpc", R8A77970_CLK_RPC, CLK_PLL1_DIV2, 5, 1),
+ DEF_FIXED("rpcd2", R8A77970_CLK_RPCD2, CLK_PLL1_DIV2, 10, 1),
+
DEF_FIXED("cl", R8A77970_CLK_CL, CLK_PLL1_DIV2, 48, 1),
DEF_FIXED("cp", R8A77970_CLK_CP, CLK_EXTAL, 2, 1),
@@ -155,6 +158,7 @@ static const struct mssr_mod_clk r8a7797
DEF_MOD("gpio1", 911, R8A77970_CLK_CP),
DEF_MOD("gpio0", 912, R8A77970_CLK_CP),
DEF_MOD("can-fd", 914, R8A77970_CLK_S2D2),
+ DEF_MOD("rpc-if", 917, R8A77970_CLK_RPC),
DEF_MOD("i2c4", 927, R8A77970_CLK_S2D2),
DEF_MOD("i2c3", 928, R8A77970_CLK_S2D2),
DEF_MOD("i2c2", 929, R8A77970_CLK_S2D2),
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH] clk: renesas: r8a77970: add RPC clock
2018-11-02 19:25 ` Sergei Shtylyov
@ 2018-11-04 8:09 ` Sergei Shtylyov
-1 siblings, 0 replies; 36+ messages in thread
From: Sergei Shtylyov @ 2018-11-04 8:09 UTC (permalink / raw)
To: linux-renesas-soc, Michael Turquette, Stephen Boyd,
Geert Uytterhoeven, linux-clk
Oops, the subject should have "clocks", not "clock".
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH] clk: renesas: r8a77970: add RPC clock
@ 2018-11-04 8:09 ` Sergei Shtylyov
0 siblings, 0 replies; 36+ messages in thread
From: Sergei Shtylyov @ 2018-11-04 8:09 UTC (permalink / raw)
To: linux-renesas-soc, Michael Turquette, Stephen Boyd,
Geert Uytterhoeven, linux-clk
Oops, the subject should have "clocks", not "clock".
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH] clk: renesas: r8a77970: add RPC clock
2018-11-02 19:25 ` Sergei Shtylyov
(?)
(?)
@ 2018-11-05 13:20 ` Geert Uytterhoeven
-1 siblings, 0 replies; 36+ messages in thread
From: Geert Uytterhoeven @ 2018-11-05 13:20 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Linux-Renesas, Michael Turquette, Stephen Boyd,
Geert Uytterhoeven, linux-clk
On Fri, Nov 2, 2018 at 8:25 PM Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> On R-Car V3M (R8A77970), the RPC/RPCD2 clocks are output by the common
> divider. Describe them, as well as the RPC-IF module clock.
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in clk-renesas-for-v4.21, with s/add/Add/ and s/clock/clocks/.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 36+ messages in thread
end of thread, other threads:[~2018-11-05 22:40 UTC | newest]
Thread overview: 36+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-01-31 20:23 [PATCH 0/2] Renesas R8A77980 CPG/MSSR clock support Sergei Shtylyov
2018-01-31 20:23 ` Sergei Shtylyov
[not found] ` <5b7895ac-11c1-ac2d-837b-56726bc6226a-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>
2018-01-31 20:27 ` [PATCH 1/2] dt-bindings: clock: add R8A77980 CPG core clock definitions Sergei Shtylyov
2018-01-31 20:27 ` Sergei Shtylyov
2018-02-05 6:08 ` Rob Herring
[not found] ` <4281b305-ff0d-cf56-ce6b-dff4589c39f6-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>
2018-02-05 9:00 ` Simon Horman
2018-02-05 9:00 ` Simon Horman
2018-02-05 15:01 ` Geert Uytterhoeven
2018-02-05 15:01 ` Geert Uytterhoeven
2018-01-31 20:31 ` [PATCH 2/2] clk: renesas: cpg-mssr: add R8A77980 support Sergei Shtylyov
2018-01-31 20:31 ` Sergei Shtylyov
2018-02-05 6:08 ` Rob Herring
2018-02-05 8:59 ` Simon Horman
[not found] ` <9008a12c-e5c8-9289-c47b-50ea9e049c67-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>
2018-02-05 19:18 ` Geert Uytterhoeven
2018-02-05 19:18 ` Geert Uytterhoeven
2018-01-31 20:29 ` [PATCH 0/2] Renesas R8A77980 CPG/MSSR clock support Sergei Shtylyov
2018-08-21 16:41 ` [PATCH] clk: renesas: r8a77970: add SD0H/SD0 clocks for SDHI Sergei Shtylyov
2018-08-28 8:58 ` Geert Uytterhoeven
2018-09-01 18:54 ` [PATCH] clk: renesas: r8a77980: add CMT clocks Sergei Shtylyov
2018-09-03 7:48 ` Geert Uytterhoeven
2018-09-01 20:12 ` [PATCH v2] clk: renesas: r8a77970: add SD0H/SD0 clocks for SDHI Sergei Shtylyov
2018-09-03 7:43 ` Geert Uytterhoeven
2018-09-05 16:59 ` [PATCH] clk: renesas: r8a77970: add CMT clocks Sergei Shtylyov
2018-09-06 8:10 ` Chris Paterson
2018-09-06 8:10 ` Chris Paterson
2018-09-06 11:05 ` Geert Uytterhoeven
2018-09-06 20:28 ` [PATCH] clk: renesas: r8a77970: add TMU clocks Sergei Shtylyov
2018-09-10 14:10 ` Geert Uytterhoeven
2018-09-19 18:10 ` [PATCH] clk: renesas: r8a77970: add TPU clock Sergei Shtylyov
2018-09-21 7:27 ` Simon Horman
2018-09-24 8:04 ` Geert Uytterhoeven
2018-11-02 19:25 ` [PATCH] clk: renesas: r8a77970: add RPC clock Sergei Shtylyov
2018-11-02 19:25 ` Sergei Shtylyov
2018-11-04 8:09 ` Sergei Shtylyov
2018-11-04 8:09 ` Sergei Shtylyov
2018-11-05 13:20 ` Geert Uytterhoeven
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