From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Jan Beulich" Subject: Re: Xen Platform QoS design discussion Date: Fri, 30 May 2014 12:15:11 +0100 Message-ID: <5388764F02000078000B53FA@mail.emea.novell.com> References: <40776A41FC278F40B59438AD47D147A9119F3FEA@SHSMSX104.ccr.corp.intel.com> <5368B418.9000307@citrix.com> <536AA342.8030003@citrix.com> <40776A41FC278F40B59438AD47D147A911A00A4C@SHSMSX104.ccr.corp.intel.com> <536B69AB.7010005@citrix.com> <40776A41FC278F40B59438AD47D147A911A150FC@SHSMSX104.ccr.corp.intel.com> <537A0B17020000780001390F@mail.emea.novell.com> <5379F576.4050108@eu.citrix.com> <537A18260200007800013A06@mail.emea.novell.com> <40776A41FC278F40B59438AD47D147A911A1AAEC@SHSMSX104.ccr.corp.intel.com> <537DD3E60200007800014CFD@mail.emea.novell.com> <537DC2F2.30702@eu.citrix.com> <40776A41FC278F40B59438AD47D147A911A206A4@SHSMSX104.ccr.corp.intel.com> <5386E96402000078000B525D@mail.emea.novell.com> <40776A41FC278F40B59438AD47D147A911A20944@SHSMSX104.ccr.corp.intel.com> <5386FA3C.3010201@citrix.com> <40776A41FC278F40B59438AD47D147A911A20F78@SHSMSX104.ccr.corp.intel.com> <538831F102000078000B534F@mail.emea.novell.com> <40776A41FC278F40B59438AD47D147A911A2121E@SHSMSX104.ccr.corp.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <40776A41FC278F40B59438AD47D147A911A2121E@SHSMSX104.ccr.corp.intel.com> Content-Disposition: inline List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: andrew.cooper3@citrix.com, george.dunlap@eu.citrix.com, dongxiao.xu@intel.com Cc: will.auld@intel.com, Ian.Campbell@citrix.com, jun.nakajima@intel.com, xen-devel@lists.xen.org List-Id: xen-devel@lists.xenproject.org >>> "Xu, Dongxiao" 05/30/14 9:52 AM >>> > From: Jan Beulich [mailto:jbeulich@suse.com] >> Question is whether this mechanism (which I'd like to be done so it can also >> later get added support for e.g. port I/O: see Linux'es dcdbas_smi_request() >> for where this might be useful) should become a sysctl op or - to be >> easily usable by the kernel too - a platform one. > >For CQM, this MSR access hypercall may be somewhat specific, because it >requires one MSR write and one MSR read, which cannot be split into two >separate hypercalls to avoid preemption in the middle. Sure - you'd need a flag to suppress preemption between two specific (batched) operations. Jan