From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48605) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wrs1t-0000oy-A6 for qemu-devel@nongnu.org; Tue, 03 Jun 2014 12:57:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Wrs1n-000722-94 for qemu-devel@nongnu.org; Tue, 03 Jun 2014 12:57:41 -0400 Message-ID: <538DFE7B.5010606@gmail.com> Date: Tue, 03 Jun 2014 11:57:31 -0500 From: Tom Musta MIME-Version: 1.0 References: <1401787684-31895-1-git-send-email-aik@ozlabs.ru> <1401787684-31895-19-git-send-email-aik@ozlabs.ru> In-Reply-To: <1401787684-31895-19-git-send-email-aik@ozlabs.ru> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v4 18/29] target-ppc: Refactor class init for POWER7/8 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alexey Kardashevskiy , qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Alexander Graf On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote: > This extends init_proc_book3s_64 to support POWER7 and POWER8. > > Signed-off-by: Alexey Kardashevskiy > --- > Changes: > v4: > * added g_assert_not_reached() to default path to catch errors earlier > --- > target-ppc/translate_init.c | 100 +++++++++++++++++++++++++++----------------- > 1 file changed, 61 insertions(+), 39 deletions(-) > > diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c > index b1288f4..17163e7 100644 > --- a/target-ppc/translate_init.c > +++ b/target-ppc/translate_init.c > @@ -7269,6 +7269,9 @@ POWERPC_FAMILY(e600)(ObjectClass *oc, void *data) > enum BOOK3S_CPU_TYPE { > BOOK3S_CPU_970, > BOOK3S_CPU_POWER5PLUS, > + BOOK3S_CPU_POWER6, > + BOOK3S_CPU_POWER7, > + BOOK3S_CPU_POWER8 > }; > > static int check_pow_970 (CPUPPCState *env) > @@ -7575,30 +7578,74 @@ static void init_proc_book3s_64(CPUPPCState *env, int version) > gen_spr_book3s_pmu_hypv(env); > gen_spr_book3s_pmu_user(env); > gen_spr_book3s_dbg(env); > - > - gen_spr_970_hid(env); > - gen_spr_970_hior(env); > - gen_low_BATs(env); > gen_spr_book3s_common(env); > - gen_spr_970_pmu_hypv(env); > - gen_spr_970_pmu_user(env); > > + switch (version) { > + case BOOK3S_CPU_970: > + case BOOK3S_CPU_POWER5PLUS: > + gen_spr_970_hid(env); > + gen_spr_970_hior(env); > + gen_low_BATs(env); > + gen_spr_970_pmu_hypv(env); > + gen_spr_970_pmu_user(env); > + break; It appears the 970/P5+ models now have both the old and the new PMU SPR numbers .... intentional? > + case BOOK3S_CPU_POWER7: > + case BOOK3S_CPU_POWER8: > + gen_spr_book3s_ids(env); > + gen_spr_amr(env); > + gen_spr_book3s_purr(env); > + break; > + default: > + g_assert_not_reached(); > + } > if (version >= BOOK3S_CPU_POWER5PLUS) { > + gen_spr_power5p_common(env); > gen_spr_power5p_lpar(env); > gen_spr_power5p_ear(env); > } else { > gen_spr_970_lpar(env); > } > - > - gen_spr_970_dbg(env); > + if (version == BOOK3S_CPU_970) { > + gen_spr_970_dbg(env); > + } > + if (version >= BOOK3S_CPU_POWER6) { > + gen_spr_power6_common(env); > + gen_spr_power6_dbg(env); > + } > + if (version >= BOOK3S_CPU_POWER8) { > + gen_spr_power8_tce_address_control(env); > + } > #if !defined(CONFIG_USER_ONLY) > - env->slb_nr = 64; > + switch (version) { > + case BOOK3S_CPU_970: > + case BOOK3S_CPU_POWER5PLUS: > + env->slb_nr = 64; > + break; > + case BOOK3S_CPU_POWER7: > + case BOOK3S_CPU_POWER8: > + default: > + env->slb_nr = 32; > + break; > + } > #endif > - init_excp_970(env); > + /* Allocate hardware IRQ controller */ > + switch (version) { > + case BOOK3S_CPU_970: > + case BOOK3S_CPU_POWER5PLUS: > + init_excp_970(env); > + ppc970_irq_init(env); > + break; > + case BOOK3S_CPU_POWER7: > + case BOOK3S_CPU_POWER8: > + init_excp_POWER7(env); > + ppcPOWER7_irq_init(env); > + break; > + default: > + g_assert_not_reached(); > + } > + > env->dcache_line_size = 128; > env->icache_line_size = 128; > - /* Allocate hardware IRQ controller */ > - ppc970_irq_init(env); > } > > static void init_proc_970(CPUPPCState *env) > @@ -7776,29 +7823,7 @@ static Property powerpc_servercpu_properties[] = { > > static void init_proc_POWER7 (CPUPPCState *env) > { > - gen_spr_ne_601(env); > - gen_spr_book3s_altivec(env); > - /* Time base */ > - gen_tbl(env); > - gen_spr_book3s_ids(env); > - gen_spr_book3s_purr(env); > - gen_spr_book3s_common(env); > - gen_spr_power5p_common(env); > - gen_spr_power6_common(env); > - gen_spr_book3s_pmu_hypv(env); > - gen_spr_book3s_pmu_user(env); > - gen_spr_book3s_lpar(env); > - gen_spr_power6_dbg(env); > - gen_spr_amr(env); > -#if !defined(CONFIG_USER_ONLY) > - env->slb_nr = 32; > -#endif > - init_excp_POWER7(env); > - env->dcache_line_size = 128; > - env->icache_line_size = 128; > - > - /* Allocate hardware IRQ controller */ > - ppcPOWER7_irq_init(env); > + init_proc_book3s_64(env, BOOK3S_CPU_POWER7); > } > > POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) > @@ -7925,10 +7950,7 @@ POWERPC_FAMILY(POWER7P)(ObjectClass *oc, void *data) > > static void init_proc_POWER8(CPUPPCState *env) > { > - /* inherit P7 */ > - init_proc_POWER7(env); > - > - gen_spr_power8_tce_address_control(env); > + init_proc_book3s_64(env, BOOK3S_CPU_POWER8); > } > > POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) > Reviewed-by: Tom Musta