From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51542) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WrsCI-0004dr-Vx for qemu-devel@nongnu.org; Tue, 03 Jun 2014 13:08:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WrsCD-0002Tz-0c for qemu-devel@nongnu.org; Tue, 03 Jun 2014 13:08:26 -0400 Message-ID: <538E0101.3030605@gmail.com> Date: Tue, 03 Jun 2014 12:08:17 -0500 From: Tom Musta MIME-Version: 1.0 References: <1401787684-31895-1-git-send-email-aik@ozlabs.ru> <1401787684-31895-22-git-send-email-aik@ozlabs.ru> In-Reply-To: <1401787684-31895-22-git-send-email-aik@ozlabs.ru> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v4 21/29] target-ppc: Enable FSCR facility check for TAR List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alexey Kardashevskiy , qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Alexander Graf On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote: > This makes user-privileged read/write fail if TAR facility is not enabled > in FSCR. > > Since this is the very first check for enabled in FSCR facility, > this also adds gen_fscr_facility_check() for using in spr_write_tar()/ > spr_read_tar(). > > Signed-off-by: Alexey Kardashevskiy > --- > target-ppc/translate_init.c | 29 ++++++++++++++++++++++++++++- > 1 file changed, 28 insertions(+), 1 deletion(-) > > diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c > index 6f0c36b..9b83d56 100644 > --- a/target-ppc/translate_init.c > +++ b/target-ppc/translate_init.c > @@ -7275,6 +7275,21 @@ enum BOOK3S_CPU_TYPE { > BOOK3S_CPU_POWER8 > }; > > +static void gen_fscr_facility_check(void *opaque, int facility_sprn, int bit, > + int sprn, int cause) > +{ > + TCGv_i32 t1 = tcg_const_i32(bit); > + TCGv_i32 t2 = tcg_const_i32(sprn); > + TCGv_i32 t3 = tcg_const_i32(cause); > + > + gen_update_current_nip(opaque); > + gen_helper_fscr_facility_check(cpu_env, t1, t2, t3); > + > + tcg_temp_free_i32(t3); > + tcg_temp_free_i32(t2); > + tcg_temp_free_i32(t1); > +} > + > static int check_pow_970 (CPUPPCState *env) > { > if (env->spr[SPR_HID0] & 0x01C00000) { > @@ -7568,10 +7583,22 @@ static void gen_spr_power6_common(CPUPPCState *env) > 0x00000000); > } > > +static void spr_read_tar(void *opaque, int gprn, int sprn) > +{ > + gen_fscr_facility_check(opaque, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); > + spr_read_generic(opaque, gprn, sprn); > +} > + > +static void spr_write_tar(void *opaque, int sprn, int gprn) > +{ > + gen_fscr_facility_check(opaque, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); > + spr_write_generic(opaque, sprn, gprn); > +} > + > static void gen_spr_power8_tce_address_control(CPUPPCState *env) > { > spr_register(env, SPR_TAR, "TAR", > - &spr_read_generic, &spr_write_generic, > + &spr_read_tar, &spr_write_tar, > &spr_read_generic, &spr_write_generic, > 0x00000000); > } > There are potential impacts to user mode here. If I am reading correctly, TAR would not be accessible in user mode. An obvious fix would be to initialize FSCR to enable TAR access in the user mode build targets.