From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55459) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ws1ct-0001My-W9 for qemu-devel@nongnu.org; Tue, 03 Jun 2014 23:12:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Ws1cj-0004UN-28 for qemu-devel@nongnu.org; Tue, 03 Jun 2014 23:12:31 -0400 Received: from mail-pb0-f47.google.com ([209.85.160.47]:60811) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ws1ci-0004T8-T4 for qemu-devel@nongnu.org; Tue, 03 Jun 2014 23:12:20 -0400 Received: by mail-pb0-f47.google.com with SMTP id rp16so6340013pbb.34 for ; Tue, 03 Jun 2014 20:12:19 -0700 (PDT) Message-ID: <538E8E8E.6050102@ozlabs.ru> Date: Wed, 04 Jun 2014 13:12:14 +1000 From: Alexey Kardashevskiy MIME-Version: 1.0 References: <1401787684-31895-1-git-send-email-aik@ozlabs.ru> <1401787684-31895-28-git-send-email-aik@ozlabs.ru> <538E0E59.7080807@gmail.com> In-Reply-To: <538E0E59.7080807@gmail.com> Content-Type: text/plain; charset=KOI8-R Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v4 27/29] target-ppc: Enable DABRX SPR and limit it to <=POWER7 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Tom Musta , qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Alexander Graf On 06/04/2014 04:05 AM, Tom Musta wrote: > On 6/3/2014 4:28 AM, Alexey Kardashevskiy wrote: >> This adds DABRX SPR. >> >> As DABR(X) are present in POWER CPUs till POWER7 only and POWER8 does not >> have them (as it implements more powerful facility instead), this limits >> DABR/DABRX registration by POWER7 (inclusive). >> >> Signed-off-by: Alexey Kardashevskiy >> --- >> target-ppc/translate_init.c | 9 ++++++++- >> 1 file changed, 8 insertions(+), 1 deletion(-) >> >> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c >> index 237074d..2c076b0 100644 >> --- a/target-ppc/translate_init.c >> +++ b/target-ppc/translate_init.c >> @@ -7415,6 +7415,11 @@ static void gen_spr_book3s_dbg(CPUPPCState *env) >> SPR_NOACCESS, SPR_NOACCESS, >> &spr_read_generic, &spr_write_generic, >> KVM_REG_PPC_DABR, 0x00000000); >> + >> + spr_register_kvm(env, SPR_DABRX, "DABRX", >> + SPR_NOACCESS, SPR_NOACCESS, >> + SPR_NOACCESS, SPR_NOACCESS, >> + KVM_REG_PPC_DABRX, 0x00000000); >> } >> > > Is no read nor write access in any mode what you intended? It appears > to be supervisor read/write in the 970 UM. This is worse actually: 970 says it is super/write and super/read powerisa 2.03..2.04 say it is hypv/write and super/read. powerisa 2.05 and newer say it is hypv/write and hypv/read. I can make it the same as DABR for now and fix this somehow when I'll be adding H_SET_XDABR, will this be ok? >> static void gen_spr_970_dbg(CPUPPCState *env) >> @@ -7784,7 +7789,6 @@ static void init_proc_book3s_64(CPUPPCState *env, int version) >> gen_spr_book3s_altivec(env); >> gen_spr_book3s_pmu_hypv(env); >> gen_spr_book3s_pmu_user(env); >> - gen_spr_book3s_dbg(env); >> gen_spr_book3s_common(env); >> >> switch (version) { >> @@ -7827,6 +7831,9 @@ static void init_proc_book3s_64(CPUPPCState *env, int version) >> gen_spr_power8_pmu_user(env); >> gen_spr_power8_tm(env); >> } >> + if (version < BOOK3S_CPU_POWER8) { >> + gen_spr_book3s_dbg(env); >> + } >> #if !defined(CONFIG_USER_ONLY) >> switch (version) { >> case BOOK3S_CPU_970: >> > -- Alexey