From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48118) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WuhTP-0006Hi-Cr for qemu-devel@nongnu.org; Wed, 11 Jun 2014 08:17:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WuhTJ-0000af-4v for qemu-devel@nongnu.org; Wed, 11 Jun 2014 08:17:47 -0400 Received: from mail-la0-x235.google.com ([2a00:1450:4010:c03::235]:36787) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WuhTI-0000aE-SV for qemu-devel@nongnu.org; Wed, 11 Jun 2014 08:17:41 -0400 Received: by mail-la0-f53.google.com with SMTP id ty20so4826510lab.12 for ; Wed, 11 Jun 2014 05:17:38 -0700 (PDT) Message-ID: <539848E1.9070007@gmail.com> Date: Wed, 11 Jun 2014 16:17:37 +0400 From: Sergey Fedorov MIME-Version: 1.0 References: <1402444514-19658-1-git-send-email-aggelerf@ethz.ch> <1402444514-19658-5-git-send-email-aggelerf@ethz.ch> In-Reply-To: <1402444514-19658-5-git-send-email-aggelerf@ethz.ch> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v3 04/32] target-arm: add arm_is_secure() function List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Fabian Aggeler , qemu-devel@nongnu.org Cc: edgar.iglesias@gmail.com, peter.crosthwaite@xilinx.com, greg.bellows@linaro.org, christoffer.dall@linaro.org, peter.maydell@linaro.org On 11.06.2014 03:54, Fabian Aggeler wrote: > arm_is_secure() function allows to determine CPU security state > if the CPU implements Security Extensions/EL3. > arm_is_secure_below_el3() returns true if CPU is in secure state > below EL3. > > Signed-off-by: Sergey Fedorov > Signed-off-by: Fabian Aggeler > --- > target-arm/cpu.h | 38 ++++++++++++++++++++++++++++++++++++++ > 1 file changed, 38 insertions(+) > > diff --git a/target-arm/cpu.h b/target-arm/cpu.h > index 903aa01..cb0da6b 100644 > --- a/target-arm/cpu.h > +++ b/target-arm/cpu.h > @@ -710,6 +710,44 @@ static inline int arm_feature(CPUARMState *env, int feature) > return (env->features & (1ULL << feature)) != 0; > } > > + > +/* Return true if exception level below EL3 is in secure state */ > +static inline bool arm_is_secure_below_el3(CPUARMState *env) > +{ > +#if !defined(CONFIG_USER_ONLY) > + if (arm_feature(env, ARM_FEATURE_EL3)) { > + return !(env->cp15.scr_el3 & SCR_NS); > + } else if (arm_feature(env, ARM_FEATURE_EL2)) { > + return false; > + } else { > + /* IMPDEF: QEMU defaults to non-secure */ > + return false; > + } > +#else > + return false; > +#endif > +} > + > +/* Return true if the processor is in secure state */ > +static inline bool arm_is_secure(CPUARMState *env) > +{ > +#if !defined(CONFIG_USER_ONLY) > + if (arm_feature(env, ARM_FEATURE_EL3)) { > + if (env->aarch64 && extract32(env->pstate, 2, 2) == 3) { > + /* CPU currently in Aarch64 state and EL3 */ > + return true; > + } else if (!env->aarch64 && > + (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { > + /* CPU currently in Aarch32 state and monitor mode */ > + return true; > + } Hi Fabian, Why don't use arm_current_pl() from patch 6 to determine EL here? Best regards, Sergey > + } > + return arm_is_secure_below_el3(env); > +#else > + return false; > +#endif > +} > + > /* Return true if the specified exception level is running in AArch64 state. */ > static inline bool arm_el_is_aa64(CPUARMState *env, int el) > {